WO2000041074A2 - Apparatus and method for dynamically reconfiguring an io device - Google Patents

Apparatus and method for dynamically reconfiguring an io device Download PDF

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Publication number
WO2000041074A2
WO2000041074A2 PCT/US2000/000177 US0000177W WO0041074A2 WO 2000041074 A2 WO2000041074 A2 WO 2000041074A2 US 0000177 W US0000177 W US 0000177W WO 0041074 A2 WO0041074 A2 WO 0041074A2
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WO
WIPO (PCT)
Prior art keywords
controller
configuration
virtual controllers
determining
modifying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2000/000177
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English (en)
French (fr)
Other versions
WO2000041074A3 (en
WO2000041074A8 (en
Inventor
Raul A. Aguilar
James T. Clee
James E. Guziak
Kevin J. Lynch
Farrukh A. Latif
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
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Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Priority to GB0112729A priority Critical patent/GB2359911B/en
Priority to JP2000592732A priority patent/JP4606589B2/ja
Publication of WO2000041074A2 publication Critical patent/WO2000041074A2/en
Publication of WO2000041074A3 publication Critical patent/WO2000041074A3/en
Publication of WO2000041074A8 publication Critical patent/WO2000041074A8/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/4401Bootstrapping
    • G06F9/4411Configuring for operating with peripheral devices; Loading of device drivers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/25Routing or path finding in a switch fabric
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/35Switches specially adapted for specific applications
    • H04L49/351Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches

Definitions

  • This invention relates to semi-conductor devices and, more particularly, to input/output (IO) controllers.
  • IO controllers provide a connection between a computer operating system and an IO interface.
  • Conventional operating systems create descriptor lists that form the instructions that an IO controller reads and follows in order to do its work.
  • Current implementations of IO controllers include hardware circuits which read and initiate the operations defined in the descriptors. Any significant variation in the descriptor requires a new circuit, consequently rendering existing circuits obsolete. In practice, this creates the situation in which the development of new operating systems and the development of new hardware is delayed because the development of either requires coordination with the other.
  • the operational speed of an IO controller interface is typically fixed and the controller is limited to the bandwidth of the interface.
  • the addition of another interface requires the addition of an add-on board or the redesign of a motherboard to accommodate a new controller interface device. Attempts to increase the bandwidth of an IO device have required modification of the device hardware, precluding the dynamic addition of bandwidth.
  • Modification or addition of hardware to a system has numerous disadvantages including reconfiguration expense, additional hardware expense and possible incompatibility with an existing operating system. Further, the addition of new hardware is performed while a system is turned off, requires a technician to install new hardware, and possibly requires a system administrator to change the operating system to support the new hardware. This process can be difficult, error prone and require expensive, time consuming design and re-qualification.
  • a method for controlling data flow through an IO controller in a computer system.
  • the method includes determining a desired configuration for the IO controller, reprogramming the IO controller to allow for processing of one or more descriptor lists, modifying the configuration of the IO controller to reflect the addition or deletion of one or more virtual controllers, re-enumerating the IO controller, and processing a descriptor list for each of the IO controller and the one or more virtual controllers.
  • the one or more virtual controllers are discovered and initialized during the re-enumeration and are capable of providing the full bandwidth supported by the IO controller.
  • the invention is an integrated circuit device for use as an IO controller comprising a system bus interface, a programmable list processor and a port router.
  • the integrated circuit device is adapted for reconfiguration to add or delete one or more virtual controllers.
  • the virtual controllers provide substantially the full bandwidth supported by the integrated circuit device.
  • the invention may be used in a personal computer system, but can also be applied to other types of compute platforms, including but not limited to information appliances, set-top boxes, cable modems, game consoles, smart appliances, handheld computers, palm-sized computers, embedded control systems, workstations, servers and the like.
  • FIG. 1 is a block diagram of one embodiment of the invention.
  • FIG. 2 is a block diagram of another embodiment of the invention.
  • FIG. 3 is a flow diagram illustrating an embodiment of the method of the invention.
  • FIG. 4 is a block diagram illustrating one embodiment of a port router which can be used with the invention.
  • FIG. 5 is a block diagram illustrating another embodiment of a port router which can be used with the invention.
  • the invention provides an apparatus and method for dynamically reconfiguring an IO device to accommodate changes in data flow protocol and/or host system interaction.
  • the invention permits the addition (or deletion) of a virtual controller creating a new channel that an operating system can use to transfer data.
  • the IO device can then provide dedicated throughput for peripheral devices that require high bandwidth, and can group several low bandwidth devices to produce more efficient data transfer.
  • the invention allows for the installation of a new operating program that can accommodate changes in an operating system, changes in system requirements, problems or bugs in devices, and changes in the data flow protocol.
  • the invention provides a practicable and cost effective solution for integrating additional internal circuitry into a compute platform (i.e. IO controllers).
  • IO controllers create a bridge between an IO stream (bus, interface, network connection) and the operating system drivers in a host computer.
  • the present invention provides a method and apparatus which use programmability to alter the operation of both the IO stream and the operating system interface sides of the bridge.
  • the invention may be applied to IO controllers including but not limited to USB, IEEE- 1394, Fibre Channel, Infmiband and Ethernet.
  • the apparatus and method of the invention can provide increased data flow between peripheral devices and a compute platform. This increased data flow is provided without the need for user intervention and allows for simple installation of complex devices to a compute platform.
  • the invention may be used in a personal computer system, but can also be applied to other types of compute platforms, including but not limited to information appliances, set-top boxes, cable modems, game consoles, smart appliances, handheld computers, palm-sized computers, embedded control systems, workstations, servers and the like.
  • An IO controller according to the invention has a longer market life, permits rapid prototyping and implementing of fixes to bugs, accommodates errors in an operating system's descriptor lists, accommodates improvements in descriptor lists, and permits the incorporation of new types of descriptor operation.
  • the invention reduces the number of different products needed to satisfy the requirements of a wide range of systems.
  • FIGURES The representations of the FIGURES provided herewith are for purposes of illustration only and is not intended to limit the possible implementations of the invention.
  • the number of ports and IO controllers present in a particular system or application may vary based on system requirements.
  • an integrated circuit (IC) device 100 for use as an IO controller having a system bus interface 120, a programmable list processor 1 10, and a port router 130.
  • the system bus interface 120, programmable list processor 1 10, and port router 130 are operatively connected.
  • the port router 130 is also preferably connected to one or more interface ports 140.
  • the IO controller can be reprogrammed or reconfigured to process multiple descriptor lists, unlike existing systems which are "single threaded" or capable of executing only a single descriptor list at one time. This functionality allows the IO controller according to the invention to act in the same manner as multiple discrete hardware controllers.
  • FIG.4 is a block diagram illustrating one embodiment of a port router 400 which can be used with the invention.
  • the port router 400 comprises a controller switch 420, a port switch 440 and connection(s) 450 between the controller switch 420 and port switch 440.
  • Connection(s) 450 comprises a hub element 401.
  • Port router 400 connects Ports A-D to a single controller, Controller A.
  • the controller switch 420, the port switch 440 and the connection(s) 450 each have specific input and output capabilities.
  • the port switch 440 has fixed inputs, 441 - 444, each connected to an interface port.
  • the port switch 440 routes any port to one or more port switch outputs.
  • the port switch 440 has a total number of outputs to support all routing elements. In the example of FIG.
  • the port switch 440 has four outputs for Hub element 401.
  • the Hub element(s) preferably comply with the requirements of the IO interface for a given application. Each Hub element combines it's inputs and provides a single output that is input in the controller switch 420. Some IO interfaces refer to the Hub Element 401 as a bridge, a concentrator or a physical interface. Multiple Hub elements may be used to connect the port switch 440 to controller switch 420.
  • the controller switch 420 preferably has one input for each connection to a Hub element and one input for each direct connection (shown in FIG 2) to the port switch 440.
  • the outputs from the controller switch 420 are fixed to match the number of controllers that are necessary or available in a given application.
  • the controller switch has one input 421 connected to Hub element 401 , and one output 427 connected to Controller A.
  • FIG. 5 illustrates the addition of a new device to Port D of the port router 400 of FIG 4, where the bandwidth capacity for Controller A reaches a threshold.
  • Controller B is added to the system and the connection of Port D through Hub element 201 is removed and a direct connection 502 is added.
  • a device Upon insertion of a device into Port D, the device is detected and it's capacity requirements are reported. This capacity is calculated to be larger than the effective capacity of
  • Controller A A new controller B is added to the system, and the port router 100 is reconfigured to effect the connection of Ports A, B and C to Controller A and Port D only to Controller B.
  • the connection for Port D to the hub element 501 is removed and a new direct connection 502 is created between the port switch 540 and the controller switch 520.
  • the connection to Controller B is created from controller switch output 528. All data flow to and from Port D and the new device flows through this new connection from the port switch output 549 to the controller switch input 522. All data flow from Ports A, B and C continues to have the same routing from port switch outputs 545, 546 and 547 to hub element 501. In this configuration the data flow from Ports A, B and C are combined and delivered to the controller switch input 521.
  • the port switch 400 will preferably start in a default state with certain port inputs connected to a desired Controller.
  • the example of FIG. 4 shows a system having a default state with four Ports, two devices connected to Ports A and B, one Hub Element 401, and one Controller A.
  • a set of hardware registers (not shown) preferably resident in the port router 400, software operating in the system can query the port router 400 and discover the default topology.
  • the system software can effect a change in routing of signals between any combination of Ports and Controllers by programming values in the hardware registers.
  • an event occurs. An event may be a new device being removed or inserted into a Port. This event triggers the software to examine the requirements of the new device.
  • These requirements may include the device's data capacity requirements (bandwidth and latency) and its data style (asynchronous, isochronous, burst, stream).
  • the new requirements are combined with the current set of requirements from devices already installed, and a new preferably optimized topology for routing the ports is computed.
  • the system software causes IO operations to suspend and effect the re-routing between the Ports and IO Controller(s). The system software then resumes IO operations and the optimized routing becomes the new routing until a new event occurs.
  • the port router 400 preferably contains embedded software which allows routing and re-routing to be effected internally without requiring the intervention of system software. This provides the ability for self- monitoring and dynamic load balancing based on the flow of data through the port router 400.
  • an integrated circuit (IC) device 200 for use as an IO controller having a peripheral component interconnect (PCI) bus 220 as the system bus interface, a programmable list processor 210, a port router 230, a data mux 250, and a plurality of FIFO(f ⁇ rst in first out) data buffers 260.
  • PCI peripheral component interconnect
  • One or more interface ports 240 are also preferably connected to the port router 230.
  • Each of the elements are preferably operatively connected to allow data signals and control signals to be transmitted between the elements. When data is received from the interface it preferably passes through a Port
  • the List Processor 210 preferably examines it and determines its disposition. The actions taken on the data element depend on the protocol rules for the interface and will be different for example with Ethernet, USB, IEEE- 1394 and the like. It is preferable that controlling software in the List Processor 210 is responsible for determining a desired configuration.
  • the List Processor 210 preferably performs an action such as but not limited to: transmit the data element to system memory, cause a pending transaction to be completed, cause an error to be transmitted to the system, cause an error to be transmitted to the interface, prepare data for transmission to the interface.
  • All data elements transmitted to and from system memory through the PCIbus 220 preferably pass through the Data Mux 250 element.
  • a data element When a data element is to be transmitted from system memory to the interface, it is preferably received through the PCIbus 220, passed through the data mux 250 and placed into the correct FIFO 260.
  • the List Processor that initiated fetching the data from system memory preferably prepares it for transmission to the interface and monitors the conditions on the interface for the appropriate opportunity for data transmission. If the interface is non responsive or not operational the List Processor 210 preferably may take several actions: save data for later retransmission, report an error to the system, and the like.
  • the List Processor element 210 preferably has many characteristics of a general purpose compute engine such as a microprocessor or microcontroller with adaptations to perform the functions of controlling the flow of data between the Port and system bus. It executes software that preferably is fixed in ROM or that more preferably may be downloaded. The software is preferably written to reflect the manner in which the protocol on the interface is defined, typically following industry standards. It is prefered that the software can also be applied for private interface standards. If for example, the protocol requires that the system transmits a data element and receives an acknowledgment that the data was correctly received, the List Processor element has a software control structure that anticipates the receipt of the acknowledgment, if no acknowledgment is received then perhaps a re-transmission is initiated or an error is transmitted to the system. The exact action depends on the rules of the protocol definition.
  • the system bus 120 may also comprise other multi-master bus structures including but not limited to PCI-X, Infiniband, VMEbus, HubLink, and the like.
  • a common feature of these operating systems is an enumeration phase. During enumeration, the hardware present on a system bus is queried, the data describing the features of the hardware is created and acted upon by operating system software.
  • the operating system used with the invention is preferably capable of performing re-enumeration if requested.
  • the invention has a default configuration that is reported during enumeration.
  • the list processor 1 10 is programmed to process a single list and is configured to report a single IO controller to the operating system. It is also preferred that the default state on start up is the state maintained from before the previous power down.
  • the list processor 110 preferably functions to interpret and act upon the instructions of an operating system.
  • a virtual controller may be created to allow the operating system to understand and act as if multiple instances of discrete IO controller hardware exist.
  • Modifying the hardware description of the IO controller and requesting that the operating system re-enumerate the IO controller allows the creation or deletion of one or more new virtual instance of the IO controller.
  • the dynamic creation of a new IO controller can be performed multiple times, until practical limits (i.e. system bus bandwidth, IO controller number limits, etc) are reached.
  • the determination may be made by the operating system or by a monitoring element (not shown) internal to the IO controller.
  • the determination that the current IO controller configuration should be modified is preferably made based on the existence of one or more predetermined conditions including but not limited to increased or decreased data flow through the IO controller.
  • the determination is preferably based on a number of criteria including but not limited to: the total bandwidth requirements of peripheral devices, the bandwidth requirements of a particular peripheral, the latency requirements of a particular peripheral, the presence of conflicting peripherals, the topology of the peripherals, the addition or removal of a peripheral, the increase or decrease in the bandwidth requirements of an existing peripheral, the increase or decrease in the latency requirements of an existing peripheral, and the such.
  • the operation of the IO controller is then preferably temporarily suspended.
  • the devices attached to the IO controller are suspended (or put to sleep) to stop the data flow.
  • the list processor 1 10 is then preferably programmed to allow the processing of one or more new descriptor lists for each virtual controller added to the system.
  • the descriptor list(s) previously in operation remain intact and are processed along with the new descriptor list(s) when operation resumes.
  • the configuration of the IO controller is modified to reflect the addition or deletion of one or more virtual controllers.
  • the devices connected to the IO controller are re-routed to a desired configuration which provides efficient data paths thus optimizing or improving the data flow through the IO controller. This is typically accomplished by dividing the data flow between the one or more IO controllers.
  • a request is made to the operating system to re-enumerate the IO controller.
  • the virtual controllers are detected, and the operating system queries to discover which devices are connected to which controllers.
  • Descriptor lists are created and the list processor 110 begins to process each descriptor list. The devices may then resume operation. Typically the devices are re-enumerated by the operating system.
  • lists processor 1 10 include multi-threaded execution in which multiple descriptor lists may be operated on simultaneously.
  • Typical operations which can be executed simultaneously by the list processor 1 10 include: fetching from system memory, caching (or fetching descriptors before they are needed to reduce multiple accesses to system memory), validation of the descriptor, preparation of IO hardware for data transfer, construction of data flow protocol elements, fetching or delivering of data from and to system memory, monitoring of data flow for exceptions, monitoring of data flow for completion, termination of descriptor, error processing and cleanup, and reporting results back to the operating system.
  • the method of controlling data flow through an IO controller in a computer system comprises determining a desired configuration for the IO controller, reprogramming the IO controller to allow for processing of one or more descriptor lists, modifying the configuration of the IO controller to reflect the addition or deletion of one or more virtual controllers, re-enumerating the IO controller, and processing a descriptor list for each of the IO controller and the one or more virtual controllers.
  • the one or more virtual controllers are preferably discovered and initialized during the re- enumeration and preferably provide the full bandwidth supported by the IO controller and defined by the interface specification.
  • Modifying the configuration of the IO controller preferably includes creating one or more new configuration descriptors which indicate the presence of the one or more virtual controllers. Connections from the interface ports are preferably rerouted to a desired routing configuration which provides efficient data flow. Determining a desired configuration for the IO controller and modifying the configuration of the IO controller is preferably controlled by drivers in the computer system, or more preferably by firmware embedded in the IO controller. Determining a desired configuration for the IO controller preferably includes determining whether the existing configuration of the IO controller should be changed based on existing conditions and determining an optimized configuration for the IO controller based on the existing conditions.
  • the method of controlling data flow through an IO controller in a computer system comprises entering a reconfiguration mode upon the existence of one or more predetermined conditions, determining a desired configuration for the IO controller, reprogramming the IO controller to allow for processing of one or more descriptor lists, modifying the configuration of the IO controller to reflect the addition or deletion of one or more virtual controllers, re-enumerating the IO controller, and processing a descriptor list for each of the IO controller and the one or more virtual controllers.
  • Entering a reconfiguration mode preferably includes suspending operation of devices connected to the computer system.
  • the predetermined conditions preferably include increased or decreased data flow through the IO controller.
  • the invention is an integrated circuit device for use as an IO controller comprising a system bus interface, a programmable list processor and a port router.
  • the system bus interface, the programmable list processor and the port router are preferably operatively connected.
  • the integrated circuit device is preferably adapted for reconfiguration to add or delete one or more virtual controllers, the virtual controllers providing substantially the full bandwidth supported by the integrated circuit device.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)
  • Bus Control (AREA)
PCT/US2000/000177 1999-01-05 2000-01-05 Apparatus and method for dynamically reconfiguring an io device Ceased WO2000041074A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB0112729A GB2359911B (en) 1999-01-05 2000-01-05 Apparatus and method for dynamically reconfiguring an IO device
JP2000592732A JP4606589B2 (ja) 1999-01-05 2000-01-05 入出力デバイスを動的に再構成する装置及び方法

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US11477299P 1999-01-05 1999-01-05
US11477199P 1999-01-05 1999-01-05
US60/114,771 1999-01-05
US60/114,772 1999-01-05
US11476799P 1999-01-06 1999-01-06
US60/114,767 1999-01-06
US09/477,591 US6199137B1 (en) 1999-01-05 2000-01-04 Method and device for controlling data flow through an IO controller
US09/477,591 2000-01-04

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WO2000041074A2 true WO2000041074A2 (en) 2000-07-13
WO2000041074A3 WO2000041074A3 (en) 2000-11-02
WO2000041074A8 WO2000041074A8 (en) 2001-06-21

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JP (1) JP4606589B2 (enExample)
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Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6266721B1 (en) * 1997-05-13 2001-07-24 Micron Electronics, Inc. System architecture for remote access and control of environmental management
US6338150B1 (en) * 1997-05-13 2002-01-08 Micron Technology, Inc. Diagnostic and managing distributed processor system
US6363497B1 (en) 1997-05-13 2002-03-26 Micron Technology, Inc. System for clustering software applications
US6324608B1 (en) 1997-05-13 2001-11-27 Micron Electronics Method for hot swapping of network components
US6145098A (en) 1997-05-13 2000-11-07 Micron Electronics, Inc. System for displaying system status
US6801971B1 (en) * 1999-09-10 2004-10-05 Agere Systems Inc. Method and system for shared bus access
US6986137B1 (en) * 1999-09-28 2006-01-10 International Business Machines Corporation Method, system and program products for managing logical processors of a computing environment
US6519660B1 (en) * 1999-09-28 2003-02-11 International Business Machines Corporation Method, system and program products for determining I/O configuration entropy
US6546450B1 (en) * 1999-12-22 2003-04-08 Intel Corporation Method and apparatus for sharing a universal serial bus device among multiple computers by switching
US6721821B1 (en) * 2000-04-13 2004-04-13 General Dynamics Information Systems Apparatus for electronic data storage
US20020156914A1 (en) * 2000-05-31 2002-10-24 Lo Waichi C. Controller for managing bandwidth in a communications network
US6772320B1 (en) * 2000-11-17 2004-08-03 Intel Corporation Method and computer program for data conversion in a heterogeneous communications network
US20020075860A1 (en) * 2000-12-19 2002-06-20 Young Gene F. High density serverlets utilizing high speed data bus
US7401126B2 (en) 2001-03-23 2008-07-15 Neteffect, Inc. Transaction switch and network interface adapter incorporating same
US7254647B2 (en) * 2001-03-23 2007-08-07 International Business Machines Corporation Network for decreasing transmit link layer core speed
US6839793B2 (en) * 2001-03-28 2005-01-04 Intel Corporation Method and apparatus to maximize bandwidth availability to USB devices
US20020194407A1 (en) * 2001-04-25 2002-12-19 Kim Hyon T. Maintaining fabric device configuration through dynamic reconfiguration
US6438128B1 (en) * 2001-05-08 2002-08-20 International Business Machines Corporation Alternate use of data packet fields to convey information
US6459698B1 (en) * 2001-06-18 2002-10-01 Advanced Micro Devices, Inc. Supporting mapping of layer 3 priorities in an infiniband ™ network
US6973085B1 (en) * 2001-06-18 2005-12-06 Advanced Micro Devices, Inc. Using application headers to determine InfiniBand™ priorities in an InfiniBand™ network
US6970921B1 (en) * 2001-07-27 2005-11-29 3Com Corporation Network interface supporting virtual paths for quality of service
US7860120B1 (en) 2001-07-27 2010-12-28 Hewlett-Packard Company Network interface supporting of virtual paths for quality of service with dynamic buffer allocation
GB2381709A (en) * 2001-10-30 2003-05-07 Graeme Roy Smith Programmable set-top box and home gateway
TW538364B (en) * 2001-12-10 2003-06-21 Via Tech Inc USB control circuit capable of automatically switching paths
US6963932B2 (en) * 2002-01-30 2005-11-08 Intel Corporation Intermediate driver having a fail-over function for a virtual network interface card in a system utilizing Infiniband architecture
US6766405B2 (en) 2002-03-28 2004-07-20 International Business Machines Corporation Accelerated error detection in a bus bridge circuit
WO2004008313A1 (en) * 2002-07-15 2004-01-22 Axalto Sa Usb device
US7461177B2 (en) * 2002-07-15 2008-12-02 Axalto S.A Device functionalities negotiation, fallback, backward-compatibility, and reduced-capabilities simulation
US6928509B2 (en) * 2002-08-01 2005-08-09 International Business Machines Corporation Method and apparatus for enhancing reliability and scalability of serial storage devices
US7894480B1 (en) 2002-08-27 2011-02-22 Hewlett-Packard Company Computer system and network interface with hardware based rule checking for embedded firewall
US7724740B1 (en) * 2002-08-27 2010-05-25 3Com Corporation Computer system and network interface supporting class of service queues
US7000043B2 (en) * 2002-09-18 2006-02-14 Sun Microsystems, Inc. Methods and apparatus for controlling performance of a communications device
KR100449807B1 (ko) * 2002-12-20 2004-09-22 한국전자통신연구원 호스트 버스 인터페이스를 갖는 데이터 전송 프로토콜제어 시스템
JP3907609B2 (ja) * 2003-04-30 2007-04-18 株式会社ソニー・コンピュータエンタテインメント ゲーム実行方法、ゲーム機、通信方法および通信装置
US7065601B2 (en) * 2003-06-06 2006-06-20 Stmicroelectronics N.V. Interface for prototyping integrated systems
US7398345B2 (en) * 2003-06-12 2008-07-08 Hewlett-Packard Development Company, L.P. Inter-integrated circuit bus router for providing increased security
US8539096B2 (en) * 2003-09-26 2013-09-17 Lsi Corporation Systems and methods for configuring ports of an SAS domain
WO2005064480A2 (de) * 2003-12-30 2005-07-14 Wibu-Systems Ag Verfahren zum steuern eines datenverarbeitungsgeräts
US7284081B2 (en) * 2004-01-27 2007-10-16 Atmel Corporation Method and system for routing data between USB ports
DE102004057756B4 (de) * 2004-11-30 2009-08-06 Advanced Micro Devices Inc., Sunnyvale USB-Steuerungseinrichtung mit OTG-Steuerungseinheit
TW200642210A (en) * 2005-02-08 2006-12-01 Koninkl Philips Electronics Nv Scalable universal serial bus architecture
US7496790B2 (en) * 2005-02-25 2009-02-24 International Business Machines Corporation Method, apparatus, and computer program product for coordinating error reporting and reset utilizing an I/O adapter that supports virtualization
US20060212870A1 (en) * 2005-02-25 2006-09-21 International Business Machines Corporation Association of memory access through protection attributes that are associated to an access control level on a PCI adapter that supports virtualization
US8458280B2 (en) * 2005-04-08 2013-06-04 Intel-Ne, Inc. Apparatus and method for packet transmission over a high speed network supporting remote direct memory access operations
US7782873B2 (en) * 2005-08-23 2010-08-24 Slt Logic, Llc Omni-protocol engine for reconfigurable bit-stream processing in high-speed networks
US8189599B2 (en) * 2005-08-23 2012-05-29 Rpx Corporation Omni-protocol engine for reconfigurable bit-stream processing in high-speed networks
US20070147115A1 (en) * 2005-12-28 2007-06-28 Fong-Long Lin Unified memory and controller
US7519754B2 (en) * 2005-12-28 2009-04-14 Silicon Storage Technology, Inc. Hard disk drive cache memory and playback device
US7889762B2 (en) * 2006-01-19 2011-02-15 Intel-Ne, Inc. Apparatus and method for in-line insertion and removal of markers
US7782905B2 (en) * 2006-01-19 2010-08-24 Intel-Ne, Inc. Apparatus and method for stateless CRC calculation
US20070208820A1 (en) * 2006-02-17 2007-09-06 Neteffect, Inc. Apparatus and method for out-of-order placement and in-order completion reporting of remote direct memory access operations
US8078743B2 (en) * 2006-02-17 2011-12-13 Intel-Ne, Inc. Pipelined processing of RDMA-type network transactions
US8316156B2 (en) * 2006-02-17 2012-11-20 Intel-Ne, Inc. Method and apparatus for interfacing device drivers to single multi-function adapter
US7849232B2 (en) 2006-02-17 2010-12-07 Intel-Ne, Inc. Method and apparatus for using a single multi-function adapter with different operating systems
US8230149B1 (en) 2007-09-26 2012-07-24 Teradici Corporation Method and apparatus for managing a peripheral port of a computer system
US20090296726A1 (en) * 2008-06-03 2009-12-03 Brocade Communications Systems, Inc. ACCESS CONTROL LIST MANAGEMENT IN AN FCoE ENVIRONMENT
US8671228B1 (en) * 2009-10-02 2014-03-11 Qlogic, Corporation System and methods for managing virtual adapter instances
US9135198B2 (en) 2012-10-31 2015-09-15 Avago Technologies General Ip (Singapore) Pte Ltd Methods and structure for serial attached SCSI expanders that self-configure by setting routing attributes of their ports based on SMP requests
US8756345B2 (en) 2012-10-31 2014-06-17 Lsi Corporation Methods and structure for managing protection information with a serial attached SCSI expander
US8782292B2 (en) 2012-10-31 2014-07-15 Lsi Corporation Methods and structure for performing a rebuild of a logical volume with a serial attached SCSI expander
US8904108B2 (en) 2012-10-31 2014-12-02 Lsi Corporation Methods and structure establishing nested Redundant Array of Independent Disks volumes with an expander
US8904119B2 (en) 2012-10-31 2014-12-02 Lsi Corporation Method and structures for performing a migration of a logical volume with a serial attached SCSI expander
US20170168971A1 (en) * 2015-12-15 2017-06-15 Intel IP Corporation Re-enumerating media agnostic devices
CN111610732B (zh) * 2020-04-28 2021-09-24 同方泰德国际科技(北京)有限公司 更换可配置型输入/输出模块的方法、装置及设备

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4939644A (en) * 1983-05-19 1990-07-03 Data General Corporation Input/output controller for controlling the sequencing of the execution of input/output commands in a data processing system
US4750113A (en) * 1985-02-28 1988-06-07 Unisys Corporation Dual function I/O controller
EP0366416B1 (en) * 1988-10-24 1997-01-08 Fujitsu Limited An input and output processing system for a virtual computer
JPH0481144A (ja) * 1990-07-23 1992-03-13 Matsushita Electric Ind Co Ltd ネットワーク制御装置
DE4035610A1 (de) * 1990-11-09 1992-05-14 Basf Ag Verfahren zur herstellung von faserverbundwerkstoffen
US5548782A (en) * 1993-05-07 1996-08-20 National Semiconductor Corporation Apparatus for preventing transferring of data with peripheral device for period of time in response to connection or disconnection of the device with the apparatus
DE69518145T2 (de) * 1994-02-10 2001-03-22 Elonex I.P. Holdings Ltd., London Verzeichnis für ein-/ausgangsdecoder
US5655148A (en) * 1994-05-27 1997-08-05 Microsoft Corporation Method for automatically configuring devices including a network adapter without manual intervention and without prior configuration information
US5671441A (en) * 1994-11-29 1997-09-23 International Business Machines Corporation Method and apparatus for automatic generation of I/O configuration descriptions
JPH09160889A (ja) * 1995-12-11 1997-06-20 Hitachi Ltd マルチプロセッサシステムの制御方法
JP3274604B2 (ja) * 1996-04-26 2002-04-15 インターナショナル・ビジネス・マシーンズ・コーポレーション 周辺デバイスの自動イネーブル方法
JP3671360B2 (ja) * 1996-10-04 2005-07-13 日本電信電話株式会社 パケットルータ処理装置
US5815731A (en) * 1996-10-31 1998-09-29 International Business Machines Corporation Method and system for providing device driver configurations on demand
US5964852A (en) * 1996-11-08 1999-10-12 Rockwell International Corporation Programmable data port interface adapter
US6058445A (en) * 1997-05-13 2000-05-02 Micron Electronics, Inc. Data management method for adding or exchanging components on a running computer
US5892928A (en) * 1997-05-13 1999-04-06 Micron Electronics, Inc. Method for the hot add of a network adapter on a system including a dynamically loaded adapter driver
JP2001167040A (ja) * 1999-12-14 2001-06-22 Hitachi Ltd 記憶サブシステム及び記憶制御装置

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JP2003532165A (ja) 2003-10-28
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GB2359911A (en) 2001-09-05
GB0112729D0 (en) 2001-07-18
GB2359911B (en) 2003-09-24
US6199137B1 (en) 2001-03-06

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