WO2000034985A3 - Verfahren zum strukturieren einer metallhaltigen schicht - Google Patents

Verfahren zum strukturieren einer metallhaltigen schicht Download PDF

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Publication number
WO2000034985A3
WO2000034985A3 PCT/DE1999/003876 DE9903876W WO0034985A3 WO 2000034985 A3 WO2000034985 A3 WO 2000034985A3 DE 9903876 W DE9903876 W DE 9903876W WO 0034985 A3 WO0034985 A3 WO 0034985A3
Authority
WO
WIPO (PCT)
Prior art keywords
structuring
metalliferous layer
metalliferous
layer
oxidant
Prior art date
Application number
PCT/DE1999/003876
Other languages
English (en)
French (fr)
Other versions
WO2000034985A2 (de
Inventor
Stephan Wege
Kerstin Krahl
Original Assignee
Infineon Technologies Ag
Stephan Wege
Kerstin Krahl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Stephan Wege, Kerstin Krahl filed Critical Infineon Technologies Ag
Priority to KR10-2001-7006970A priority Critical patent/KR100417724B1/ko
Priority to JP2000587356A priority patent/JP2002536817A/ja
Priority to EP99964395A priority patent/EP1145286A3/de
Publication of WO2000034985A2 publication Critical patent/WO2000034985A2/de
Priority to US09/873,229 priority patent/US6511918B2/en
Publication of WO2000034985A3 publication Critical patent/WO2000034985A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Es wird ein Verfahren zum Strukturieren einer metallhaltigen Schicht vorgeschlagen. Die metallhaltige Schicht (4) wird dabei unter Verwendung einer Ätzmaske (8) in einer plasmaunterstützten Ätzgasatmosphäre bei einer Temperatur oberhalb von 130 °C in Anwesenheit zumindest einer Halogenverbindung und zumindest eines Oxidationsmittels geätzt, wobei die Konzentration des Oxidationsmittels höher als die Konzentration der Halogenverbindung ist.
PCT/DE1999/003876 1998-12-04 1999-12-03 Verfahren zum strukturieren einer metallhaltigen schicht WO2000034985A2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR10-2001-7006970A KR100417724B1 (ko) 1998-12-04 1999-12-03 금속 함유층의 패터닝 방법
JP2000587356A JP2002536817A (ja) 1998-12-04 1999-12-03 金属含有層を構造化する方法
EP99964395A EP1145286A3 (de) 1998-12-04 1999-12-03 Verfahren zum strukturieren einer metallhaltigen schicht
US09/873,229 US6511918B2 (en) 1998-12-04 2001-06-04 Method of structuring a metal-containing layer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19856082.6 1998-12-04
DE19856082A DE19856082C1 (de) 1998-12-04 1998-12-04 Verfahren zum Strukturieren einer metallhaltigen Schicht

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/873,229 Continuation US6511918B2 (en) 1998-12-04 2001-06-04 Method of structuring a metal-containing layer

Publications (2)

Publication Number Publication Date
WO2000034985A2 WO2000034985A2 (de) 2000-06-15
WO2000034985A3 true WO2000034985A3 (de) 2002-02-14

Family

ID=7890037

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/003876 WO2000034985A2 (de) 1998-12-04 1999-12-03 Verfahren zum strukturieren einer metallhaltigen schicht

Country Status (6)

Country Link
US (1) US6511918B2 (de)
EP (1) EP1145286A3 (de)
JP (1) JP2002536817A (de)
KR (1) KR100417724B1 (de)
DE (1) DE19856082C1 (de)
WO (1) WO2000034985A2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6818493B2 (en) 2001-07-26 2004-11-16 Motorola, Inc. Selective metal oxide removal performed in a reaction chamber in the absence of RF activation
US7358171B2 (en) * 2001-08-30 2008-04-15 Micron Technology, Inc. Method to chemically remove metal impurities from polycide gate sidewalls
JP2007502547A (ja) 2003-05-30 2007-02-08 東京エレクトロン株式会社 Ｈｉｇｈ−ｋ誘電材料をエッチングする方法とシステム。
JP4358556B2 (ja) * 2003-05-30 2009-11-04 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
KR100541152B1 (ko) * 2003-07-18 2006-01-11 매그나칩 반도체 유한회사 반도체 소자의 금속 배선층 형성 방법
DE10338422B4 (de) * 2003-08-18 2007-08-16 Infineon Technologies Ag Selektiver Plasmaätzprozess zur Aluminiumoxid-Strukturierung und dessen Verwendung
US7964512B2 (en) * 2005-08-22 2011-06-21 Applied Materials, Inc. Method for etching high dielectric constant materials
JP5028829B2 (ja) * 2006-03-09 2012-09-19 セイコーエプソン株式会社 強誘電体メモリ装置の製造方法
JP4853057B2 (ja) * 2006-03-09 2012-01-11 セイコーエプソン株式会社 強誘電体メモリ装置の製造方法
US7780862B2 (en) * 2006-03-21 2010-08-24 Applied Materials, Inc. Device and method for etching flash memory gate stacks comprising high-k dielectric
US8722547B2 (en) * 2006-04-20 2014-05-13 Applied Materials, Inc. Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4432132A (en) * 1981-12-07 1984-02-21 Bell Telephone Laboratories, Incorporated Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
EP0547884A1 (de) * 1991-12-18 1993-06-23 Kabushiki Kaisha Toshiba Verfahren zum selektiven Ätzen eines Metall-Oxids auf einem Tantal enthaltenden Material
JPH10178095A (ja) * 1996-07-09 1998-06-30 Nippon Steel Corp 半導体装置及びその製造方法
US5866484A (en) * 1996-07-09 1999-02-02 Nippon Steel Corporation Semiconductor device and process of producing same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4026742A (en) * 1972-11-22 1977-05-31 Katsuhiro Fujino Plasma etching process for making a microcircuit device
US3923568A (en) * 1974-01-14 1975-12-02 Int Plasma Corp Dry plasma process for etching noble metal
US3951709A (en) * 1974-02-28 1976-04-20 Lfe Corporation Process and material for semiconductor photomask fabrication
DE2738839A1 (de) * 1977-08-29 1979-03-15 Siemens Ag Plasma-aetzverfahren fuer chrom- schichten
US4568410A (en) * 1984-12-20 1986-02-04 Motorola, Inc. Selective plasma etching of silicon nitride in the presence of silicon oxide
US5496437A (en) * 1993-06-10 1996-03-05 Ceram Incorporated Reactive ion etching of lead zirconate titanate and ruthenium oxide thin films
JP3238563B2 (ja) 1994-03-16 2001-12-17 株式会社東芝 半導体装置の製造方法
JP2956485B2 (ja) * 1994-09-07 1999-10-04 日本電気株式会社 半導体装置の製造方法
US6350699B1 (en) * 2000-05-30 2002-02-26 Sharp Laboratories Of America, Inc. Method for anisotropic plasma etching using non-chlorofluorocarbon, fluorine-based chemistry

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4432132A (en) * 1981-12-07 1984-02-21 Bell Telephone Laboratories, Incorporated Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
EP0547884A1 (de) * 1991-12-18 1993-06-23 Kabushiki Kaisha Toshiba Verfahren zum selektiven Ätzen eines Metall-Oxids auf einem Tantal enthaltenden Material
JPH10178095A (ja) * 1996-07-09 1998-06-30 Nippon Steel Corp 半導体装置及びその製造方法
US5866484A (en) * 1996-07-09 1999-02-02 Nippon Steel Corporation Semiconductor device and process of producing same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JAE-WHAN KIM ET AL: "REACTIVE ION ETCHING MECHANISM OF PLASMA ENHANCED CHEMICALLY VAPOR DEPOSITED ALUMINUM OXIDE FILM IN CF4/O2 PLASMA", JOURNAL OF APPLIED PHYSICS,US,AMERICAN INSTITUTE OF PHYSICS. NEW YORK, vol. 78, no. 3, 1 August 1995 (1995-08-01), pages 2045 - 2049, XP000541839, ISSN: 0021-8979 *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 11 30 September 1998 (1998-09-30) *

Also Published As

Publication number Publication date
WO2000034985A2 (de) 2000-06-15
US6511918B2 (en) 2003-01-28
KR20010086078A (ko) 2001-09-07
EP1145286A2 (de) 2001-10-17
EP1145286A3 (de) 2002-04-24
DE19856082C1 (de) 2000-07-27
KR100417724B1 (ko) 2004-02-11
US20020011461A1 (en) 2002-01-31
JP2002536817A (ja) 2002-10-29

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