WO2000027061A1 - Dispositif et procede de communication - Google Patents
Dispositif et procede de communication Download PDFInfo
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- WO2000027061A1 WO2000027061A1 PCT/JP1999/002612 JP9902612W WO0027061A1 WO 2000027061 A1 WO2000027061 A1 WO 2000027061A1 JP 9902612 W JP9902612 W JP 9902612W WO 0027061 A1 WO0027061 A1 WO 0027061A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/003—Arrangements for allocating sub-channels of the transmission path
- H04L5/0058—Allocation criteria
- H04L5/006—Quality of the received signal, e.g. BER, SNR, water filling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/003—Arrangements for allocating sub-channels of the transmission path
- H04L5/0044—Arrangements for allocating sub-channels of the transmission path allocation of payload
- H04L5/0046—Determination of how many bits are transmitted on different sub-channels
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/1469—Two-way operation using the same type of signal, i.e. duplex using time-sharing
- H04L5/1484—Two-way operation using the same type of signal, i.e. duplex using time-sharing operating bytewise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M11/00—Telephonic communication systems specially adapted for combination with other electrical systems
- H04M11/06—Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
- H04M11/062—Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors using different frequency bands for speech and other data
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/0001—Arrangements for dividing the transmission path
- H04L5/0003—Two-dimensional division
- H04L5/0005—Time-frequency
- H04L5/0007—Time-frequency the frequencies being orthogonal, e.g. OFDM(A), DMT
Definitions
- the present invention relates to a communication device and a communication method for performing data communication between a plurality of data communication devices via a telephone line, for example, by a discrete multitone modulation / demodulation method.
- ADSL Asymmetric Digital Subscriber Line
- HDSL High-bit-rate Digital Subscriber
- x, SDS L and other xDS L communication systems are attracting attention.
- the xDSL communication method used for this is called DMT (Discrete MultiTone) modulation / demodulation method.
- DMT Discrete MultiTone modulation / demodulation method.
- This method is standardized in ANSI T1.413 and the like.
- the xDSL transmission line is used especially when the xDSL transmission line and the ISDN transmission line of the half-duplex communication type SDN communication system are adjacent to each other, for example, by being bundled by an intermediate line.
- the xDSL communication via the Internet receives interference noise from other lines such as the ISDN transmission line, causing a problem such as a reduction in speed, and various measures have been taken.
- Fig. 19 shows the reason that the ISDN transmission line 2 from the Central Office (CO) 1 and the ADSL transmission line 3 which is an xDSL transmission line are bundled together in an intermediate line. This figure shows the state of interference noise that the I SDN transmission line 2 gives to the ADSL transmission line 3.
- CO Central Office
- an ADSL terminal-side device (ATU-R: ADSL Transceiver Unit, Remote terminal end) 4, which is a communication device on the side of the ADSL communication system, is viewed from the side.
- the interference noise transmitted by the station equipment (ISDN LT) 7 on the ISDN transmission system side through the ADSL transmission line 3 is called FEXT (Far-End cross Talk) noise
- the ISSDN transmission system side The interference noise transmitted by the terminal device (ISDN NT1) 6 through the ADSL transmission line 3 is called NEXT (Near-End cross Talk) noise.
- NEXT Near-End cross Talk
- the ADSL terminal side device (ATU-R) 4 When viewed from the ADSL station side device (ATU-C; ADSL Transceiver Unit, Central office end) 5 which is the station side device of the ADSL communication system side, the ADSL terminal side device (ATU-R) 4 The interference noise transmitted from the station device (ISDN LT) 7 on the ISDN transmission system side becomes NEXT noise, and the terminal device (ISDN NT1) 6 on the ISDN transmission system side.
- the transmitted interference noise is FEXT noise.
- the upstream and downstream transmissions are full-duplex transmissions, and are performed simultaneously. Therefore, when viewed from the ADSL terminal side device (ATU-R) 4, the ADSL terminal NEXT noise generated from the terminal device (ISDN NT1) 6 of the ISDN transmission system close to the side device (ATU-R) 4 is dominant, that is, has a great influence.
- the characteristics of the NEXT noise component that has a large effect are measured, and each of the NEXT noise components matching the noise characteristics is measured.
- a time domain equalizer (TEQ) that performs adaptive equalization processing in the time domain, and a frequency that performs bitmap that determines the number of transmission bits and gain of the channel and improves transmission characteristics
- the coefficients of the frequency domain equalizer (FEQ) that performs the adaptive equalization processing of the area are determined by converging, and one set of coefficient tables for NEXT noise is provided for each of TEQ and FEQ. ing.
- the Japanese ADSL scheme proposes a scheme that switches the bitmap according to the FEXT section and the NEXT section of the TCM-I SDN interference noise ("G. lite: Proposal for draft of Annex of G. lite. ", ITU-T, SG-15, Waikiki, Hawaii 29 June-3 July 1998, Temporary Document WH-047).
- FIG. 20 shows an outline of a digital communication system using a digital communication device adopting the above method.
- 11 is a Central Office (CO) that controls TCM-ISDN communication and ADSL communication, etc.
- 12 is TCM-ISDN transmission line for performing TCM-I SDN communication
- 13 is ADSL ADSL transmission line for communication
- 14 is an ADSL terminal device (ATU-R; ADSL Transce iver) such as a communication modem for performing ADSL communication with another ADSL terminal device (not shown) via the ADSL transmission line 13.
- 15 is an ADSL station unit (ATU-C; ADSL Transceiver Unit, Central of the end) that controls ADSL communication in the central office 11, and 16 is a TCM-I SDN transmission line 12.
- TCM—ISDN terminal equipment such as a communication modem that performs TCM—I SDN communication with other TCM—I SDN terminal equipment (not shown).
- this synchronization controller 18, TCM- I SDN office equipment ( TCM-I SDN LT) 17 or ADSL station side device (ATU-C) 15 may be provided.
- the TCM-I SDN station-side device (far-duplex communication device) TCM—I SDN LT) TCM—I SD 17 is adjacent by a collective line, etc.
- the interference noise transmitted via the N transmission line 12 and the ADSL transmission line 13 is transmitted via the N transmission line 12 and the ADSL transmission line 13
- the interference noise transmitted via the N transmission line 12 and the ADSL transmission line 13 is called "NEXT noise”.
- Interference noise transmitted from the station side device (ISDN LT) 17 of the ISDN transmission system which is a near half-duplex communication device, is the reverse of the case seen from the L terminal side device (ATU-R) 14.
- the interference noise transmitted by the terminal device (ISDN NT1) 16 of the ISDN transmission system which becomes NEXT noise and becomes a far half-duplex communication device, becomes FEXT noise.
- FIG. 21 shows the configuration of a transmission unit such as a communication modem or a transmission-only machine (hereinafter referred to as a transmission system) of an ADSL station unit (ATU-C; central office end) 15 in a digital communication device. Is shown functionally.
- FIG. 22 functionally shows the configuration of a receiving unit such as a communication modem of the ADSL terminal-side device (ATU-R) 14 or a receiving-only device (hereinafter referred to as a receiving system) in the digital communication device.
- ATU-R ADSL terminal-side device
- a receiving-only device hereinafter referred to as a receiving system
- Fig. 21 41 is a multiplex sync control (Mux / Sync Control), 42 and 43 are cyclic redundancy checks (crc :), 44 and 45 are scrambled 'forward error collections (Scrara and FEC), 46 Is Inle Reeve, 47 and 48 are Rate-Convertor, 49 is Tone ordering, 50 is a constellation encoder and gains Constellation encoder and gain seal ling, 51 is an inverse discrete Fourier transform (IDFT), 52 is an input parallel / serial buffer, 53 is an analog processing DZA converter Analog Processing and DAC).
- Mux / Sync Control multiplex sync control
- 42 and 43 are cyclic redundancy checks (crc :)
- 44 and 45 are scrambled 'forward error collections (Scrara and FEC)
- 46 Is Inle Reeve 47 and 48 are Rate-Convertor
- 49 is Tone ordering
- 50 is a constellation encoder and gains Constellation encoder and gain seal ling
- 51
- 14 1 is an analog processing and AZD converter (analog processing and ADC).
- 14 2 is a time domain equalizer (TEC)
- 14 3 is an input serial parallel buffer
- 14 4 is a discrete RFT (DFT)
- 145 is a frequency domain equalizer (FEQ)
- FEQ frequency domain equalizer
- 146 is a constellation encoder and gain sealing
- 147 is a tone ordering.
- 148, 149 are Rate-converters
- 150 are Deinterleave
- 154, 154 are descrambled foreground collections (Descram and FEC)
- 153 and 154 are cyclic redundancy check (crc :)
- 155 is multiplex / sync control (Mux / Sync Control).
- transmission data is multiplexed by a multiplex / sync control (Mux / Sync Control) 41 and cyclically transmitted.
- a code for error detection is added by redundancy 4 2 and 4 3
- a code for FEC is added and descrambling is performed by descrambling and correction 4 4 and 4 5, and in some cases interleaving 4 6 multiply.
- rate conversion processing is performed by the rate converters 47 and 48
- ton order processing is performed by the ton ordering 49
- constellation data is created by the constellation encoder and gain scaling 50
- inverse discrete Fourier transform is performed.
- the inverse discrete Fourier transform is performed by the unit 51, the digital waveform is converted to an analog waveform through a DZA converter, and then a low-pass filter is applied.
- ATU-R ADSL terminal side device
- analog processing and the AZD converter 14 1 A single pass filter is applied to the signal, an analog waveform is converted to a digital waveform through an A / D converter, and then adaptive equalization in the time domain is performed through a time domain equalizer (TEQ) 142.
- TEQ time domain equalizer
- the data subjected to the adaptive equalization processing in the time domain is converted from serial data to parallel data via an input serial / parallel buffer 143, and is subjected to discrete Fourier transform by a discrete Fourier transform unit (DFT) 144.
- the frequency domain adaptive equalizer (FEQ) 145 performs frequency domain adaptive equalization.
- the constellation data is reproduced by the constellation encoder's gain scaling 146, converted to serial data by the tongue ordering 147, rate-converted by the rate converters 148 and 149, and descrambled.
- the FEC or descrambling is performed in the collection 151, and in some cases, Dinterleave 150 is applied to the descrambling, and the FEC or descrambling is performed in the collection 152, and then the cyclic redundancy check 153 or 154 is performed. And play the data with the multiplex sync control (Mux / Sync Control) 155.
- the synchronization controller 18 synchronizes the transmission timing between the TCM—I SDN station device (TCM—I SDN LT) 17 and the ADSL station device (ATU—C) 15.
- the ADSL terminal side device (AT UR) can recognize the generation timing of NEXT noise and FEXT noise.
- the ADSL terminal side device (ATU-R) 14 is moving up on the TCM-ISDN transmission line 12, whose timing is known in advance, due to the synchronization between the TCM-ISDN communication and the ADSL communication.
- the NEXT noise occurs in the received data and the received signal received via the ADSL transmission line 13, while the TCM-I SDN transmission line 12 whose timing is known in advance is also used.
- a FEXT noise is generated during the reception of data via the ADSL transmission line 13 during a predetermined time during which data is falling.
- Japanese ADSL system as shown in Fig.
- bitmaps A and B corresponding to the FEXT section and the NEXT section are allocated, and the rate converters 148 and 149 in Fig.
- the bit allocation is increased in the FEXT section with a small number of bits, and the bit allocation is reduced in the NEXT section with a large amount of noise. As a result, the transmission rate can be increased compared to the case where the bit allocation is determined only in the NEXT section.
- Fig. 24 shows how to allocate data coming in at a uniform rate (64 kbps in the following calculation example) to bitmap A and bitmap B during transmission.
- a uniform rate 64 kbps in the following calculation example
- bitmap A and bitmap B bitmap A and bitmap B during transmission.
- fixed bits are stored for data sent at a uniform rate in symbol units. It is converted into bits for bitmap A and bitmap B by the rate converter.
- the transmission symbol interval is 246 s for an ISDN cycle of 2.5 ms, so it does not become an integral multiple.
- the following is a calculation example for calculating the bit allocation in the case of a single bit map using only bitmap A for data allocation.
- bit assignment for a dual bitmap that uses both bitmap A and bitmap B.
- bitmap A 39 bits.
- transmission data is allocated to the bitmap A portion as much as possible in each hyperframe unit, so that data of one cycle may be replaced by data of a later cycle in some cases. It may be assigned to the bitmap A part, and additional delay time occurs for that data.
- bits are assigned to the bitmap A and the bitmap B of the hyperframe as completely as possible. It can be assigned to a period, and there is an additional delay for that data.
- Such a conventional device has a problem that the delay is excessive.
- an object of the present invention is to provide a communication device and a communication method capable of suppressing a delay. Disclosure of the invention
- a communication device is a communication device that sets a data transmission period that is a period suitable for data transmission within one cycle according to a transmission path and a quasi-data transmission period that is a period other than the data transmission period.
- bits are allocated and transmitted so that data for one cycle can be transmitted in the data transmission period for one cycle, and data is uniform in the data transmission period for one cycle. .
- the communication device includes a data transmission period that is a period suitable for data transmission within one cycle according to a transmission path and a quasi-data transmission period that is a period other than the data transmission period.
- the data transmission period and the quasi-data for one period can be transmitted in the data transmission period and the quasi-data transmission period for one period. Bits are allocated and transmitted so that the data is uniform during each transmission period.
- the communication device sets a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than the data transmission period in one cycle according to the transmission path.
- the bits are allocated and transmitted so that the second data for the period of (i) can be transmitted.
- the communication device sets a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than the data transmission period in one cycle according to the transmission path,
- a communication device for multiplexing and communicating first and second data wherein the first data for one cycle can be transmitted in the data transmission period and the quasi-data transmission period for one cycle; and Bit allocation is performed so that the first data is uniform in each of the data transmission period and the quasi-data transmission period for one cycle, and the data transmission period and the quasi-data transmission period for a predetermined period Bit allocation is performed so that the second data for a predetermined period can be transmitted to a portion where the first data is not allocated in Things.
- the communication device is a communication device that sets a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than the data transmission period in one cycle according to a transmission path. , So that data for one cycle can be transmitted in the data transmission period for one cycle, and in the data transmission period for one cycle, The transmitted data is received after allocating bits so that the data becomes uniform, and based on the data allocated to the data transmission period for one cycle, all data for one cycle is received. It is something to play.
- the communication apparatus is a communication apparatus for setting a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than the data transmission period in one cycle according to a transmission path.
- one cycle of the data transmission period and the quasi-data transmission period can be transmitted during one cycle of the data transmission period and the quasi-data transmission period.
- the received data is transmitted after performing bit allocation so that the evening becomes uniform, and based on the data allocated to the data transmission period and the quasi-data transmission period for one cycle of the received data. Re, the entire data for one cycle is reproduced.
- the communication device sets a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than the data transmission period in one cycle according to the transmission path,
- a communication device that multiplexes and communicates the first and second data, such that the first data for one cycle can be transmitted in the data transmission period for one cycle; and Bits are allocated so that the first data is uniform in a transmission period, and a portion of the data transmission period where the first data is not allocated in the data transmission period is replaced by a predetermined period of the first data. Bit is allocated so that the data of step 2 can be transmitted, the transmitted data is received, and one of the received data is allocated to the data transmission period for one cycle. Based on the first data, all the first data for one cycle is reproduced, and based on the second data allocated to the data transmission period for a predetermined cycle among the received data, The second whole data for a predetermined period is reproduced.
- the communication device sets a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than the data transmission period in one cycle according to the transmission path, Communication for multiplexing the first and second data
- the transmission device so that the first data for one cycle can be transmitted during the data transmission period and the quasi-data transmission period for one cycle, and the data transmission period and the quasi-data transmission period for one cycle Bit allocation is performed so that the first data is uniform in each period, and a portion where the first data is not allocated in the data transmission period and the quasi-data transmission period for a predetermined period is Bit allocation is performed so that the second data for a predetermined period can be transmitted, the transmitted data is received, and the received data is transmitted in the data transmission period and the quasi-data transmission period for one period.
- a data transmission period that is a period suitable for overnight transmission within one cycle and a quasi-data transmission period that is a period other than the data transmission period are set according to a transmission path.
- bit allocation is performed so that data for one cycle can be transmitted in the data transmission period for one cycle, and data is uniform in the data transmission period for one cycle. And send it.
- the communication method according to the present invention is a communication method for setting a data transmission period, which is a period suitable for data transmission within one cycle, and a quasi-data transmission period, which is a period other than the data transmission period, according to a transmission path.
- a data transmission period which is a period suitable for data transmission within one cycle
- a quasi-data transmission period which is a period other than the data transmission period, according to a transmission path.
- one cycle of the data transmission period and the quasi-data transmission period can be transmitted, and one cycle of the data transmission period and the quasi-data transmission period.
- the bits are allocated and transmitted so that the night becomes uniform.
- the communication method sets a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than the data transmission period in one cycle according to a transmission path,
- the first data for one cycle is added to the data transmission period for one cycle.
- Bit is allocated so that the first data is uniform in the data transmission period for one cycle, and the first data in the data transmission period for a predetermined cycle is Bit allocation is performed to a portion that has not been allocated so that the second data for a predetermined period can be transmitted and transmitted.
- the communication method sets a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than the data transmission period in one cycle according to the transmission path.
- the communication method according to the present invention is a communication method for setting a data transmission period, which is a period suitable for data transmission within one cycle, and a quasi-data transmission period, which is a period other than the data transmission period, according to a transmission path.
- bits are allocated so that data for one cycle can be transmitted in the data transmission period for one cycle, and data is transmitted so as to be uniform in the data transmission period for one cycle.
- Data is received and all data for one cycle is reproduced based on the data allocated to the data transmission period for one cycle among the received data.
- the communication method according to the present invention is a communication method for setting a data transmission period, which is a period suitable for data transmission within one cycle, and a quasi-data transmission period, which is a period other than the data transmission period, according to a transmission path.
- a data transmission period which is a period suitable for data transmission within one cycle
- a quasi-data transmission period which is a period other than the data transmission period, according to a transmission path.
- one cycle of the data transmission period and the quasi-data transmission period can be transmitted, and one cycle of the data transmission period and the quasi-data transmission period can be transmitted.
- the transmitted data is received by allocating bits so that the evening becomes uniform, and based on the data allocated to the data transmission period and the quasi-data transmission period for one cycle of the received data, In this way, the entire data for one cycle is reproduced.
- a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than the data transmission period are set according to a transmission path.
- Bit is allocated so that the second data can be transmitted, the transmitted data is received, and the received data is allocated to the data transmission period of one cycle before the data is transmitted.
- the first data for one cycle is reproduced based on the first data, and the second data assigned to the data transmission period for a predetermined cycle among the received data is reproduced. Based on the evening, the second whole day for a predetermined period should be played.
- the communication method sets a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than the data transmission period in one cycle according to the transmission path.
- a communication method for multiplexing and communicating first and second data wherein the first data for one cycle can be transmitted during the data transmission period and the quasi-data transmission period for one cycle; and
- bits are allocated so that the first data is uniform, and the data transmission period and the quasi- Bit allocation is performed so that a predetermined period of the second data can be transmitted to a portion where the first data is not allocated in the data transmission period, and the data is transmitted.
- Received data and the first data allocated to the data transmission period and the quasi-data transmission period for one cycle of the received data.
- One cycle of all the first data is reproduced based on one night, and based on the received data, the second data allocated to the data transmission period and the quasi-data transmission period for a predetermined period is reproduced. In other words, the second whole data for a predetermined period is reproduced.
- FIG. 1 is an explanatory diagram showing bit allocation of a communication device according to the present invention
- FIG. 2 is an explanatory diagram showing transmission delay time in a single bit map of the present invention
- FIG. FIG. 4 is an explanatory diagram showing a reception delay time in a single bit map according to the present invention.
- FIG. 4 is an explanatory diagram showing bit allocation of a communication device according to the present invention.
- FIG. 5 is a diagram illustrating a dual bit map according to the present invention.
- FIG. 6 is an explanatory diagram showing a transmission delay time in the dual bitmap of the present invention.
- FIG. 7 is an explanatory diagram showing a transmission delay time.
- FIG. 8 is an explanatory diagram showing the bit allocation of the communication device according to the present invention.
- FIG. 9 is an explanatory diagram showing the transmission delay time in the single bit map of the present invention.
- Bit of the communication device according to the invention FIG. 11 is an explanatory diagram showing assignment, FIG. 11 is an explanatory diagram showing a transmission delay time in a dual bit map of the present invention, and FIG. 12 is a diagram showing transmission / reception during a conventional communication device initialization procedure.
- FIG. 13 is an explanatory view showing a table passed between the transmission and reception during the initialization procedure of the communication device according to the present invention.
- FIG. Fig. 15 is a functional configuration diagram showing a transmission function of the AD SL station-side device according to the present invention; Fig. 15 is a functional configuration diagram showing a reception function of the AD SL terminal-side device according to the present invention; FIG.
- FIG. 6 is an explanatory diagram showing the bit allocation of the communication device according to the present invention.
- FIG. 17 is an explanatory diagram showing the bit allocation of the communication device according to the present invention.
- Fig. 4 shows a slot configuration of transmission / reception data between ADSL station-side devices according to the invention.
- FIG. 19 is an explanatory diagram showing a state of interference noise between transmission lines
- FIG. 20 is an explanatory diagram showing a state of interference noise between transmission lines
- FIG. Figure 1 shows the transmission function of the AD SL station equipment.
- FIG. 22 is a functional block diagram showing the reception function of the ADSL terminal side device
- FIG. 23 is an explanatory diagram showing the correspondence between the FEXT period and the NEXT period and the bit map.
- FIG. 24 is an explanatory diagram showing a conventional bitmap allocation
- FIG. 25 is an explanatory diagram showing a hyperframe structure.
- bits are allocated so that transmission data for one cycle can be transmitted within a data transmission period for one cycle. Bit allocation is performed at the rate converters 47 and 48 in FIG. 21 as in the case of the conventional communication device.
- Figure 1 shows an overview of bit allocation.
- bit assignment is performed so that all the uniform data for one cycle can be transmitted in a data transmission period that is a period suitable for data transmission within one period (for example, the above-mentioned FEXT section).
- Dummy bits are inserted in the portion of the data transmission period to which transmission data is not allocated, and the data is transmitted.
- bit allocation is performed so that data for one cycle (2.5 ms), that is, data for 10 DMT symbols is included in three symbols of bitmap A (symbols that fall within the data transmission period). If a bit to which data is not allocated remains in the third symbol of top A, a dummy bit is inserted in that part. Furthermore, when bitmap A continues for four symbols (for example, the 0th cycle and the 1st cycle in Fig. 25), all the 4th symbols of bitmap A are set as dummy bits. That is, the number of bits in bitmap A must satisfy the following conditions.
- Transmission rate kb ps (2.5 ms per cycle)
- the specifications in such a bit allocation are as follows (in the present embodiment, the transmittable data rate of the ADSL transmission line determined based on the S ratio measured during the training period as described above is A calculation example of bit allocation for 64 kbps is shown).
- bit map A is set to 54 bits.
- the transmitted data is rate-converted and returned to a uniform rate.
- the data that should have been received at a uniform rate may not arrive due to the change in bit allocation when transmitting at the transmission side (see Fig. 3).
- the maximum delay time on the receiving side is 7 when the symbol number is 152 in the example of FIG.
- the data is offset by a buffer or the like. 0.444203 ms, which is the sum of this offset value (0.19655 ms) and one symbol time (0.263737 ms), which is the processing delay of the discrete Fourier transform (DFT) in the receiver, is the reception delay.
- DFT discrete Fourier transform
- bit allocation is performed by the rate converters 47 and 48 in FIG. 21 as in the conventional communication device.
- Fig. 4 shows an overview of bit allocation.
- Bits are allocated to a data transmission period that is a FEXT period described above and a quasi-data transmission period that is a period other than the data transmission period (for example, a NEXT period described above).
- dummy bits are inserted and transmitted in the portion of the data transmission period and the quasi-data transmission period to which no transmission data is allocated.
- data for one period (2.5 ms), that is, data for 10 DMT symbols (before rate conversion) is equivalent to 3 symbols of bitmap A (symbol that enters the data transmission period) + bitmap B ( Bit allocation (excluding IS SClnverse Synch Symbol) and SSCSynch Symbol) is performed so that 10 symbols can be entered in 7 symbols (after rate conversion) for 7 symbols in the quasi-data transmission period), and data is not distributed in bitmap B.
- Insert dummy bits in the part If bitmap A continues for four symbols, transmission data is allocated to the fourth symbol of bitmap A using the same bit allocation as bitmap A described above, and data is transmitted in bitmap A and bitmap B. Insert dummy bits in the unallocated part. At this time, the difference between the number of bits allocated to bitmap A and the number of bits allocated to bitmap B is made as small as possible to reduce the amount of delay.
- bit numbers of bitmap A and bitmap B must satisfy the following conditions.
- the difference between the number of bits allocated to bitmap A and the number of bits allocated to bitmap B should be as small as possible (when bitmap B is the minimum value, the delay time is the worst value). Become) .
- the specifications in such a bit allocation are as follows (in the present embodiment, the transmittable data rate of the ADSL transmission line determined based on the SZN ratio measured during the training period as described above is A calculation example of bit allocation for 64 kbps is shown).
- bit map A is set to 49 bits.
- the delay time is as follows (see Fig. 5).
- the transmitted data is rate-converted and returned to a uniform rate.
- data that should have been received at a uniform rate may not be delivered due to the change in bit allocation when transmitting on the transmitting side (see Fig. 6).
- the delay time on the receiving side becomes maximum when the symbol number is 152 in the example of FIG.
- the data is offset by a buffer or the like.
- DFT discrete Fourier transform unit
- the rate One cycle of data before the bart is allocated to the three symbols of bitmap A. If bitmap A continues for four symbols, the data is packed into the first three symbols, and dummy bits are inserted into the symbols after it, and transmitted. I have. In other words, the data is assigned to the first three symbols regardless of whether bitmap A has 3 symbols or 4 symbols in one cycle. The time required is the same. For this reason, as shown in FIG. 7, the 10th symbol data (# 9, # 29) before the rate conversion is converted to the third symbol (# 2, # 23) after the rate conversion.
- the transmission delay time becomes the worst value.
- the difference between the end of the 10th symbol before rate conversion and the end of the 3rd symbol after rate conversion is largest, for example, as shown in Fig. 25 after the FEXT period has started. This is the case where the symbol in bitmap A starts earliest (for example, symbol number 81 in FIG. 25). This state is a case where four symbols can enter and exit during the FEXT period (that is, bitmap A at this time becomes bitmap A4). Therefore, the worst value of the transmission delay time is when the bitmap A has four symbols, and if the delay time when the bitmap A has four symbols can be improved, the worst value is also improved. Transmission delay time can be reduced.
- the communication device provides a data transmission method in a data transmission period (for example, corresponding to the above-mentioned FEXT section) which is a period suitable for data transmission within one cycle.
- a data transmission period for example, corresponding to the above-mentioned FEXT section
- Bit allocation is performed by the rate converters 47 and 48 in FIG. 21 similarly to the conventional communication device.
- Fig. 8 shows the outline of bit allocation.
- bit assignment is performed so that all the uniform data for one cycle can be transmitted in a data transmission period that is a period suitable for data transmission within one period (for example, corresponding to the above-mentioned FEXT section).
- Dummy bits are inserted in the portion of the data transmission period to which transmission data is not allocated, and the data is transmitted.
- bit allocation is made so that one cycle (2.5 ms), that is, 10 DMT symbols are included in three symbols of bitmap A (symbols that end the data transmission period). If bits to which data is not allocated remain in the third symbol of bitmap A, dummy bits are inserted in those portions. Also, when bitmap A continues for four symbols, data for 10 DMT symbols is evenly distributed to four symbols of bitmap A, and a portion where data of each symbol of bitmap A is not allocated , A dummy bit is inserted.
- bitmap A when bitmap A has three symbols in one cycle is called bitmap A3.
- Bitmap A in the case where there are four symbols in bitmap A in one cycle is called bitmap A4.
- bitmap A3 and bitmap A4 must satisfy the following conditions.
- the specifications in such a bit allocation are as follows (in the present embodiment, as described above, the transmittable data rate of the ADSL transmission path is determined based on the SZN ratio measured during the training period. Shows an example of calculating the bit allocation when is 64 kbps).
- bit map A is set to 54 bits. In other words, the number of bits of data distributed to bitmap A3 is 54.
- the delay time is as follows (see Fig. 9): o
- the transmitted data is rate-converted and returned to a uniform rate.
- data that should have been received at a uniform rate may not be delivered due to a change in bit allocation when transmitting on the transmitting side.
- the delay time on the receiving side is maximum when the symbol number is 152 in the example of FIG.
- the data is offset by a buffer or the like.
- This offset value (0.1 9565ms) is the processing delay of the discrete Fourier transform unit (DFT) in the receiver.
- 0.44203 ms which is the sum of one symbol time (0.26373 ms), is the reception delay.
- the maximum delay time in the transmitter / receiver device is 2.43478 ms, which is the sum of the transmission delay time (1.999275 ms) and the reception delay time (0.44423 ms). This is because the transmission delay time (2.05072ms), the reception delay time (0.44423ms :), and the maximum delay time (2.449275ms) in the transceiver device are reduced.
- Bit allocation is performed by the rate converters 47 and 48 in Fig. 21 as in the case of the conventional communication equipment.
- FIG. 10 shows an outline of bit allocation.
- the data transmission period which is a period suitable for data transmission within one cycle of the uniform data for one cycle (for example, corresponds to the FEXT section described above)
- this data transmission period Bit allocation is performed during the quasi-data transmission period that is a period other than the period (for example, equivalent to the NEXT section described above).
- a dummy bit is inserted into a portion where the transmission data is not allocated in the data transmission period and the quasi-night transmission period, and transmitted.
- data for one cycle (2.5 ms), that is, data for 10 DMT symbols (before rate conversion) is equivalent to 3 symbols of bitmap A (symbol that enters the data transmission period) + bitmap B (quasi- The bit allocation should be such that it would fall within the 7 symbols of the data transmission period), and dummy bits should be inserted into bitmap A and bitmap B where no data was allocated. If bitmap A continues for 4 symbols, the data for 10 DMT symbols (before rate conversion) is distributed to 6 symbols for bitmap B, and then uniformly distributed to 4 symbols for bitmap A. In addition, dummy bits are inserted into bitmap A and bitmap B where data is not distributed.
- bitmap A when there are three symbols of the bitmap A in one cycle is referred to as a bitmap A3.
- Bitmap A in the case where there are four symbols of bitmap A in one cycle is called bitmap A4.
- bitmap A and bitmap B must satisfy the following conditions.
- the delay time is as follows (see Fig. 11
- Transmission delay time (worst value is for symbol number 205)
- the transmitted data is rate-converted and returned to a uniform rate, as in the case shown in Fig. 6.
- the bit allocation is Data that should be received at a uniform rate may not arrive due to the change (see Fig. 12).
- the delay time on the receiving side becomes maximum when the symbol number is 152 in the example of FIG.
- the data is offset by a buffer or the like.
- DFT discrete Fourier transform unit
- the transmission rate is 64 kbps, 2.23 165 ms
- the sum of the transmission delay time (1.82088 ms) and the reception delay time (0.41 077 ms) is the maximum delay time in the transmitter / receiver device. Becomes This is because the transmission delay time (1.8 4759ms), the reception delay time (0.41 077ms), and the maximum delay time in the transceiver device (2.25836ms), which were obtained earlier, are suppressed. You can see that it is done.
- the data transmission period (e.g., equivalent to the above-mentioned FEXT section) which is a period suitable for data transmission within one cycle and the quasi-data which is a period other than the data transmission period within one cycle Transmission period (e.g., equivalent to the NEXT section described above)
- the quasi-data which is a period other than the data transmission period within one cycle Transmission period (e.g., equivalent to the NEXT section described above)
- transmission delay time can be reduced.
- the delay time can be similarly suppressed at different data rates.
- the functions shown using the functional configuration diagram in the above description may be realized by hardware or SZW.
- the data may be distributed so that the data is uniform, and dummy bits may be inserted temporally in front of the symbol.
- the insertion position is not limited to those shown in FIG. 8 and FIG.
- bitmap A is 44 bits, but bitmap A described above (hereinafter referred to as low transmission delay mode) uses bitmap A. Requires 54 bits.
- ADSL transmission line 13 (Fig. 20) The data transmission capacity of ADSL transmission line 13 (Fig. 20) is required.
- the actual valid transmission data is 64 kbps
- 80 kbps-64 kbps 16 kbps is the transmission loss in the ADSL transmission line 13.
- bitmap A in the mode other than the low transmission delay mode (hereinafter referred to as normal mode) is 44 bits
- the transmission amount is smaller than the low transmission delay mode.
- data for which the delay time is to be suppressed and data for which the delay time is not so required are mixed, and when these are multiplexed and transmitted, the dummy generated in the low transmission delay mode described above is used.
- the normal mode data is also allocated to the bit portion so that transmission is efficiently performed so that a transmission port does not occur.
- the path from the Multibrex Z sync control 41 to the ton ordering 49 One is an interleaved data buffer path including interleave 46, and the other is a fast data buffer path not including interleave 46.
- Interleaved data with interleaving—Evening buffer route has more delay.
- the ADSL terminal-side device on the receiving side (Fig. 22) also has two routes. With such a configuration, it is possible to selectively use the interleaved route and the non-interleaved route.
- Fig. 12 shows an example of the table transmitted during this initialization procedure.
- m12 and ml3 are indicated as Reserved for future use, but in the present invention, as shown in FIG. 13, in the fast data buffer route and the interleaved data buffer route, the low transmission delay mode is used. Use this part as a flag to indicate which of the / normal mode to select.
- the meaning of ml2 and ml3 at this time is shown below.
- m13 0, the interleaved data buffer path is processed in normal mode.
- ml3 1, the interleaved data buffer path is in low transmission delay mode.
- Internet data that transmits voice-based data (first data) that wants to minimize the effects of transmission delays in a fast data buffer path and in a low transmission delay mode, and that emphasizes the data transmission rate over delay.
- the operation when receiving a request from the upper layer to transmit the overnight (second data) through the interleaved data buffer path and in the normal mode will be described with reference to FIGS. 14 and 15. I do. Fig.
- FIG. 14 is a functional block diagram showing the configuration of the transmission system of the AD SL station-side device.
- Fig. 15 is a functional diagram showing the configuration of the reception system of the AD SL terminal-side device. It is a block diagram.
- reference numeral 61 denotes low transmission delay mode control means for controlling the selection of the fast data buffer path, the interleaved data buffer path, and the mode selection of the low transmission delay mode Z normal mode.
- reference numeral 161 denotes a low transmission delay mode control means for controlling the selection of the fast data buffer / interleaved data buffer path and the selection of the low transmission delay mode. Is a table that is passed between sending and receiving.
- the low transmission delay mode control means 61 controls the audio data to be transmitted through the fast data buffer path and the Internet data to be transmitted through the interleaved data buffer path. I do. Then, voice de-cyclical redundancy in the evening 42, scramble. The data is transmitted to the rate converter 4 7 via the color collection 4 4, and the Internet data is transmitted via the cyclic redundancy check 4 3, the scrambled form factor collection 4 5, and the interleave 4 6 Transmit to rate converter 48.
- the low transmission delay mode control means 61 controls the rate converters 47, 48 so that the audio data is processed in the low transmission delay mode and the in-net data is processed in the normal mode. 48 processes and transmits each data according to this control.
- the bit allocation between the audio data (first data) and the Internet data (second data) is determined, and then each data is multiplexed by ton ordering 49, analog processing and DZA converter 5
- the signal is transmitted to the ADSL terminal side device 16 via the ADSL transmission line 13 via the 3 or the like.
- the low transmission delay mode control means 16 1 has a table 16 2 (which reflects the contents transmitted in the initialization procedure). Referring to Fig. 15), control is performed so that voice data is transmitted via the fast data buffer path and Internet data is transmitted via the interleaved data buffer path. Then, the audio data is transmitted to the rate converter 148 via the discrete Fourier transform unit 144 and the like, and the Internet data is transmitted to the rate converter 149.
- the rate converter 14 4 processes the voice data in the low transmission delay mode and the Internet data in the normal mode. 8, 149 are controlled, and the rate converters 148, 149 process and transmit the respective data according to this control.
- the descrambling of the audio data was performed via the forward error collection 151, the cyclic redundancy check 15 3 and the multiplex Z-sink control 15 5 Reeve 150, Descramble 'Ford Dora One Collection 1 52, Cyc Transmit via Rick Redundancy Check 154 and Multiplex Z Sync Control 155.
- bit allocation is performed by appropriately selecting the low transmission delay mode and the normal mode for the voice data and the Internet data, respectively. If data is transmitted in such a way that normal mode data is also distributed to the dummy bits generated in the low transmission delay mode, voice should be transmitted using a communication method with a small transmission delay, and Internet data should be transmitted using a normal communication method. Therefore, transmission can be performed without causing transmission loss, and the disadvantage of transmission loss occurring in the low transmission delay mode can be eliminated.
- 64 kbps voice data is transmitted with low transmission delay.
- voice data is allotted for one cycle to the data transmission period for one cycle
- Internet data is allocated in such a way that a predetermined period (corresponding to one hyperframe) is included in the portion where voice data including dummy bits are not allocated in the data transmission period of one hyperframe.
- An example of transmission will be described (see FIG. 16). The operation is the same as described above.
- the maximum number of bits that can be taken in the predetermined FEXT section is 480 bits, and the maximum number of bits that can be taken in the NEXT section is 0 bit.
- Transmits 64 kbps data for example, one ISDN phone
- interleaves 512 kbps for example, one Internet access
- Bit allocation is performed so that voice data using the fast data buffer path for 10 symbols can be transmitted using symbols (bitmap A) in the FEXT section.
- bitmap A when there are three bitmaps A in one cycle is called a bitmap A3.
- bit map A4 a bit map having four bit maps A in one cycle is referred to as a bit map A 4.
- bitmap A3 the number of bits of audio data to be transmitted in bitmap A3 is 54 bits.
- bitmap A4 the number of bits of audio data to be transmitted in bitmap A4 is 40 bits. Then, Internet data using the interleaved data buffer path is allocated to an unused portion of the bitmap A.
- the number of bits required to transmit Internet data using the interleaved data buffer path is as follows.
- Internet data using the interleaved data buffer path can be allocated to the unused portion of bit map A and transmitted.
- the data for which the delay time is desired to be reduced and the data for which the An example of efficient transmission without generating transmission ports by combining the above-mentioned low transmission delay mode and normal mode using dual bitmaps in the case where night and night are mixed will be described. See figure). The operation is the same as above.
- the maximum number of bits that can be taken in the FEXT section determined based on the ratio measured during the training period is 384 bits
- the maximum number of bits that can be taken in the NEXT section is 8 bits
- audio data 64 kbps for example, , One ISDN telephone
- 512 kbps of Internet data for example, one Internet access network
- Bit allocation is performed so that audio data using the fast data buffer path for 10 symbols can be transmitted using symbols in the FEXT section (bitmap A) and symbols in the NEXT section (bitmap B).
- bitmap A when there are three bitmaps A in one cycle is called a bitmap A3.
- bitmap A4 A bitmap in the case where there are four bitmaps A in one cycle is referred to as a bitmap A4.
- the number of bits of audio data to be transmitted in bitmap A3 is 35 bits.
- voice data using one cycle of the fast data buffer path can be transmitted in one cycle of the FEXT section and the NEXT section, so that delay can be suppressed.
- the difference between the number of bits to be allocated to the bitmap A and the number of bits to be allocated to the bitmap B is allocated to be small, delay can be suppressed.
- One (the number of bits of audio data that can be transmitted in six symbols in the NEXT section)
- the symbol number in the FEXT section that is, the number of bits of audio data to be transmitted in bitmap A4 is 28 bits. This makes it possible to transmit the audio data using the fast data buffer path for one cycle in the FEXT section and the NEXT section for one cycle, thereby reducing delay. In addition, since the difference between the number of bits allocated to bitmap A and the number of bits allocated to bitmap B is small, delay can be suppressed.
- bit maps B are allocated to audio data using the fast data buffer path
- the Internet data using the interleaved data buffer path is allocated to unused parts of the bit map A.
- the number of bits required to transmit Internet data using the interleaved data buffer path is as follows.
- Internet data using the interleaved data buffer path can be allocated to an unused portion of the bitmap A and transmitted.
- the low transmission delay mode and the normal mode are appropriately selected for the voice data and the Internet data, respectively, and bit transmission is performed. If data is distributed and multiplexed based on the bit distribution and transmitted, voice can be transmitted using the communication method with little transmission delay, Internet data can be transmitted using the normal communication method, and the transmission port Since transmission can be performed without causing transmission, the disadvantage of transmission loss that occurs in the low transmission delay mode can be eliminated.
- STM Serial Transfer Mode
- the low transmission delay mode control means 61 (Fig. 14) and 161 (Fig. 15) are functions to control the transmission and reception of data in this way, and store voice data and Internet data in them. It has a function to detect timing synchronization and its position so that the slot that has been allocated can be known in advance, and based on the result, selects the data path and controls whether the path is in low transmission delay mode or normal mode. It controls the data transmission according to the table created by the initialization procedure or the instruction from the upper layer. Alternatively, normal mode data may be allocated to the dummy bit generated in the low transmission delay mode, so that another portion of the data can be transmitted using the portion that has become available.
- bit allocation is the same for both bitmap A3 and bitmap A4 in the normal mode.
- the maximum number of bits used in bitmap A is limited to bitmap A3 and bitmap A.
- the transmission may be performed by changing the bit allocation so that the value of 4 becomes equal. As a result, during the training period Based on the SZN ratio, it is possible to handle the case where the maximum number of bits that can be taken in the predetermined FEXT section is small.
- the data may be distributed so that the data is uniform, and dummy bits may be inserted temporally in front of the symbol.
- the positions to be inserted are not limited to those shown in FIGS. 16 and 17.
- ml2 and ml3 in the table of the initialization procedure are used as a flag for selecting one of the low transmission delay mode Z and the normal mode.
- the effect can be obtained.
- the same effect can be obtained even if the data itself can be selected by other methods such as adding a flag.
- the description is given when a request to select which of the low transmission delay mode Z and the normal mode is selected is received from the upper layer.
- the same effect can be obtained by automatically selecting according to the type of data.
- a communication device that sets a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than this data transmission period in one cycle according to the transmission path, One cycle of data during the data transmission period for one cycle And the data is averaged during the data transmission period for one cycle.
- the transmission delay can be suppressed by allocating bits so that the transmission becomes negative.
- a communication device that sets a data transmission period, which is a period suitable for data transmission within one period, and a quasi-data transmission period, which is a period other than this data transmission period, according to a transmission path, includes one period.
- One period of data can be transmitted during the data transmission period and the quasi-data transmission period, and data is uniform in each of the one period of the data transmission period and the previous quasi-data transmission period. Transmission delay can be suppressed by allocating bits to the data and transmitting.
- a data transmission period which is a period suitable for data transmission within one cycle
- a quasi-data transmission period which is a period other than the data transmission period
- the first and second data transmission periods are set.
- the first data for one cycle can be transmitted in the data transmission period for one cycle
- the data transmission period for one cycle is Bit assignment is performed so that the first data is uniform, and a portion of the data transmission period for which the first data has not been allocated for a predetermined period is allocated for a predetermined period.
- a data transmission period which is a period suitable for data transmission within one cycle
- a quasi-data transmission period which is a period other than the data transmission period
- the first and second data transmission periods are set.
- the first data for one cycle can be transmitted in the data transmission period and the quasi-data transmission period for one cycle
- Bit allocation is performed so that the first data becomes uniform in each of the data transmission period and the quasi-data transmission period
- the data transmission period and the quasi-data transmission period in the quasi-data transmission period for a predetermined period are performed.
- Bit allocation and transmission are performed so that a predetermined period of the second data can be transmitted to a portion to which the 1 data has not been allocated. Thus, transmission loss and transmission delay can be suppressed.
- a communication device that sets a data transmission period, which is a period suitable for data transmission within one period, and a quasi-data transmission period, which is a period other than this data transmission period, according to a transmission path, includes one period. Bit allocation is performed so that one cycle of data can be transmitted during the data transmission period, and data is uniformed during one cycle of the data transmission period, and the transmitted data is received. The transmission delay can be suppressed by reproducing the entire data for one cycle based on the data allocated to the data transmission period for one cycle among the data thus obtained.
- a communication device that sets a data transmission period, which is a period suitable for data transmission within one period, and a quasi-data transmission period, which is a period other than this data transmission period, according to a transmission path, includes one period. Bits are set so that data for one cycle can be transmitted in the data transmission period and the quasi-data transmission period, and that data is united in each of the data transmission period and the quasi-data transmission period for one cycle. After receiving the transmitted data after allocating, based on the data allocated to the data transmission period and the quasi-data transmission period for one cycle of the received data, all the data for one cycle is obtained. By reproducing, transmission delay can be suppressed.
- a data transmission period that is a period suitable for overnight transmission within one cycle and a quasi-data transmission period that is a period other than this data transmission period are set according to the transmission path, and the first and second data transmission periods are set.
- the first data for one cycle can be transmitted in the data transmission period for one cycle, and the first data is transmitted in the data transmission period for one cycle.
- Bit assignment is performed so that the first data is uniform, and the second data for a predetermined cycle is assigned to a portion where the first data is not allocated in the data transmission period for a predetermined cycle.
- the transmitted data is received after allocating bits so that data can be transmitted, and one cycle of the received data is based on the first data allocated to the data transmission period for one cycle. First and reproduces all data evening minute of data evening said received Based on the second data allocated to the data transmission period for a predetermined period, all the second data for a predetermined period is reproduced to suppress transmission loss and delay transmission. Can be suppressed.
- a data transmission period which is a period suitable for data transmission within one cycle
- a quasi-data transmission period which is a period other than the data transmission period
- the first and second data transmission periods are set.
- the first data for one cycle can be transmitted in the data transmission period and the quasi-data transmission period for one cycle
- the data transmission for one cycle Bit allocation is performed so that the first data becomes uniform in each of the period and the quasi-data transmission period, and the first data in the data transmission period and the quasi-data transmission period for a predetermined period is provided.
- Bit allocation is performed so that a predetermined period of the second data can be transmitted to a portion where data has not been allocated, and the transmitted data is received.
- a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than the data transmission period are set according to a transmission path
- a bit is allocated and transmitted so that one cycle of data can be transmitted during the data transmission period and data is uniform during one cycle of the data transmission period, thereby reducing transmission delay. Can be suppressed.
- a data transmission period that is a period suitable for data transmission within one period and a quasi-data transmission period that is a period other than this data transmission period are set according to a transmission path.
- one period is used.
- One data period during the data transmission period and the quasi-data transmission period, and one data transmission period and the quasi-data transmission period By allocating and transmitting bits so that data becomes uniform in each of the quasi-data transmission periods, transmission delay can be suppressed.
- a data transmission period which is a period suitable for data transmission within one cycle
- a quasi-data transmission period which is a period other than the data transmission period
- the first and second data transmission periods are set.
- the first data for one cycle can be transmitted in the data transmission period for one cycle
- the first data is transmitted in the data transmission period for one cycle.
- Bit allocation is performed so that data becomes uniform
- the second data for a predetermined period is transmitted to a portion where the first data is not allocated in the data transmission period for a predetermined period.
- a data transmission period which is a period suitable for data transmission within one cycle
- a quasi-data transmission period which is a period other than the data transmission period
- the data transmission for one cycle can be transmitted in the data transmission period and the quasi-data transmission period for one cycle, and the data transmission for one cycle.
- Bit allocation is performed so that the first data is uniform in each of the period and the quasi-data transmission period, and the first data in the data transmission period and the quasi-data transmission period for a predetermined period are allocated.
- Transmission loss is achieved by allocating bits to a portion where the 1 data is not allocated so that the second data for a predetermined period can be transmitted, and transmitting the second data. It is possible to suppress the transmission delay with obtaining.
- a communication method in which a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than this data transmission period are set in one cycle according to the transmission path, Receiving the transmitted data by allocating bits so that data for one cycle can be transmitted in the data transmission period of the above, and so that the data becomes uniform during the data transmission period of one cycle; Based on the data assigned to the data transmission period for one cycle of the received data, all data for one cycle By reproducing the night, transmission delay can be reduced.
- a data transmission period that is a period suitable for data transmission within one cycle and a quasi-data transmission period that is a period other than the data transmission period are set according to a transmission path.
- One period of data can be transmitted during the data transmission period and the quasi-night transmission period, and each period of the data transmission period and the previous quasi-data transmission period is one period.
- the transmitted data is received after allocating bits so that the data is uniform, and based on the data allocated to the data transmission period and the quasi-data transmission period for one cycle of the received data.
- the transmission delay can be suppressed by reproducing the entire data for one cycle.
- a data transmission period which is a period suitable for data transmission within one cycle
- a quasi-data transmission period which is a period other than the data transmission period
- the first and second data transmission periods are set according to the transmission path
- the first and second data transmission periods are set.
- the first data for one cycle can be transmitted in the data transmission period for one cycle
- the first data is transmitted in the data transmission period for one cycle.
- Bit allocation is performed so that data becomes uniform
- the second data for a predetermined period is transmitted to a portion where the first data is not allocated in the data transmission period for a predetermined period.
- the received data is transmitted after performing bit allocation so that one cycle can be performed based on the first data allocated to the data transmission period for one cycle of the received data.
- the second data allocated to the data transmission period for a predetermined period among the received data By reproducing all the data, transmission loss and transmission delay can be suppressed.
- a data transmission period which is a period suitable for data transmission within one cycle
- a quasi-data transmission period which is a period other than the data transmission period
- the first and second data transmission periods are set.
- the first data for one cycle is included in the data transmission period for one cycle and the quasi-data transmission period.
- Bit is allocated so that the first data is uniform in each of the data transmission period and the quasi-data transmission period for one cycle, and Bits are allocated to a portion of the data transmission period and the quasi-data transmission period to which the first data has not been allocated so that a predetermined period of the second data can be transmitted.
- the communication device and the communication method according to the present invention are suitable for a communication method in which data communication is performed between a plurality of data communication devices via a telephone line, for example, by a discrete multitone modulation / demodulation method. I have.
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Description
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EP99919653A EP1050988A4 (en) | 1998-10-29 | 1999-05-19 | COMMUNICATION DEVICE AND METHOD |
US09/559,175 US7457309B1 (en) | 1998-10-29 | 2000-04-27 | Bit assignment in a communication system and communication method |
US11/785,012 US7801170B2 (en) | 1998-10-29 | 2007-04-13 | Bit assignment in a communication system and communication method |
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JP30858698A JP3191783B2 (ja) | 1998-10-29 | 1998-10-29 | 通信装置および通信方法 |
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GB2424805B (en) * | 2005-03-30 | 2007-02-28 | Toshiba Res Europ Ltd | Efficient channel tracking in packet based OFDM systems |
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US9716508B1 (en) * | 2016-03-28 | 2017-07-25 | Analog Devices Global | Dummy signal generation for reducing data dependent noise in digital-to-analog converters |
US10855435B2 (en) * | 2017-01-18 | 2020-12-01 | Sony Interactive Entertainment Inc. | Communication apparatus, generated data size controlling method, and program |
EP3593457B1 (en) * | 2017-03-10 | 2024-05-15 | Intel Corporation | Partial echo cancellation duplexing |
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- 1999-05-19 KR KR10-2000-7007221A patent/KR100384089B1/ko not_active IP Right Cessation
- 1999-05-19 CA CA002309208A patent/CA2309208A1/en not_active Abandoned
- 1999-05-19 EP EP99919653A patent/EP1050988A4/en not_active Withdrawn
- 1999-05-19 CN CN99801942A patent/CN1287728A/zh active Pending
- 1999-05-19 AU AU37326/99A patent/AU744613B2/en not_active Ceased
- 1999-06-05 TW TW088109353A patent/TW429703B/zh not_active IP Right Cessation
-
2000
- 2000-04-27 US US09/559,175 patent/US7457309B1/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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JP3191783B2 (ja) | 2001-07-23 |
EP1050988A4 (en) | 2006-08-16 |
US7801170B2 (en) | 2010-09-21 |
US20070195828A1 (en) | 2007-08-23 |
CN1287728A (zh) | 2001-03-14 |
EP1050988A1 (en) | 2000-11-08 |
US7457309B1 (en) | 2008-11-25 |
AU3732699A (en) | 2000-05-22 |
TW429703B (en) | 2001-04-11 |
CA2309208A1 (en) | 2000-05-11 |
KR20010033698A (ko) | 2001-04-25 |
KR100384089B1 (ko) | 2003-05-14 |
JP2000138729A (ja) | 2000-05-16 |
AU744613B2 (en) | 2002-02-28 |
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