WO2000024224A1 - Architecture pour gerer des canaux de transmission dans le commutateur d'un systeme de telecommunication, en particulier du type satellite - Google Patents

Architecture pour gerer des canaux de transmission dans le commutateur d'un systeme de telecommunication, en particulier du type satellite Download PDF

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Publication number
WO2000024224A1
WO2000024224A1 PCT/IT1998/000284 IT9800284W WO0024224A1 WO 2000024224 A1 WO2000024224 A1 WO 2000024224A1 IT 9800284 W IT9800284 W IT 9800284W WO 0024224 A1 WO0024224 A1 WO 0024224A1
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WO
WIPO (PCT)
Prior art keywords
serial transmission
transmission
channel
input
architecture
Prior art date
Application number
PCT/IT1998/000284
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English (en)
Italian (it)
Inventor
Carlo Alberto Ponzoni
Guido Albertengo
Original Assignee
Laben S.P.A.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Laben S.P.A. filed Critical Laben S.P.A.
Priority to PCT/IT1998/000284 priority Critical patent/WO2000024224A1/fr
Publication of WO2000024224A1 publication Critical patent/WO2000024224A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/204—Multiple access
    • H04B7/2046—SS-TDMA, TDMA satellite switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/64—Distributing or queueing
    • H04Q3/68—Grouping or interlacing selector groups or stages
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13003—Constructional details of switching devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1302—Relay switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1304—Coordinate switches, crossbar, 4/2 with relays, coupling field
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13046—Binary switch, β-element
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13106—Microprocessor, CPU
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13216—Code signals, frame structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13299—Bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13333—Earth satellites
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1334—Configuration within the switch
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13341—Connections within the switch

Definitions

  • the present invention relates to an architecture for the management of transmission channels in a switch of a telecommunication system, in particular of the satellite type.
  • the invention relates to an architecture for the management of transmission channels in a switch of a telecommunication system, in particular of the satellite type comprising a switching matrix connected between a plurality of input channels and a plurality of output channels.
  • the invention also relates to a structure for the transmission and the channelling of digital signals connected to at least one input channel and at least one output channel .
  • the invention relates in particular, but not exclusively, to an architecture which is able to be installed on board a satellite for telecommunications and the following description is made with reference to this field of application with the sole scope of simplifying the exposure.
  • a satellite for telecommunications can be considered as an element of a complex transmission network. In any case, given its importance, it is usual to consider it as a telecommunication system in itself.
  • the subsystem S/S BUS comprises the essential elements for the operation of the satellite, not necessarily a telecommunications satellite. It therefore comprises:
  • a subsystem of navigation and trim control capable, in particular, of assuring the orientation of the satellite foreseen by the mission
  • a power subsystem capable of supplying electrical energy necessary to the carrying out of the mission to the satellite itself, in all the foreseen working conditions, protecting and isolating the loads, and delivering voltages with sufficient tolerance
  • control and telemetry subsystem to send commands to the satellite, control their correct execution, and know the status of the satellite itself.
  • subsystem S/S Payload comprises the receiving RX and transmission TX sections from and for the sites on earth.
  • the receiving section RX is normally connected to the transmission section TX by means of a signal process chain, comprising essentially of an amplification chain, a conversion block of the input signal at a lower frequency (down-converter) , a shifting block at intermediate frequency of the transmitted signal, a possible analogic switching matrix at intermediate frequency, as well as a transmission chain, complementary to the receiving chain.
  • a signal process chain comprising essentially of an amplification chain, a conversion block of the input signal at a lower frequency (down-converter) , a shifting block at intermediate frequency of the transmitted signal, a possible analogic switching matrix at intermediate frequency, as well as a transmission chain, complementary to the receiving chain.
  • the transmission chain operates as a radio link, amplifying the signal received and re-transmitting it after having shifted it in frequency.
  • the structure described is suitable for the transmission of signals both in analogical form and numerical form.
  • the transmission chain comprises in this case, downstream of the intermediate frequency amplifier IF, a demodulator which allows a numeric signal in base band to be obtained.
  • a numeric type switching matrix Downstream of the demodulation stage a numeric type switching matrix can be installed (commonly referred to with the term "digital switching matrix") .
  • the transmission chain is complementary to that of receiving, comprising a modulator, an up-conversion chain and some amplification stages, as previously seen.
  • it is possible to operate with intermediate steps on the signal transmitted for example, carrying out a de-coding/coding by means of suitable devices. In such schemes it is possible to further foresee different coding types for the signal received and for that transmitted.
  • S/S Payload subsystem is traditionally distinct from the S/S BUS subsystem in the architecture as a whole of the satellite. This separation is indispensable also because of the fact that in general different companies, suitably specialised, produce the different components of the satellite.
  • a satellite of this type sees the earth as a series of distinct geographic areas . These areas are commonly indicated with the term "spot”.
  • spot The transmissions coming from each spot can be re-transmitted towards the same spot it came from or towards other spots by means of static or modifiable connections matrices. The latter are identifiable by the term "permutation matrices".
  • permutation matrices are re-configured so as to assign a higher number of connections to the areas with more traffic: configuration times are established in the order of a second, so as to be absolutely reasonable for an operator and to also permit complex re- configurations.
  • These matrices can be used together with a simple transmission chain or with a transmission-regeneration chain.
  • switching matrix we mean an apparatus for switching able to manage all the incoming and outgoing channels from the satellite's telecommunication equipment.
  • the management of channels for telecommunication are particularly carried out in an independent way from the geographic distribution of the connections, distinguishing only the input flows/channels (also called up-link) from the output flows/channels (also called down-link) for each single area, making in this way the best use of resources, that is to say of the connections available.
  • Terrestrial switching is a discipline characterised by a vast industrial involvement, dynamic - because it is based on the availability of electronic and similar technologies - historically identified with the development of "large projects” and in consequence the dominion of the large companies in the field.
  • Local terrestrial stations can be taken as a possible reference, in that the direct connection of the users to the satellite would render the satellite functionally levelled down to a local station (or a station for cellular telephony, except for the larger band switched) .
  • TST switches are known (or switches equivalent to STS) , comprising one or more stages of input T, one or more stages of output T and a single stage S.
  • an input stage T moves the information temporally into an intermediate position, or into a service position, Tm, algorithmically determined in such a way as to avoid collisions; a further output stage T therefore moves the information, transferred onto the output channel determined thanks to the stage S, into the desired final time position T2.
  • the two stages T create the time switchings requested, guaranteeing the complete use of the space matrix S placed between them, independent of whatever the time positions Tl and T2 may be and independent from whatever the input line INI and the output line OUT2 may be . It is also advisable to specify that the complexity of the calculation of such an intermediate position Tm increases in a superlinear way with the dimensions of the matrix.
  • the few known satellite switches revolve around a concept of switch developed within the European Space Agency (ESA) , having a capacity of the base module, equal to 260 Mb/s, up to 2Gb/s.
  • ESA European Space Agency
  • maximum extension applicable is equal to 2 Gb/s against needs of switching of 10 Gb/s required by the satellites being designed today;
  • the TST solution presents the drawback of a switching delay more than double the duration of the frame.
  • the switch thus obtained presents therefore numerous disadvantages .
  • the technical problem which is the basis of the present invention is to design a switch suitable for satellite applications, having structural and operational characteristics such as to allow for the management of a very high number of channels, at the same time limiting its weight and dissipated power, therefore overcoming the limitations of the solutions which make reference to switches for terrestrial stations according to prior art .
  • the idea of solution at the basis of this invention is to use a modular architecture based on a parallelisation of the switching matrix in order to reduce dimensions and control complexity thereof.
  • the present invention foresees the use of a serial transmission channel, able to carry both original and processed information inside the modular architecture, regenerating it in the process.
  • the reliability of modular architecture is further guaranteed by the use of a redundancy structure for this serial transmission channel, capable of facing situations of malfunction or failure of the main channel .
  • FU Frame Unit
  • Figure 1 B shows a schematic view of a structure of informative units (FU) :
  • FIG. 2 shows a schematic view of an embodiment for switching the structure of informative units of figure IB
  • Figure 3 shows a schematic view of an architecture of "byte sliced” type according to the invention
  • Figure 4 shows a schematic view of a substitution of data of the type denominated ping-pong used in the architecture of figure 3;
  • Figures 5 and 6 show respective schematic views of an example of movement of information performed by means of a pipeline according to the invention.
  • Figure 7 shows as an example the possible aspect of a physical embodiment of the invention.
  • a satellite switch comprises essentially of a matrix, denominated herein as switching matrix, connected between a plurality of lines, or channels, of input and a plurality of lines or channels of output.
  • switching matrix carries out the transferral of information present on an input channel on a suitably selected output channel, at the same carrying out a time shifting.
  • the information arrives at the input channels in the form of bit frames, subdivided on said plurality of input lines and suitably indexed according to the instant of receiving.
  • Such structure of informative units can be identical to that of input/output or be the fruit of a suitable process, deterministically reconstructable with reference to a Frame Start Signal SIT.
  • a memory matrix, or sub-machine, SM1,...,SM64 is associated to each group of bit B1,...,B64.
  • the advantages offered by a common memory architecture include a reduced delay in transit of the data inside the switch, the possibility of increasing the reliability with controlled increases of the dimension of the common memory, and the limited complexity of control of the memory itself and of the switch in its whole .
  • the common memory also called switching matrix given its central function in the operations of switching of the channels of input and output of the transmission system, requires furthermore the availability of memory banks, capable of being written and read at a speed of 10 Gb/s, and if necessary higher.
  • the satellite switch according to the present invention parallelises the functions of switching.
  • the memory slot structure already present in known equipment is made use of, which is equal to 64 Bytes against 1 Byte of the terrestrial applications.
  • each sub-machine SMI, ... , SM64 contains a time segment of all the lines of input connected to the switch.
  • sixty- four parallel sub-machines SMI, ... ,SM64 are used, which work at a peak speed of 10 Gb/s, but at an average speed equal to 1/64 of 10 Gb/s and are therefore possible even with the components already known for present applications.
  • FU Frame Unit
  • Figure IB schematically shows also this decomposition in parallel sub-machines, indicated with the acronym SM , " Shared Memory” .
  • the frame structure 1 of figure IB is implemented by means of a structure of elementary modules 2, in particular processing blocks, connected in parallel to each other between a bus 3 of input and a bus 4 of output, as illustrated in figure 2.
  • the structure of each single module will be illustrated in detail at a later point.
  • the embodiment of the structure of frame 1 schematically illustrated in figure 2 presents also the possibility of overcoming the failure of an elementary module 2.
  • a number of elementary modules 2 above the number of sub-machines SMI, .... ,SM64, necessary for the frame decomposition according to the invention in this particular example equal to sixty- four, it is possible to face more failures, until the requisites for reliability required by each specific application are satisfied.
  • frame structure 1 of the type illustrated in figure IB is called "byte sliced” and is usable, without having to use further stages of switching, until the following relationship is observed:
  • C is the total capacity to be switched (normally expressed in bits/s) ;
  • n is the number of bits composing an Informative Unit
  • T is the access time to the memory banks of the sub- machines SM1,...,SM64 selected;
  • frame 1 as described might present certain problems if applied directly to actual equipment for telecommunication operating on board satellite .
  • the structure of frame 1 comprises a single input bus on which all the information relative to the frame to be transmitted are stored.
  • the switching matrix can in this case continue to operate, but at reduced capacity, that is without being able to guarantee the operation on all input and output lines.
  • bus is of the passive type, so as to avoid a multiplexer in output, the complexity of which would eliminate the advantages of the architecture of the byte sliced type according to the invention.
  • a passive bus moreover, is not capable of guaranteeing the stable operation of the actual switching matrix, in the conditions of speed specified (40 Mb/s in this specific example) .
  • the byte sliced architecture 5 comprises of at least one chain 6 of elementary modules 6 l r 6 2 , ... , 6 n , connected to an input demultiplexer 8 and to an output multiplexer 9, via a main pipeline transmission channel 10.
  • Such main pipeline 10 further connects each elementary module to each other 6 1# 6 2 ,...,6 n of said chain 6.
  • each elementary module extracts its own byte in input and feeds an already processed byte in output, at the same time regenerating the information transported by the pipeline itself before feeding it to the next elementary module.
  • This approach therefore allows the regeneration of the entire pipeline 10 passing from one elementary module to another and, at the same time, halving the number of connections necessary.
  • each informative unit FU is composed of four bytes.
  • a reduced frame is used as an example to facilitate the understanding of the mechanism of operation of the byte sliced architecture 5 according to the invention, avoiding the numeric complications of an example corresponding to the actual needs of space applications .
  • the first module 6 ⁇ of the chain 6 extracts the first byte of each "Fu input k+2 , F i+1, and substitutes it with the first byte destined for "FU output K" and coming from "Fi", as illustrated in figure 5.
  • the pipeline is correctly formed and temporally shifted of one frame plus two informative units FU, as illustrated in figure 6.
  • each module SM in an identical way as all the others, that is operating the substitution on the pipeline of the groups of bit extracted with those processed and pertinent to the preceding FU, according to the invention the structure of the frame at the output of the pipeline is advantageously already the one desired, without it therefore being necessary to make any further elaboration.
  • a further optimization is therefore obtained by working on the main pipeline 10, also known as traffic pipeline, in particular by subdividing the switch into "M” sections - with "M” submultiple of "n” (number of bits composing the informative units FU) .
  • Each section Sm (each one composed of operating modules in accordance with the above mentioned concept of byte sliced structure) , processes the position bits "m + M” , "m + 2M” , etc.
  • the number of input/output connections per module is therefore divided by "M" .
  • the final architecture 5 of the byte sliced type comprises in fact a first chain 6 and a second chain 7 of elementary modules, 6 17 6 2 ,-..,6 n and l ⁇ , 7 2 ,...,7 n respectively, dedicated to the parallel processing of odd and even bits respectively.
  • Such first and second chain of elementary modules are connected to a input demultiplexer 8 and to an output multiplexer 9, via a main pipeline 10, which connects each elementary module to each other, both of the first and of the second chain.
  • the input demultiplexer 8 provides for the generation of two pipelines 10 and 10', odd and even, and the output multiplexer 9 recomposes the flow of information of frame.
  • the reliability of the machine is further guaranteed by the use of a redundancy structure by means of a pipeline of redundancy 11, identical to the main pipeline 10.
  • each module independent of the chain it belongs to (odd or even, in a specific example of embodiment) , contains a time portion of all the channels .
  • the flow of traffic as a whole can travel on portions of both the pipelines, main and of redundancy, allowing for a single failure on the interface to be adjusted: in the case of a failure it is sufficient to switch the transmission of the main pipeline to the pipeline of redundancy. According to their position even more than one failure can be adjusted.
  • each group of data is carried out, in each module denominated SM, by means of a double memory bank which operates in successive frame ranges alternating the functions carried out by each single bank, in a so- called “ping-pong" way, as schematically illustrated in figure 4.
  • Each elementary module therefore comprises an input controller 14 connected to an output controller 15 via a first memory bank 16 and a second memory bank 17, operating in alternate cycles, of a duration equal to the duration of an entire frame.
  • the memory bank 16 stores the data coming from the input controller 14, whilst the memory bank 17 sends the data stored in the previous cycle to the output controller 15.
  • the two banks exchange the repetitive functions, so that the memory bank 17 stores the data coming from the input controller 14, whilst the memory bank 16 sends the data stored in the previous cycle to the output controller
  • the byte sliced architecture 5 advantageously carries out a demultiplexing (and following multiplexing) bit to bit (instead of, for example, byte to byte) , minimising in this way the number of registers necessary for carrying out such operation and therefore the power consumption, a parameter which is always critical in applications for space .
  • connection memory DM Driving Memory
  • connection memory DM contains the order of the re-reading of the data previously stored in each module SM in sequential order.
  • the suitable order of re-reading of the data allows each byte to be inserted in a suitable position on the pipeline in such a way that at the output it will be placed in the suitable output line in a suitable time position.
  • the traffic pipeline operates at a speed of 40 Mb/s whilst the sub-machines operate at 20 Mb/s with an address bus having 19 lines (for a total of 524,288 addresses) .
  • Multiplexing the addresses of memory at 40 Mb/s it is possible to also reduce to about a half the lines of the pipeline of the memory of connection, which can therefore use 10 lines instead of 19 lines.
  • the various sub-machines carry out the reading in parallel of the bytes of their competence, or use the current memory address present on the pipeline.
  • each sub-machine SM could receive and regenerate all the flow of information transported in the switching matrix, providing, in the specific example, a cascade of thirty-two sub-machines per switching matrix.
  • the sub-machines SM grouped on the same board are in fact connected via a passive bus, not adopted as far as the whole switching matrix is concerned, because of the problems it causes.
  • the reduced number of sub-machines SM (and therefore the related problems of fan-out) , and the reduced distances (and therefore easier synchronisation) , makes possible the adoption of the passive bus, for example, by means of a similar and reduced structure of the embodiment in figure 2.
  • each sub-machine is programmable by remote control, it is possible to connect to the passive bus more sub-machines than are necessary.
  • a unit of switching designed in accordance with the present invention in assembled form, would take the aspect shown as an example in figure 7.
  • the satellite switch according to the invention presents four specific technical elements:
  • connection memory DM equipped with a pipeline with "dual bus detour" type structure

Abstract

La présente invention concerne une architecture permettant de gérer des canaux de transmission dans le commutateur d'un système de télécommunication, en particulier du type satellite comprenant une grille de commutation connectée entre plusieurs canaux d'entrée et plusieurs canaux de sortie. Cette grille de commutation est pourvue de plusieurs sous-machines (SMi), chacune de ces sous-machines étant montée en parallèle entre un sous-groupe de canaux d'entrée destinés à recevoir des signaux d'entrée (Bi), et un sous-groupe de canaux de sortie, par l'intermédiaire d'au moins un canal principal de transmission série (10) du type à pipeline. Cette invention concerne également une structure de transmission et d'acheminement de signaux numériques. Cette structure, connectée à au moins un canal d'entrée et à au moins un canal de sortie, comprend au moins une chaîne (6) de modules élémentaires (61, 62, ..., 6n) pour traiter des signaux, ces modules étant connectés en cascade par l'intermédiaire d'un canal principal de transmission série (10) du type à pipeline. De plus, chacun de ces modules élémentaires(61, 62, ..., 6n) prélève de ce canal principal de transmission série (10) des informations binaires relatives à ce dernier, avant d'émettre depuis ce canal principal de transmission série (10) des informations binaires préalablement traitées, ce qui régénère les informations transportées par ledit canal principal de transmission série (10), avant même que ces informations ne soient fournies au module élémentaire suivant. Ainsi, le passage d'un module élémentaire à un autre permet de régénérer le canal principal de transmission série (10).
PCT/IT1998/000284 1998-10-16 1998-10-16 Architecture pour gerer des canaux de transmission dans le commutateur d'un systeme de telecommunication, en particulier du type satellite WO2000024224A1 (fr)

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Application Number Priority Date Filing Date Title
PCT/IT1998/000284 WO2000024224A1 (fr) 1998-10-16 1998-10-16 Architecture pour gerer des canaux de transmission dans le commutateur d'un systeme de telecommunication, en particulier du type satellite

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Application Number Priority Date Filing Date Title
PCT/IT1998/000284 WO2000024224A1 (fr) 1998-10-16 1998-10-16 Architecture pour gerer des canaux de transmission dans le commutateur d'un systeme de telecommunication, en particulier du type satellite

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003059004A1 (fr) * 2001-12-27 2003-07-17 Intel Corporation Permutation de signal

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2596606A1 (fr) * 1986-03-28 1987-10-02 Lmt Radio Professionelle Commutateur a architecture modulaire
DE3735853C1 (en) * 1987-10-23 1989-05-11 Ant Nachrichtentech Switching system
US5220320A (en) * 1988-03-11 1993-06-15 Comsat Switch matrix including both B switching elements and crossbar switch matrices
US5696470A (en) * 1995-06-07 1997-12-09 Comsat Corporation Solid-state electronic switching module

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2596606A1 (fr) * 1986-03-28 1987-10-02 Lmt Radio Professionelle Commutateur a architecture modulaire
DE3735853C1 (en) * 1987-10-23 1989-05-11 Ant Nachrichtentech Switching system
US5220320A (en) * 1988-03-11 1993-06-15 Comsat Switch matrix including both B switching elements and crossbar switch matrices
US5696470A (en) * 1995-06-07 1997-12-09 Comsat Corporation Solid-state electronic switching module

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BERNER W ET AL: "MOBS - A MODULAR ON-BOARD SWITCHING SYSTEM", IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE & EXHIBITION, vol. 3 of 3, 28 November 1988 (1988-11-28) - 1 December 1988 (1988-12-01), HOLLYWOOD, FLORIDA, pages 1769 - 1773, XP000043798 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003059004A1 (fr) * 2001-12-27 2003-07-17 Intel Corporation Permutation de signal
US7177301B2 (en) 2001-12-27 2007-02-13 Intel Corporation Signal permuting

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