WO2000019599A1 - Schaltungsanordnung zum mischen eines eingangssignals und eines oszillatorsignals miteinander - Google Patents
Schaltungsanordnung zum mischen eines eingangssignals und eines oszillatorsignals miteinander Download PDFInfo
- Publication number
- WO2000019599A1 WO2000019599A1 PCT/DE1999/003102 DE9903102W WO0019599A1 WO 2000019599 A1 WO2000019599 A1 WO 2000019599A1 DE 9903102 W DE9903102 W DE 9903102W WO 0019599 A1 WO0019599 A1 WO 0019599A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- input
- differential amplifier
- phase
- signal
- voltage
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1433—Balanced arrangements with transistors using bipolar transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1491—Arrangements to linearise a transconductance stage of a mixer arrangement
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
- H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
Definitions
- Circuit arrangement for mixing an input signal and an oscillator signal with one another
- the invention relates to a circuit arrangement for mixing an input signal and an oscillator signal with one another.
- Image rejection mixers are an advantageous solution to save complex image rejection filters for input receivers and to achieve a higher level of integration.
- Such mixers have the disadvantage that they require more than twice the performance of a conventional mixer.
- the question of power consumption is particularly important in mobile applications, since the power consumption there essentially influences the cost intensity, the structure of the respective device and its properties.
- Signal frequency suppression mixers are known, for example, from US Pat. Nos. 4,801,900 and 5,661,485. Such mixers generally include an input amplifier with low noise, two identical mixer stages, each with an associated amplifier for an oscillator signal, a phase divider for generating two orthogonal oscillator signals from the original oscillator signal and an output phase combiner.
- the input and output impedance relationships play a special role here.
- a more or less high input impedance in the amplifiers for the oscillator signal usually means a higher power consumption.
- the insertion loss due to these additional elements must be compensated for by the phase combiner at the output, which in turn entails a higher power consumption.
- Usual amplifiers with low noise are constructed as power-voltage converters with an input-side trans sistor (or pair of transistors in a differential version) in a cascode circuit, which drives a passive load such as a parallel low-pass network with resistors and capacitors.
- a voltage-current feedback with a resistor needs a precisely matched input impedance to achieve the required linearity.
- inputs with common emitters are best suited for low noise, they must be operated with a very high bias (a few mA). The power signal at the input is thus converted into a current that drives the passive load and leads to a voltage at the output as an output signal.
- large voltage signals require a corresponding DC voltage reserve.
- the mixers have a significantly higher input impedance compared to the output impedance of the amplifiers in order to reduce the insertion loss.
- an input stage with a common emitter as with the amplifier must be implemented, to which additional linearity requirements have to be imposed due to the amplifier's amplification.
- This linearity can be achieved by emitter degeneration, but this requires a very high output impedance in the mixer in order to achieve a voltage converter gain of approximately OdB. This in turn means that a higher headroom is required.
- the same requirements also apply to the phase combiner and it also requires an additional headroom.
- the object of the invention is to provide a circuit arrangement of the type mentioned, which does not have the above disadvantages.
- the circuit arrangement according to the invention for mixing an input signal and an oscillator signal with one another has in particular the following features:
- the present invention makes it possible to stack individual circuit blocks on top of one another in such a way that, on the one hand, the bias currents can be divided by the individual blocks and, on the other hand, that they can operate even at very low supply voltages down to 2.7 V.
- the mixers have a very low input impedance (due to the coupled bases) and are each supplied with half the current (at half the bias current level of the amplifier with low noise).
- only a small voltage control reserve is required by such an architecture.
- the amplifiers amplifying the oscillator signal are designed such that the output impedance is small enough, the mixer can be reduced to a simple pair of switches which switch the oscillator signal and which replaces the input stage with a common base.
- phase combiner which is constructed in a similar way, can then finally be added to the mixer and receive the same bias current as the other circuit parts. Since the bias currents are high, the input impedances of all blocks are small enough so that there is little signal loss overall. The overall gain is essentially generated by the amplifier with low noise in order to advantageously compensate for higher noise contributions from the mixers due to the signal distribution at their input. Finally, the stacking of the phase combiner and the mixer can significantly reduce the power consumption of the entire arrangement.
- the two phase shifters each have a symmetrical input and a symmetrical output, each with an inverting and non-inverting connection.
- the inverting and non-inverting inputs on the input side are Short circuits with the output-side inverting and non-inverting connections are connected directly or crosswise by means of two resistors and two capacitors.
- a suitable phase shifter current input and output can thus be implemented with little circuit complexity and in passive circuit technology. Passive implementation also has the advantage that there is essentially no additional noise, such as with active phase shifters.
- the controllable current sources preferably have a first constant current source connected in series with the respective differential amplifier, a second constant current source connected in parallel with the respective differential amplifier, and an amplifier stage connected in parallel with the first constant current sources.
- a cascode circuit is preferably provided in the amplifier stage and / or adding device, which is fed in particular from a common reference voltage source.
- the circuit arrangement according to the invention shown in the drawing contains two differential amplifiers 1 and 2, each of which has two emitter-coupled npn bipolar transistors 3, 4 and 5, 6, respectively.
- the bases of the transistors 3, 4 are connected to a symmetrical output of a phase divider 7, while the bases of the transistors 5, 6 are connected to the other symmetrical output of the phase divider 7.
- An oscillator signal 8 is applied to the phase divider 7.
- Orthogonal oscillator signals are present at the two symmetrical outputs of the phase divider 7, that is to say two signals which are phase-shifted by 90 ° with respect to one another and which affect the oscillator. zillatorsignal 8 decrease.
- the phase shift of 90 ° is achieved in that the oscillator signal is supplied on the one hand to a phase shifter with a phase shift of 45 ° and on the other hand to a phase shifter with a phase shift of 135 °. This results in a phase difference of 90 ° between the two signals at the output of the two phase shifters and thus at the outputs of the phase divider 7.
- the symmetrical outputs of the phase divider 7 are voltage outputs for controlling the transistors 3, 4 and 5, 6.
- the differential amplifiers 1 and 2 are each fed by a constant current source 9 or 10 in such a way that the constant current source 9 is connected between the coupled emitters of the transistors 3 and 4 on the one hand and a reference potential 11 on the other hand and the constant current source 10 between the coupled emitters of the transistors 5 and 6 on the one hand and the reference potential 11 on the other hand.
- the coupled emitters of transistors 3 and 4 are connected to a positive supply potential 13 via a constant current source 12 and the coupled emitters of transistors 5 and 6 are likewise connected to the positive supply potential 13 via a constant current source 14.
- the coupled emitters of transistors 3 and 4 or 5 and 6 are brought together via a cascode stage and connected to the output of an amplifier stage.
- the cascode stage consists of two npn bipolar transistors 15 and 16, the bases and emitters of which are each connected to one another.
- the coupled bases are connected to a reference potential 17.
- Emitters of transistors 15 and 16 are each connected to the coupled emitters of transistors 3 and 4 or 5 and 6.
- the coupled emitters of the transistors 15 and 16 are finally connected to the collector of an npn bipolar transistor 18, the emitter of which is supplied with the reference potential 11 and the base of which is supplied with an input signal 19.
- the transistor 18 forms a gear amplifier stage, but at the same time acts in conjunction with the cascode circuit 15, 16, 17 and the current sources 9, 10, 12, 14 as a controllable current source for the differential amplifiers 1 and 2.
- Passive phase shifters are each connected downstream of the current outputs of the differential amplifiers 1 and 2 forming collectors of transistors 3, 4, 5, 6 and are guided to an adder via the phase shifters.
- the adding stage acting as a combiner in turn contains four cascode stages, the outputs of which are combined in pairs and form the symmetrical output 20, 21 of the circuit arrangement according to the invention.
- the collectors of two npn bipolar transistors 22 and 23 are connected to one another and to the connection 20.
- the collectors of two npn bipolar transistors 24 and 25 are connected to one another and to the output terminal 21.
- the bases of the transistors 22, 23, 24, 25 are connected to one another and to the reference potential 17.
- the emitters of the transistors 22, 24 and 23, 25 represent the current inputs of the adder inputs, while the connections 20 and 21 form the symmetrical current inputs of the bias circuit and of the circuit arrangement according to the invention.
- the two phase shifters each connected between the differential amplifiers 1 and 2 and the adder are passive and are formed by an RC network.
- the collector of transistor 3 with the emitter of transistor 22, the collector of transistor 4 with the emitter of transistor 24, the collector of transistor 5 with the emitter of transistor 25 and the collector of transistor 6 with the emitter of Transistor 23 is connected via an ohmic resistor 26, 27, 28, 29.
- the collector of transistor 3 with the emitter of transistor 24, the collector of transistor 4 with the emitter of transistor 22, the collector of transistor 5 with the emitter of transistor 23 and the collector of the transistor 6 connected to the emitter of transistor 25 via a capacitor 30, 31, 32, 33, respectively.
- the differential amplifier stages 1 and 2 are each stacked one above the other, i. H. connected in series in terms of current.
- the input amplifier is used on the one hand for amplification and on the other hand for controlling the bias currents of differential amplifier stages 1 and 2 and thus for multiplication.
- the constant current sources 9, 10, 12, 14 each deliver the same current in the exemplary embodiment.
- the circuit is characterized by low effort, low bias currents and a low operating voltage. Due to the current coupling, no significant voltage control reserve is necessary and the impedance matching of the individual stages with each other is almost ideal.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99969857A EP1119903B1 (de) | 1998-09-30 | 1999-09-27 | Schaltungsanordnung zum mischen eines eingangssignals und eines oszillatorsignals miteinander |
JP2000572992A JP2002526957A (ja) | 1998-09-30 | 1999-09-27 | 入力信号と発振器信号相互の混合のための回路装置 |
US09/822,017 US6456144B2 (en) | 1998-09-30 | 2001-03-30 | Circuit configuration for mixing an input signal and an oscillator signal with one another |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19844970.4 | 1998-09-30 | ||
DE19844970A DE19844970C2 (de) | 1998-09-30 | 1998-09-30 | Schaltungsanordnung zum Mischen eines Eingangssignals und eines Oszillatorsignals miteinander |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/822,017 Continuation US6456144B2 (en) | 1998-09-30 | 2001-03-30 | Circuit configuration for mixing an input signal and an oscillator signal with one another |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000019599A1 true WO2000019599A1 (de) | 2000-04-06 |
Family
ID=7882879
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1999/003102 WO2000019599A1 (de) | 1998-09-30 | 1999-09-27 | Schaltungsanordnung zum mischen eines eingangssignals und eines oszillatorsignals miteinander |
Country Status (5)
Country | Link |
---|---|
US (1) | US6456144B2 (de) |
EP (1) | EP1119903B1 (de) |
JP (1) | JP2002526957A (de) |
DE (1) | DE19844970C2 (de) |
WO (1) | WO2000019599A1 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1184971A1 (de) * | 2000-08-17 | 2002-03-06 | Motorola, Inc. | Schaltmischstufe |
JP3958511B2 (ja) | 2000-09-28 | 2007-08-15 | 株式会社リコー | トナー補給装置および画像形成装置 |
EP1555582B1 (de) | 2001-01-31 | 2011-06-29 | Ricoh Company, Ltd. | Tonerbehälter und damit versehene Bilderzeugungsvorrichtung |
DE10134754A1 (de) * | 2001-07-17 | 2003-02-06 | Infineon Technologies Ag | Multipliziererschaltung |
US6741121B2 (en) * | 2002-08-27 | 2004-05-25 | Micron Technology, Inc. | Differential amplifier common mode noise compensation |
US6731150B2 (en) | 2002-08-28 | 2004-05-04 | Micron Technology, Inc. | Amplifiers with variable swing control |
US6693485B1 (en) | 2002-08-29 | 2004-02-17 | Micron Technology, Inc. | Differential amplifiers with increased input ranges |
US7183851B2 (en) * | 2004-06-30 | 2007-02-27 | Intel Corporation | Differential dual port current conveyor circuit |
DE102010012814A1 (de) | 2010-03-26 | 2011-09-29 | Rohde & Schwarz Gmbh & Co. Kg | Vorrichtung und Verfahren zur Erfassung von mobilen Endgeräten |
KR101259605B1 (ko) | 2011-12-05 | 2013-04-30 | 에이스웨이브텍(주) | 차동증폭기와 하이브리드 결합기를 이용한 주파수 위상 변환방법 |
US10171045B2 (en) | 2016-08-18 | 2019-01-01 | Skyworks Solutions, Inc. | Apparatus and methods for low noise amplifiers with mid-node impedance networks |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0434203A2 (de) * | 1989-12-16 | 1991-06-26 | Nortel Networks Corporation | Kreuzgekoppelte Mischerstufe für Zero-ZF-Funkempfänger |
EP0714163A1 (de) * | 1994-11-23 | 1996-05-29 | Analog Devices, Inc. | Mischer mit niedriger Versorgungsspannung |
EP0774832A1 (de) * | 1995-11-17 | 1997-05-21 | Nec Corporation | Quadraturdemodulator |
EP0853374A1 (de) * | 1997-01-11 | 1998-07-15 | Plessey Semiconductors Limited | Mischer mit Unterdrückung der Spiegelfrequenz |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4321549A (en) * | 1980-05-06 | 1982-03-23 | The United States Of America As Represented By The Secretary Of The Navy | Switching quadrature detector |
DE3412191A1 (de) * | 1984-04-02 | 1985-10-31 | Telefunken electronic GmbH, 7100 Heilbronn | Integrierbare empfaengerschaltung |
US4663594A (en) * | 1984-09-13 | 1987-05-05 | Motorola, Inc. | Electronic phase shifter circuit and method |
US4801900A (en) * | 1987-12-18 | 1989-01-31 | Unisys Corporation | Image reject apparatus for signal synthesis applications |
JPH0417405A (ja) * | 1990-05-10 | 1992-01-22 | Alps Electric Co Ltd | ミキサ回路 |
EP0660512B1 (de) * | 1993-12-22 | 1999-12-08 | Philips Composants Et Semiconducteurs | Phasenschiebverstärker und seine Verwendung in einer Zusammenführungsschaltung |
US5661485A (en) * | 1995-09-08 | 1997-08-26 | Condor Systems, Inc. | Homodyne receiver apparatus and method |
-
1998
- 1998-09-30 DE DE19844970A patent/DE19844970C2/de not_active Expired - Fee Related
-
1999
- 1999-09-27 EP EP99969857A patent/EP1119903B1/de not_active Expired - Lifetime
- 1999-09-27 WO PCT/DE1999/003102 patent/WO2000019599A1/de active IP Right Grant
- 1999-09-27 JP JP2000572992A patent/JP2002526957A/ja active Pending
-
2001
- 2001-03-30 US US09/822,017 patent/US6456144B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0434203A2 (de) * | 1989-12-16 | 1991-06-26 | Nortel Networks Corporation | Kreuzgekoppelte Mischerstufe für Zero-ZF-Funkempfänger |
EP0714163A1 (de) * | 1994-11-23 | 1996-05-29 | Analog Devices, Inc. | Mischer mit niedriger Versorgungsspannung |
EP0774832A1 (de) * | 1995-11-17 | 1997-05-21 | Nec Corporation | Quadraturdemodulator |
EP0853374A1 (de) * | 1997-01-11 | 1998-07-15 | Plessey Semiconductors Limited | Mischer mit Unterdrückung der Spiegelfrequenz |
Also Published As
Publication number | Publication date |
---|---|
JP2002526957A (ja) | 2002-08-20 |
EP1119903A1 (de) | 2001-08-01 |
DE19844970A1 (de) | 2000-04-27 |
EP1119903B1 (de) | 2002-05-29 |
US20010040477A1 (en) | 2001-11-15 |
US6456144B2 (en) | 2002-09-24 |
DE19844970C2 (de) | 2001-02-22 |
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