WO2000013359A1 - Systeme de communication numerique, emetteur et recepteur a cet effet et detecteur de synchronisation de trame - Google Patents
Systeme de communication numerique, emetteur et recepteur a cet effet et detecteur de synchronisation de trame Download PDFInfo
- Publication number
- WO2000013359A1 WO2000013359A1 PCT/JP1999/004583 JP9904583W WO0013359A1 WO 2000013359 A1 WO2000013359 A1 WO 2000013359A1 JP 9904583 W JP9904583 W JP 9904583W WO 0013359 A1 WO0013359 A1 WO 0013359A1
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- WO
- WIPO (PCT)
- Prior art keywords
- pattern
- basic
- inversion
- predetermined
- taps
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
Definitions
- the present invention relates to a digital communication system for transmitting frame-structured transmission data, such as a mobile communication system using a code division multiple access (CDMA) system, and a transmission device therefor.
- the present invention relates to a receiver and a frame synchronization detection circuit.
- a frame structure that creates one block every certain time is often used for error detection and use of correction codes, time multiplexing of control signals, and the like.
- Detection of the synchronization pattern on the receiving side can be realized by correlating the received data with the synchronization pattern prepared on the receiving side. Such processing is performed by using a match filter.
- the match filter generally has a transverse filter configuration as shown in FIG. 11, and the number of symbols constituting a synchronous pattern (in the example of FIG. 10 is shown in FIG. 10). It has the same number of taps as h).
- Each tap is connected to a multiplier 21 (2 1 —:! To 21 — h), and each symbol P (P 0 to P h — ⁇ ) of the synchronization pattern. The coefficients corresponding to are multiplied respectively. Then, the output of each multiplier 21 is added by the adder 22 to obtain a detection output.
- the detection output obtained by such a matched filter has, for example, a waveform as shown in FIG.
- the level of the detection output is significantly increased when all the symbols of the synchronization pattern appear in each tap, and the synchronization pattern is detected.
- the timing was completed. Therefore, the arrival timing of the synchronization pattern, that is, the frame timing, is detected.
- the number of symbols in the synchronization pattern may be increased.
- a synchronization detection circuit as shown in Fig. 14 is used.
- the output of the adder 14 that is, the level of the detection output becomes a peak. That is, synchronous detection can be performed.
- the number of taps required for the match filter 11 is basically as follows.
- the number of taps required for the matched filter formed by the delay unit 12 and the adder 14 is m, which is the same number of m as the number of symbols in the turn PA. So there is a synchronization of m x n symbols. Turn detection can be realized with m + n tap numbers. According to this method, even if a pattern having a small correlation at different positions is used as the basic pattern PA, the basic pattern pA is repeated. As a result, a large correlation is generated at the position where the time axis is shifted, so that the detection output has a waveform in which a plurality of peaks P11 to P17 are generated as shown in FIG.
- the timing of peak P11 which has the highest level, is the timing for detecting the synchronization pattern, but the level difference from other peaks is small.
- the detection accuracy could not be sufficiently improved.
- the purpose of the present invention is to provide a digital communication system and its transmitting and receiving devices capable of performing synchronization detection with high accuracy while having a simple configuration.
- Another object of the present invention is to provide a frame synchronization detection circuit.
- the present invention provides a transmitting device in a digital communication system, which includes a predetermined basic pattern including a predetermined number of symbols and a basic pattern.
- An order corresponding to a predetermined inversion pattern which is obtained by combining a basic inversion pattern obtained by inverting the polarity of each symbol of the pattern with a predetermined number of inversion information indicating a non-inversion position and an inversion position, respectively.
- a synchronous pattern generating means composed of a basic pattern storage unit and a synchronous pattern generating unit, and a synchronous pattern are divided, and the synchronous pattern is divided.
- the transmission data is frame-structured by adding the synchronization pattern generated by the generation means.
- the receiving apparatus has the same number of taps as the number of symbols included in the basic pattern, and at least some of the symbols included in the basic pattern are set.
- the delay time between taps is the same as the time between the note symbols, and the tap coefficient is equal to the note symbol.
- It has a first match filter set correspondingly and the same number of taps as the number of basic patterns and inverted basic patterns included in the synchronization pattern. The delay time between them is the same as the arrangement period of the basic pattern and the inverted basic pattern in the synchronous pattern, and as a tap coefficient, two predetermined values having different polarities from each other. Either one is the second set in accordance with the reverse pattern. It has a frame synchronization detection circuit that is connected in series with the match filter.
- the frame position of the transmission data is determined by a predetermined basic pattern consisting of a combination of a predetermined number of symbols and an inverted basic pattern obtained by inverting the polarity of each symbol of this basic pattern. And are indicated by a synchronization pattern arranged in an order corresponding to a predetermined inversion pattern.
- the receiver synchronizes the frame by detecting this synchronization pattern.However, the basic pattern and the first match filter corresponding to the symbol of the basic pattern are noted. The process of correlating the symbol of interest in the inverted basic pattern and the process of correlating the inverted pattern with a second matched filter corresponding to the inverted pattern are compared. Synchronous pattern is obtained by performing serially before and after. An error is detected.
- the inversion pattern is based on a combination of two types of inversion presence / absence information having different polarities, all of the inversion patterns are aligned with the second match filter. In some cases, the reversal information is canceled out, and the output level of the second matched filter is reduced.
- the synchronization pattern transmitted by the transmitting apparatus of the present invention has the same number of touch symbols as the number of the attention symbols set as a part of the symbols included in the synchronization pattern.
- the delay time between the taps is the same as the time between the attention symbols, and the tap coefficient is set to match the attention symbols.
- It has a frame synchronization detection circuit consisting of a filter and the same number of taps as the number of symbols included in the synchronization pattern, and the delay time between the taps is the same as the symbol period.
- the same, and the tap coefficient is Detected by a frame synchronization detection circuit consisting of a match filter set in accordance with the pattern.
- the synchronization pattern can be detected even by a conventional frame synchronization detection circuit.
- FIG. 1 is a block diagram showing a main configuration of a transmission device in a digital communication system according to an embodiment of the present invention.
- FIG. 2 is a diagram showing a configuration of a basic pattern used in an embodiment of the present invention.
- FIG. 3 is a diagram showing a configuration of an inverted pattern used in one embodiment of the present invention.
- FIG. 4 is a diagram showing a structure of a synchronization pattern used in one embodiment of the present invention.
- FIG. 5 is a diagram showing a specific example of a synchronization pattern used in one embodiment of the present invention.
- FIG. 6 is a diagram that specifically shows how synchronization patterns are generated.
- FIG. 7 is a diagram showing a configuration of a frame synchronization detection circuit provided in the receiving device in the digital communication system according to one embodiment of the present invention.
- FIG. 8 is a diagram showing an example of an output waveform of the matched filter 11 in FIG.
- FIG. 9 is a diagram showing an example of a waveform of a detection output in the frame synchronization detection circuit shown in FIG.
- FIG. 10 is a diagram showing a conventional example of a frame configuration of transmission data in a digital communication system.
- Figure 11 shows the general structure of a match filter for detecting frame synchronization.
- FIG. 12 is a diagram showing an example of a waveform of a detection output of the matched filter shown in FIG. 11;
- FIG. 13 is a diagram showing a configuration of a synchronous pattern formed by repeating a basic pattern an integer number of times.
- FIG. 14 is a block diagram showing a configuration of a synchronization detection circuit that performs synchronization detection based on the synchronization pattern shown in FIG.
- FIG. 15 is a diagram showing an example of an output waveform of the match filter 11 in FIG.
- FIG. 16 is a diagram showing an example of a detection output waveform of the synchronization detection circuit shown in FIG. 14;
- FIG. 1 is a block diagram showing a main configuration of a transmission device in a digital communication system according to the present embodiment. Note that this transmission device can be applied to “wid e b a n d C D M A”
- the transmission apparatus of the present embodiment has a basic pattern storage unit 1, a synchronization pattern generation unit 2, and a frame formation unit 3, and has a configuration.
- the basic pattern storage unit 1 is, for example, an R-M color, and stores a basic pattern and an inverted basic pattern. As shown in Fig. 2, the basic pattern consists of m pieces of “1” or “0”, respectively. Thin Bol S a (S ao ⁇ S a m ⁇ ) force Ru Rana. As the basic pattern, a code string having a low autocorrelation, such as an orthogonal Gold code, is used. The inverted basic pattern is obtained by inverting the polarity of each symbol with respect to the basic pattern (rotating ⁇ on the IQ plane).
- the synchronization pattern generation unit 2 arranges the basic pattern and the inverted basic pattern stored in the basic pattern storage unit 1 according to a predetermined inverted pattern, and generates a synchronous pattern.
- the generated inversion pattern is composed of n pieces of inversion information B (B0 to Bn- 1).
- the inversion information B indicates whether to arrange the basic pattern or the inverted basic pattern. Specifically, the inversion information B is set to “1” at the arrangement position of the basic pattern, and is set to “1 1” at the arrangement position of the inverted basic pattern.
- this inversion pattern shows the configuration of a synchronization pattern composed of a combination of n basic patterns and inversion basic patterns.
- the frame forming unit 3 divides transmission data provided for transmission at predetermined time intervals. Then, the frame forming section 3 adds the synchronization pattern given from the synchronization pattern generation section 2 to the transmission data at predetermined time intervals, thereby converting the transmission data into a frame structure. Become
- the synchronization pattern generation unit 2 repeats and arranges n basic patterns PA, and multiplies each basic pattern by an inverted pattern as shown in FIG. Such synchronization pattern Is generated.
- n is set to “4”, and the reversal pattern ⁇ B 0, B! , B 2, B 3 ⁇ are ⁇ 1, 1, 1, 1 ⁇ , as shown in FIG. 5, one basic pattern PA followed by three basic patterns PA Is generated, a synchronous pattern is generated.
- Fig. 6 shows more specifically how such a synchronization pattern is generated.
- the symbol number m of the turn PA is defined as “16”, and ⁇ 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 1, 0 ⁇ Naru no. Turn as a turn.
- the number of symbols in the turn is “64”, but it is usually “256”. That is, if the basic pattern PA is the above-described pattern, the number of repetitions n is set to “16”. When the number of repetitions n is “16”, the reversal pattern is ⁇ 1,1,1,1,11, —1,1,1,1,1,1,1,1,1,1, — For example, a pattern such as 1, 1, 11, 11, 1 ⁇ can be applied.
- n is set to “4”, and the inversion pattern is assumed to be ⁇ 11, 11 1, 1 ⁇ .
- the number of symbols in the synchronization pattern is “25 6”
- the number m of symbols in the basic pattern PA is “16”
- the number n of repetitions is “16”
- the synchronization pattern is
- the receiving apparatus in the digital communication system according to the present embodiment is provided with a frame synchronization detecting circuit having the configuration shown in FIG.
- FIG. 7 the same parts as those in FIG. 14 are denoted by the same reference numerals.
- An application of this receiver is a mobile station in a “wideband CDMA” (W—CDMA) type mobile communication system.
- W—CDMA wideband CDMA
- Match filter 11 is a basic filter. It corresponds to Turn PA. That is, the matched filter 11 has m taps, the same as the number of symbols in the basic pattern PA, and the delay time between taps is the same as the symbol period. In addition, one of “1” and [—1 ”is a basic pattern P as a tap coefficient. Set for A.
- the delay unit 1 2 is connected in series in the order of the delay units 1 2-1, 1 2-2 ′′ ⁇ , 1 2 1 J, 1 2-k.
- the output of the match filter 11 is given to the delay section 12-1 in the previous stage and is then viewed. Therefore, each delay unit 12 sequentially delays the output from the match filter 11.
- the delay time of each delay unit 12 is as follows: basic time, zero turn PA and inverted basic time. It is set to the repetition period Tr of the turn / PA.
- Multiplier 1 3 has 1 3 — k ′′, 1 3-2, 1 3 1 1, and delay section 1 2 —:! 1 1 2 — Connected to each output of k.
- the multipliers 13-n are connected to the output ⁇ : of the matched filter 11. Then, these multipliers 13 — 1 to 13 ⁇ are inverted. ⁇ 0 ⁇ ⁇ at the turn is set as a tap coefficient, and this tap coefficient is multiplied to the input.
- Adder 1 4 is a multiplier 1 3 —:! 11 3 — Calculates the sum of the outputs of ⁇ , and outputs a detection output at a level corresponding to the calculated sum.
- the delay unit 12, the multiplier 13 and the adder 14 constitute a matched filter corresponding to the inversion pattern.
- the match filter 11 When the synchronization pattern generated by the transmitting apparatus as described above is input to this frame synchronization detection circuit, the match filter 11 outputs the basic pattern. Or, a peak is generated at the output every time the inverted basic pattern is aligned. As a result, the synchronization pattern For each input to the filter, the output of the matched filter 11 1 has the same number of peaks as the number of repetitions n.
- the polarities of the peak when the basic pattern is aligned in the match filter 11 and the peak when the inverted basic pattern is aligned are opposite to each other.
- the output of the match filter 11 has a waveform in which a peak occurs in accordance with the inversion pattern. For example, if the number of repetitions n is “4” and the inversion and zero turn are ⁇ —1, 1, 1, 1 ⁇ , a waveform as shown in FIG. 8 is obtained.
- a more configured match filter correlates with the inversion pattern.
- the n peaks at the output of the match filter 11 correspond to the match filter constituted by the delay unit 12, the multiplier 13 and the adder 14.
- a peak is generated in the detection output at the time when each tap of the filter is completed.
- peaks also occur in the detection output at positions where the time axis is shifted.
- the peak of the peak is opposite in polarity when a part of n peaks in the signal output from the match filter 11 is input to the adder 14. Therefore, they cancel each other, and the level becomes small.
- the detection output will have a waveform as shown in FIG. Become. Then, the true frame sync timer Second, the absolute value of the peak p1, which has the largest absolute value, is larger than the absolute value of the peak, and the absolute values of the level peaks P2, P3, P4, and P5 becomes 1/4.
- the detection of the true peak that is, the detection of the frame synchronization timing is performed.
- the accuracy is improved.
- the number of taps included in the frame synchronization detection circuit in the present embodiment is m + n, which is smaller than the number m X n of symbols of the synchronization pattern.
- the symbol number m of the basic pattern P A is “16” and the number of repetitions n is “16”, the synchronization is not performed.
- the number of symbols in the turn is “256”, whereas the number of taps is “68”. Therefore, synchronization, Circuit size and current consumption can be reduced as compared with the case where a matched filter corresponding to the entire turn is used.
- the absolute value of the peak with the second largest absolute value is 1/4 of the absolute value of the peak with the largest absolute value.
- this varies depending on the setting of the reverse pattern.
- the inversion pattern is ⁇ 1, 11, 11 ⁇
- the level of the second largest absolute value is higher than the absolute value of the peak with the largest absolute value.
- the absolute value of the peak will be 2Z4, and the level difference will decrease.
- Examples of appropriate inversion patterns when the number of repetitions n is “4” are ⁇ 11, 1, 1, 1, 1 ⁇ and ⁇ 1, 11, 11, 1, 1 ⁇ . .
- these appropriate inversion patterns are expressed as ⁇ B a, B b, B c, B d ⁇ , the inversion is ⁇ —B a, one B b, -B e, -B d ⁇
- ⁇ B d, B c, B b, B a ⁇ which is a change of the order, is also a suitable inversion pattern.
- the present invention is not limited to the above embodiment.
- the generation of the synchronization pattern in the transmission device may be performed by a logic circuit.
- both the basic pattern and the inverted basic pattern are stored in the basic pattern storage unit 1.
- only the basic pattern is stored in the basic pattern storage unit 1.
- the polarity may be inverted to create an inverted basic pattern.
- each symbol of the synchronization pattern is binary, but the present invention can be applied to a case where the symbol is multi-valued / complex.
- the processing performed by the frame synchronization detection circuit of the present embodiment is a linear conversion, and includes a match filter 11, a delay section 12, a multiplier 13, and an adder 14. It is up to you to swap the order with a different match filter.
- the synchronization pattern is arranged at the beginning of the frame.
- the synchronization pattern is arranged at an arbitrary position other than the beginning determined by the system, the above effect can be obtained. it is obvious.
- the match filter 11 is based on the entire basic pattern, but only some of the symbols in the basic pattern are used.
- the matched filter 11 may be a symbol corresponding to only the eye symbol.
- the synchronization pattern transmitted by the transmission apparatus of the above embodiment can be obtained by a general frame synchronization detection circuit including one matched frame as shown in FIG. It is possible to detect. And even in this case, even if the matched freight shown in FIG. 11 corresponds to the entire synchronization pattern, or it is synchronized. It is also possible to use only a part of the symbols of the turn as the attention symbol, and to make the match filter shown in FIG. 11 correspond to only the attention symbol.
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- Synchronisation In Digital Transmission Systems (AREA)
- Mobile Radio Communication Systems (AREA)
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99940475A EP1037423A4 (en) | 1998-08-28 | 1999-08-25 | DIGITAL COMMUNICATION SYSTEM, TRANSMITTER AND RECEIVER THEREFOR AND FRAME SYNCHRONIZATION DETECTOR |
US09/558,098 US6658072B1 (en) | 1998-08-28 | 2000-04-25 | Digital communication system transmitting and receiving devices therefor and frame synchronization detection circuit |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24394798 | 1998-08-28 | ||
JP10/243947 | 1998-08-28 | ||
JP29980098 | 1998-10-21 | ||
JP10/299800 | 1998-10-21 | ||
JP10/313400 | 1998-11-04 | ||
JP31340098A JP2955576B1 (ja) | 1998-08-28 | 1998-11-04 | ディジタル通信システムとその送信装置および受信装置、ならびにフレーム同期検出回路 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/558,098 Continuation US6658072B1 (en) | 1998-08-28 | 2000-04-25 | Digital communication system transmitting and receiving devices therefor and frame synchronization detection circuit |
Publications (1)
Publication Number | Publication Date |
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WO2000013359A1 true WO2000013359A1 (fr) | 2000-03-09 |
Family
ID=27333190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP1999/004583 WO2000013359A1 (fr) | 1998-08-28 | 1999-08-25 | Systeme de communication numerique, emetteur et recepteur a cet effet et detecteur de synchronisation de trame |
Country Status (4)
Country | Link |
---|---|
US (1) | US6658072B1 (ja) |
EP (1) | EP1037423A4 (ja) |
JP (1) | JP2955576B1 (ja) |
WO (1) | WO2000013359A1 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3387079B2 (ja) | 1999-03-01 | 2003-03-17 | 日本電気株式会社 | 相関値検出装置、それを有するスペクトラム逆拡散装置、受信端末及び送受信端末並びに相関値検出方法 |
JP3363107B2 (ja) | 1999-03-01 | 2003-01-08 | 日本電気株式会社 | 相関値検出装置、それを有するスペクトラム逆拡散装置、受信端末及び送受信端末並びに相関値検出方法 |
JP3296341B2 (ja) * | 1999-09-20 | 2002-06-24 | 日本電気株式会社 | 相関器 |
JP2003198523A (ja) * | 2001-12-27 | 2003-07-11 | Matsushita Electric Ind Co Ltd | 同期検出装置および同期検出方法 |
KR100667785B1 (ko) * | 2004-12-16 | 2007-01-12 | 삼성전자주식회사 | 카오스 기반 통신 시스템에서 동기화 방법 및 장치, 위치인식 방법 및 장치 |
US7801107B2 (en) * | 2006-05-25 | 2010-09-21 | Mitsubishi Electric Research Laboratories, Inc. | Method for transmitting a communications packet in a wireless communications network |
EP2061170B1 (en) * | 2006-09-11 | 2014-11-12 | Inventergy, Inc. | Ofdm transmitter and ofdm receiver |
GB2444307A (en) * | 2006-12-01 | 2008-06-04 | Plextek Ltd | Extracting timing data from a two part preamble, the second part of the preamble being the inverse of the first part. |
US8194529B2 (en) * | 2008-09-08 | 2012-06-05 | Sony Corporation | Frame and data pattern structure for multi-carrier systems |
US8665691B2 (en) * | 2009-02-05 | 2014-03-04 | Sony Corporation | Frame and data pattern structure for multi-carrier systems |
EP2216928B1 (en) * | 2009-02-05 | 2012-12-19 | Sony Corporation | Frame and data pattern structure for multi-carrier systems |
EP2701334B1 (en) | 2011-04-21 | 2016-06-29 | Fujitsu Limited | Data reception apparatus and marker information extraction method |
US9491025B2 (en) * | 2013-07-25 | 2016-11-08 | Empire Technology Development Llc | Timing synchronization in an orthogonal frequency-division multiplexing (OFDM) system |
JP6592558B1 (ja) * | 2018-06-07 | 2019-10-16 | Nttエレクトロニクス株式会社 | フレーム同期装置、光通信装置およびフレーム同期方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
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NL7110022A (ja) * | 1971-07-21 | 1973-01-23 | ||
US4688218A (en) * | 1981-07-15 | 1987-08-18 | Etablissement Public De Diffusion Dit "Telediffusion De France" | Multiplex channels for continuous flow for numerical signal |
US5388126A (en) * | 1992-12-21 | 1995-02-07 | Rypinski; Chandos A. | Baseband signal processor for a microwave radio receiver |
FR2721466B1 (fr) * | 1994-06-21 | 1996-07-26 | Alcatel Mobile Comm France | Signal de contrôle pour récepteurs, dispositif de synchronisation, dispositif d'égalisation, procédé de synchronisation et récepteurs correspondants. |
US6049576A (en) * | 1996-10-29 | 2000-04-11 | Stanford Telecommunications, Inc. | Kronecker product code acquisition system |
-
1998
- 1998-11-04 JP JP31340098A patent/JP2955576B1/ja not_active Expired - Fee Related
-
1999
- 1999-08-25 WO PCT/JP1999/004583 patent/WO2000013359A1/ja not_active Application Discontinuation
- 1999-08-25 EP EP99940475A patent/EP1037423A4/en not_active Withdrawn
-
2000
- 2000-04-25 US US09/558,098 patent/US6658072B1/en not_active Expired - Lifetime
Non-Patent Citations (3)
Title |
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"The latest method of spectral diffusion communication", R.C. DIXON, translation by Tachino, Ed. JATECK, pages 204-205, 30 November 1978, XP002926597 * |
See also references of EP1037423A4 * |
TACHIKAWA S-I, YUKAWA T, MARUBAYASHI G: "NONLINER CODE SEQUENCE FOR RAPID ACQUISITION", TECHNICAL RESEARCH REPORT STUDY GROUP II , SPECTRAL DIFFUSIONCOMMUNICATION, XX, XX, 25 March 1987 (1987-03-25), XX, pages 39 - 45, XP002926596 * |
Also Published As
Publication number | Publication date |
---|---|
JP2955576B1 (ja) | 1999-10-04 |
JP2000196498A (ja) | 2000-07-14 |
EP1037423A4 (en) | 2004-11-17 |
EP1037423A1 (en) | 2000-09-20 |
US6658072B1 (en) | 2003-12-02 |
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