WO1999053639A1 - Unite de commande de noeud d'un noeud d'acces dans un reseau de telecommunication - Google Patents

Unite de commande de noeud d'un noeud d'acces dans un reseau de telecommunication Download PDF

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Publication number
WO1999053639A1
WO1999053639A1 PCT/EP1998/002091 EP9802091W WO9953639A1 WO 1999053639 A1 WO1999053639 A1 WO 1999053639A1 EP 9802091 W EP9802091 W EP 9802091W WO 9953639 A1 WO9953639 A1 WO 9953639A1
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WO
WIPO (PCT)
Prior art keywords
sel
control unit
sec
output
signal
Prior art date
Application number
PCT/EP1998/002091
Other languages
English (en)
Inventor
Antti Poutanen
Seppo Peltola
Original Assignee
Nokia Networks Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Networks Oy filed Critical Nokia Networks Oy
Priority to PCT/EP1998/002091 priority Critical patent/WO1999053639A1/fr
Priority to AU77582/98A priority patent/AU7758298A/en
Publication of WO1999053639A1 publication Critical patent/WO1999053639A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master

Definitions

  • the invention relates to a node control unit of an access node in a telecommunications network including input ports for receiving reference signals and output ports for supplying to a node clock access line a synchronous equipment clock signal generated by an analog voltage controlled oscillator, forming part of a phase locked loop circuit for synchronizing the synchronous equipment clock signal with one of the received reference clock signals, the phase locked loop circuit being supplied at one of its inputs with one of the received reference clock signals and at one of the other inputs with the output signal of the analog voltage controlled oscillator.
  • Node control units used for providing a synchronous equipment clock signal to node elements are well known in telecommunication systems.
  • Fig. 2 shows the implementation of a conventional system for synchronous equipment clock supply. The implementation receives several reference clock signals and outputs a synchronous system clock as well as reference clock signals.
  • Digital clock selectors have inputs for unit internal reference signals from internal signal lines LINE_REF#1- #4 and signals originating from tributary units via reference lines RCLK1-4, the signals coming from reference lines RCLK1-4 being monitored by an analog loss-of-signal detector, respectively.
  • the clock selectors receive moreover an external reference signal - 2 -
  • an analog NRZ (non return to zero) interface via an G.703 interface, an analog NRZ (non return to zero) interface and an analog clock recovery device.
  • the output of the clock recovery device is further supplied to an analog G.704 framer device, controlled by a microprocessor .
  • One of the reference signals selected by the clock selectors is passed on to an analog phase locked loop, comprising analog loop counters and a phase detector, an analog low pass filter, an AD/DA memory circuitry controlled by a microprocessor, and an analog voltage controlled oscillator (VCO) circuitry.
  • the output of the VCO is supplied as system clock to a node clock access line .
  • Reference signals selected by the clock selectors are passed on to reference clock lines RCLK1- .
  • a last reference signal selected by the clock selectors is supplied to a second phase locked loop comprising as well analog loop counters and a phase detector, an analog low pass filter and an analog voltage controlled oscillator circuitry.
  • the output of this oscillator is supplied to a microprocessor controlled analog G.704 framer device.
  • An G.703 interface and an NRZ interface receive the signal from the G.704 framer device and supply an external reference signal.
  • the node clock system of the state of the art comprises a great amount of analog electronic circuitry, which is expensive to install and which is not very reliable. Analog phase locked loops require moreover intensive testing in mass production. - 3 -
  • the object is achieved according to the invention with a node control unit of the preamble, in which the phase locked loop circuit connected to the analog voltage controlled oscillator is realized in a single electronic component .
  • the single electronic component in which the first phase locked loop is partly integrated comprises additionally a fully digitally realized second phase locked loop connected to a second digital oscillator for generating a clock signal used for synchronization of external network elements, the second phase locked loop receiving at one of its inputs one of the reference clock signals and at another of its inputs the output of the second oscillator.
  • a fully digitized and integrated phase locked loop implementation does not need any calibration or tuning in the production, which leads to a reduction of costs.
  • the partially digitized phase locked loop can be calibrated by a completely automated software operation.
  • the integration of a plurality of elements of the node control unit on a VLSI chip allows to implement many functions with very close logical operations together, especially selectors, dividers and loss-of-signal detectors, in order to reduce system noise and cross talk.
  • the integration of different digital functions, most of which are realized in the state of the art as analog functions, to one VLSI-chip increase the reliability of the system. This is particularly of importance, since a synchronous equipment clock is also used as master clock source of the system.
  • the invention preferably isolates all functions of a synchronous equipment clock to one VLSI-chip, thereby increasing the integration level in the telecommunication network.
  • the invention furthermore makes it possible to implement the clock function considerably cheaper than it can be done with a conventional implementation.
  • a VLSI-chip for a node control unit according to the invention can be obtained with conventional semiconductor technology. - 5 -
  • the reduced number of physical devices moreover reduces the power consumption of the synchronous equipment clock and results in a very small physical PCB board space in the unit, approximately one fourth compared to conventional system equipment clocks.
  • Fig. 1 shows a preferred embodiment of a node control unit according to the invention
  • Fig. 2 shows an implementation of a conventional node control unit.
  • Figure 1 shows those elements of a node control unit that are used for node clock supply.
  • most of the elements are integrated on a VLSI- chip, which is supplied with several reference clock signals and which outputs synchronous clock signals for node elements and external network elements .
  • the input ports are provided four input ports connected to reference clock lines RCLK1-4 carrying reference clock signals provided by tributary units of other access nodes of the network, the input ports being accessed via software controlled buffers B.
  • the input ports are connected to a reference selection bus RSB for 16 kHz, the connection being monitored by a loss-of-signal monitoring LOS. - 6 -
  • VLSI-chip has programmable dividers D1-D4, the output of which is supplied to the reference selection bus RSB as well.
  • an input port supplied with an external reference signal EXT2MREF coming from outside the system, i.e., either from another access node or from an atom clock.
  • the signal external first passes an G.703 interface, connected to an analog loss-of-signal monitoring ALOS, and reaches the input port via a dual/single rail TTL transceiver (not shown) .
  • the input port is connected to a digital loss-of-signal monitoring DLOS, to a "non return to zero" signal line coding NRZl and to a HDB3-decoder .
  • the output of the HDB3-decoder is connected to a G.704 framer, outputting an synchronization message SSM.
  • the output of both, NRZl and HDB3-decoder, are connected via a selector to a digital clock recovery PLL CDR (Clock and Data Recovery) .
  • the CDR has another input connected to an external analog 65 MHz oscillator OSI.
  • the output of the digital clock recovery PLL CDR is passed via another programmable divider D5 to the reference selection bus RSB.
  • the reference selection bus RSB provides signals for six different selectors SECPLL_SEL, REF1_SEL, REF2_SEL, REF3_SEL, REF4_SEL and REFPLL_SEL.
  • the first selector SECPLL_SEL receive as inputs reference signals from signal lines RCLK1, RCLK2 , LINE REF #l-#4 and the external reference signal EXT2MREF.
  • the output of this selector SECPLL_SEL is connected via a first loop counter LCla, a phase detector PD1, a low pass filter LPF1 and a pulse width modulator PWM with an external analog crystal voltage controlled oscillator SEC_VCO.
  • the output of the oscillator SEC__VCO is passed on one hand via a software controlled buffer B to a node clock access line NCLK.
  • the output of the oscillator SEC_VCO is fed back to a second loop counter LClb of the phase locked loop, which provides the second input of the phase detector PD1 of the phase locked loop.
  • Phase detector PD1 and low pass filter LPF1 furthermore supply a signal to the software, while the low pass filter LPF1 also receives a signal from the software.
  • the signal generated by the first voltage controlled oscillator SEC_VCO is moreover provided as a 32 kHz RTC- signal after having passed a divider D7 integrated on the VLSI-chip and dividing the frequency of signals by 768.
  • selectors REF1_SEL, REF2_SEL, REF3_SEL, REF4_SEL all receive as inputs the reference signals from LINE REF #l-#4 and the external 2M reference signal.
  • Each of those selectors REF1_SEL, REF2_SEL, REF3_SEL, REF4_SEL has an output connected via external software controlled buffers B to reference clock lines RCLK1-4, respectively.
  • the last selector REFPLL_SEL receives as inputs reference signals from signal lines RCLK1-4 and LINE REF #l-#4. Additionally, there is provided an input for the outputted signal of the SEC_VCO via a programmable divider D6.
  • the output of the selector REFPLL_SEL is connected via a first loop counter LC2a, a phase detector PD2 and a low pass filter LPF2 with a digital numerical controlled oscillator NCO, which is also integrated on the VLSI- - 8 -
  • phase detector PD2 supplies a signal to the software.
  • the output of the oscillator NCO is moreover passed on to a signal line coding NRZ2 and to a G.704 framing.
  • the G.704 framing which receives at another input synchronization messages SSM, is connected to the input of a HDB3-coder receiving an alarm indicating signal AIS coming from the next functional block or from a reference point.
  • the output of signal line coding NRZ2 and HDB3- coder passes via a selector and provides the input for a external G.703 interface, which is connected via another software controlled buffer B with an external 2M reference line.
  • VLSI-chip The functioning of the VLSI-chip is the following:
  • the reference selection bus RSB supplies several reference clock signals to the different selectors, which may choose the best one as reference for node clock supply, synchronization etc., according e.g. to a received synchronization message. All signals transmitted by the bus are of 16 kHz.
  • the reference signals coming from signal lines RCLK1-4 can be forwarded directly to the bus RSB.
  • the reference signals from lines LINE_REF#1- #4, though, can be of 16kHz, but also of 64k, 192k, 2048k or 19440kHz. Therefore, the frequency of the incoming signals from these lines first have to pass dividers Dl- D4 before having access to the bus RSB.
  • the dividers Dl- D4 can be programmed to divide the frequencies of - 9 -
  • the LOS detector of the selected reference signal from one of the reference lines RCLK1-RCLK4, LINE REF #l-#4 is used also to initiate a fast transition to a "hold-over state" of the first phase locked loop SEC_PLL.
  • an incoming external reference signal is treated depends on whether it is a signal of 2.048 MHz or of 2.048 Mbit/s.
  • a 2.048 MHz reference signal always passes the non return to zero signal line coding NRZl.
  • a 2.048 Mbit/s reference signal is passed via the HDB3-decoder for converting it to a 2.048 MHz signal. Both kinds of signals are used in the following for synchronizing the digital clock recovery PLL, which uses the external 65 MHz oscillator for sampling, before supplying the resulting signal, via a divider D5 dividing the frequency of the signal by 128, as a signal of 16kHz to the reference selection bus.
  • the G.704 termination which is also integrated in the chip, can be used for extracting synchronization messages SSM from the signal outputted by the HDB3 decoder.
  • Each selector SECPLL_SEL, REF1_SEL, REF2_SEL, REF3_SEL, REF4_SEL and REFPLL_SEL selects from those reference signals on the reference selection bus to which it has access the best one, e.g. according to a synchronization message .
  • the first phase locked loop SEC_PLL is used to filter a selected reference clock signal so that the output - 10 -
  • the first loop counter LCla of the first phase locked loop SEC_PLL counts the loops of the signal provided by the selector SECPLL_SEL divided by 2 and the second loop counter LClb counts the loops of the signal generated by the oscillator SEC_VCO, which outputs a signal of 24576 kHz, divided by 1536.
  • the phase detector PD1 compares the phase difference between the output of the two loop counters LCla, LClb. When the presently selected reference signal fails, the phase detector PD1 is no longer able to determine a useful phase difference. In this case the software is informed via an UNLOCK signal that another reference signal has to be selected. The result of the phase detector PDl is passed on via the low pass filter LPFl to the pulse width modulator PWM.
  • control loop of the phase locked loop SEC_PLL can be opened and controlled by a processor.
  • the digital value of the output of the phase detector PDl is read by the processor and the output value of the digital low pass filter LPFl is replaced with a value written in a register by the processor.
  • the processor can read the value of the output of the phase detector PDl for statistical processing.
  • the processor can also add some off-set to the closed loop control signal for calibration or dynamic output phase management purposes .
  • the output of the pulse width modulator PWM exits also the VLSI-chip and is used to control the voltage controlled oscillator SEC_VC0 generating a sinus clock signal with a frequency of 24576 kHz.
  • This clock signal is supplied to a node clock access line NCLK for clock supply of all node elements, like the tributary units. - 11 -
  • the operations of the selector SECPLL_SEL are synchronized with the phase detector PDl to achieve the required low phase hit during the clock switching.
  • the signals outputted by the selectors REF1_SEL-REF4_SEL are not processed any further within the VLSI-chip.
  • the selected reference signals are forwarded directly to reference clock lines RCLK1-4.
  • the last selector REFPLL_SEL supplies a selected reference signal to the second phase locked loop REF_PLL, which works basically like the first phase locked loop SEC_PLL.
  • the used oscillator is a numerical controlled oscillator NCO and is integrated on the VLSI-chip, receiving only a sampling signal with a frequency of 65526 kHz from an external oscillator 0S2, which may be the same as the first sampling oscillator OSI used for sampling by the digital clock recovery PLL CDR.
  • the second loop counter LC2b of this phase locked loop REF_PLL counts the loops of the numeric controlled oscillator NCO divided by 256.
  • the signal outputted by the NCO is used to synchronize external network elements or to provide a more stable frequency source for the node clock. It can be outputted via the signal line coding NRZ2 as 2.048 MHz signal or via G.704 framing and HDB3-coder as 2.048 Mbit/s signal.
  • a synchronization message SSM that is to be encoded and transmitted can be inputted to the G.704 framing for this purpose. If some functional block or reference point does not receive a valid signal, it transmits to the HDB3- coder an alarm indication signal AIS, which may include - 12 -

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention concerne une unité de commande de noeud d'un noeud d'accès dans un réseau de télécommunication. Cette unité comprend des ports d'entrée pour recevoir des signaux de référence et des ports de sortie pour fournir à une ligne d'accès d'horloge de noeud (NCLK) un signal d'horloge d'équipement synchrone généré par un oscillateur à commande de tension analogique (SEC_VCO) faisant partie d'un circuit à boucle à phase asservie (SEC_PLL) pour synchroniser le signal d'horloge du matériel synchrone avec un des signaux d'horloge de référence reçus. Le circuit à boucle à phase asservie (SEC_PLL) est alimenté, au niveau d'une de ses entrées, avec un des signaux d'horloge de référence reçus, et au niveau de l'autre de ses entrées avec le signal de sortie de l'oscillateur à commande de tension analogique (SEC_VCO). Selon l'invention, le circuit à boucle à phase asservie (SEC_PLL) connecté audit oscillateur à commande de tension analogique (SEC_VCO) fonctionne de manière numérique dans un seul composant électronique, pour obtenir une unité de commande de noeud améliorée alimentant l'horloge. Le circuit à boucle à phase asservie (SEC_PLL) connecté à l'oscillateur à commande de tension analogique (SEC_VCO) fonctionne de manière numérique dans un seul composant électronique.
PCT/EP1998/002091 1998-04-09 1998-04-09 Unite de commande de noeud d'un noeud d'acces dans un reseau de telecommunication WO1999053639A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/EP1998/002091 WO1999053639A1 (fr) 1998-04-09 1998-04-09 Unite de commande de noeud d'un noeud d'acces dans un reseau de telecommunication
AU77582/98A AU7758298A (en) 1998-04-09 1998-04-09 Node control unit of an access node in a telecommunications network

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP1998/002091 WO1999053639A1 (fr) 1998-04-09 1998-04-09 Unite de commande de noeud d'un noeud d'acces dans un reseau de telecommunication

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WO1999053639A1 true WO1999053639A1 (fr) 1999-10-21

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4521918A (en) * 1980-11-10 1985-06-04 General Electric Company Battery saving frequency synthesizer arrangement
US4633193A (en) * 1985-12-02 1986-12-30 At&T Bell Laboratories Clock circuit synchronizer using a frequency synthesizer controlled by a frequency estimator
EP0517431A1 (fr) * 1991-05-28 1992-12-09 Codex Corporation Circuit et procédé de commutation entre horloges redondantes pour une boucle à verrouillage de phase
WO1993014570A1 (fr) * 1992-01-20 1993-07-22 Asea Brown Boveri Ab Procede et dispositif de reglage d'un signal d'impulsions d'horloge generees de maniere interne

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4521918A (en) * 1980-11-10 1985-06-04 General Electric Company Battery saving frequency synthesizer arrangement
US4633193A (en) * 1985-12-02 1986-12-30 At&T Bell Laboratories Clock circuit synchronizer using a frequency synthesizer controlled by a frequency estimator
EP0517431A1 (fr) * 1991-05-28 1992-12-09 Codex Corporation Circuit et procédé de commutation entre horloges redondantes pour une boucle à verrouillage de phase
WO1993014570A1 (fr) * 1992-01-20 1993-07-22 Asea Brown Boveri Ab Procede et dispositif de reglage d'un signal d'impulsions d'horloge generees de maniere interne

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Publication number Publication date
AU7758298A (en) 1999-11-01

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