WO1999049604A1 - Procede de transmission de donnees, codeur et decodeur - Google Patents

Procede de transmission de donnees, codeur et decodeur Download PDF

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Publication number
WO1999049604A1
WO1999049604A1 PCT/DE1999/000575 DE9900575W WO9949604A1 WO 1999049604 A1 WO1999049604 A1 WO 1999049604A1 DE 9900575 W DE9900575 W DE 9900575W WO 9949604 A1 WO9949604 A1 WO 9949604A1
Authority
WO
WIPO (PCT)
Prior art keywords
data packets
poh
data
user data
control information
Prior art date
Application number
PCT/DE1999/000575
Other languages
German (de)
English (en)
Inventor
Siegfried Huber
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to CA002325448A priority Critical patent/CA2325448A1/fr
Priority to EP99913107A priority patent/EP1064746A1/fr
Publication of WO1999049604A1 publication Critical patent/WO1999049604A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H04J2203/0094—Virtual Concatenation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5649—Cell delay or jitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/565—Sequence integrity

Definitions

  • the present invention relates to a method for
  • a large number of data transmission methods are known from the prior art, including those with synchronous digital hierarchy (SDH) and those based on an asynchronous transfer mode (ATM).
  • SDH synchronous digital hierarchy
  • ATM asynchronous transfer mode
  • a hierarchy level of the European standard comprises four channels of the next lower hierarchy level. Due to the plesiochronous transmission, the nominal transmission rates are not exactly four times the respective lower level, but are slightly higher to accommodate stuff bits to compensate for clock fluctuations.
  • the disadvantage of the PDH method is that base channels are only directly accessible at the lowest hierarchical level. A complete step-by-step demultiplexing is required to extract a 64 kbit / s base channel from a higher hierarchical level.
  • the basic format of the SDH transmission is the STM-1 frame (Synchronous Transport Module Level 1, see Fig. 3). It consists of a header, the section additional information 52 (section overhead, SOH) and a user data component, the
  • an STM-1 frame is transmitted for 125 ⁇ s.
  • Three further hierarchy levels are defined, with the transmission capacity quadrupling from hierarchy level to hierarchy level.
  • the 125 ⁇ s-filling frames on the various hierarchy levels are referred to as STM-N frames, where N specifies the number of m 125 ⁇ s transmitted STM-1 frames and can have the values 1, 4, 16 or 64.
  • An STM-1 frame consists of 2430 bytes, which are divided into nine lines to 270 bytes.
  • the first nine bytes of each line carry the additional information (overhead) which is intended for the operation and management of the system (FIG. 3).
  • the section additional information 52 (section overhead, SOH) is in turn divided into the regenerator section overhead RSOH m the lines 1 to 3, a Pomter field P m the fourth line and the multiplexer section overhead MSOH in lines 5 to 9.
  • the RSOH is used for monitoring used between two regenerators, and the MSOH is used to monitor and manage the route between two multiplexers.
  • the Pomterfeld points to the beginning of the payload 54 within the STM-1 frame. This allows multiplexing without overflow if a channel to be transmitted does not fit exactly into the user data area 54. 3
  • ATM Asynchronous Transfer Mode
  • the header includes, among other things, a channel identification (VPI), a path identification (VCI) and a PT field (Payload Type), which specifies the type of user data.
  • VPI channel identification
  • VCI path identification
  • Payload Type PT field
  • the ATM Forum has specified specifications for direct cell transmission at 155 Mbit / s over shielded twisted pair cables (Shielded Twisted Pair) over a length of max. 100 and the TAXI interface. Further recommendations for direct cell transmission with lower data rates between 25 Mbit / s and 51 Mbit / s are under discussion.
  • a known class 4 virtual container (VC-4, FIG. 4) was used. Similar to the STM-N frame, the VC-4 m is divided into nine lines as well as a header and a user data area. The header of the VC-4 is called path overhead (POH) and includes the first byte of each of the nine lines.
  • POH path overhead
  • the VC-4 user data area comprises the remaining 260 bytes of the nine lines and is referred to as the C-4 container.
  • a C-4 container is filled line by line with ATM cells.
  • the byte interleaved mode (56) was defined for STM-4 frames.
  • Four C-4 containers are byte by byte with ATM cells 4 filled up.
  • Section 56 shows the end of one and the beginning of the next ATM cell.
  • the header bytes are labeled hl, h2 to h5 and the bytes of the user data (payload) are labeled pl, p2 to p48.
  • each VC-4 still has its own pointer P, this corresponds to a virtually linked data packet chain VC-4-4vc.
  • Vc stands for "virtually concatenated”
  • VC-4-Xvc virtually chained data packet chains
  • FIG. 1 shows an encoder according to the invention at the starting point (origination point) of a data transmission link
  • Fig. 6 Supplement to the scheme according to Fig. 5 for the additional recognition of a virtually linked data packet chain VC-4-Xvc an STM-N frame.
  • the 1 shows an encoder 2 according to the invention at the starting point of a data transmission link.
  • the encoder 2 receives user data 4 via an input line and outputs it in the form of data packets via an output line 14.
  • the user data are preferably delivered in the form of ATM cells.
  • the data on the output line 14 are preferably divided in accordance with the synchronous digital hierarchy STM-N frames, for example STM-4 or STM-16 frames.
  • the user data user data packets (C-4) are divided, the data of a user data packet being transmitted together via output line 14. Therefore, the choice of the type of user data packets depends on the data organization on the
  • the path overhead information (Path Overhead, POH) is added to the processing stages 11 of the C-4 containers. How 6
  • the additional path information comprises nine bytes, each of the nine lines of the C-4 container being preceded by one byte of the additional path information.
  • the H4 byte is preferably used for the present invention.
  • either the cyclic H4 byte counter 8 or another source for the H4 bytes can be selected.
  • Adding the additional path information to a C-4 container creates a class 4 virtual container, a VC-4.
  • section overhead information is added to the devices 12 in order to obtain complete STM-N frames which are then transmitted via the output line 14 in accordance with the synchronous digital hierarchy.
  • the STM-N frames are expected to arrive at the end point in the same order as they were sent at the start point. Since the transmission of an STM-N frame takes 125 ⁇ s m, the maximum permissible runtime differences of individual VC-4s of a virtually chained VC-4-Xvc are ⁇ 62.5 ⁇ s, since the pointer value of a VC-4 is only within an STM Frame is clear, and thus runtime differences of the individual VC-4 can only be compensated within the STM frame. With the help of the cyclic H4-byte counter, each STM-N frame and thus the subunits VC-4 and C-4 contained in it are provided with a bit sequence.
  • This bit sequence is written, for example, in the H4 byte of the path overhead information (Path Overhead, POH) of the virtually concatenated VC-4 containers to a VC-4-Xvc.
  • the bit sequence is preferably increased by one from STM-N frames to STM-N frames, so that the H4 byte is paid out cyclically in ascending order. Since a byte has a value range from 0 to 255, the maximum runtime difference is expanded from ⁇ 62.5 ⁇ s to ⁇ 16ms. 7
  • each VC-4 are provided container with a new bit sequence in the H4 byte.
  • the encoder enters the same H4 value for virtually concatenated VC-4-Xvc (same start time for all VC-4).
  • the decoder 20 operates essentially in mirror image of the encoder 2.
  • the decoder 20 receives data packets via an input line 21, a part of which is preferably viewed or transmitted as being virtually linked to a VC-4-Xvc.
  • the virtual concatenation indication can be contained in another area of the POH of each virtually concatenated VC-4 or, as was previously the case, can only be determined on the decoder by the transmission system's operating system for the corresponding VC-4s, with no automatic recognition on the decoder.
  • the bit sequence in the H4 byte itself that for temporal
  • VC-4-Xvc a data packet chain VC-4-Xvc.
  • the decoder 20 receives a large number of data packet chains (VC-4-Xvc) and possibly a large number of non-chained single data packets via the receive line 21.
  • the input data are preferably delivered in the form of STM-N frames. After decoding, the input data are output via a multiplicity of output data lines 32, for example as ATM cell streams.
  • the additional section information 52 (SOH) is filtered out of the STM-N frame.
  • the Pomter values P the
  • Section additional information 52 is forwarded to demapper 27 via data lines 22. After filtering out 8th
  • the section additional information from the STM-N frames remains VC-4 containers which are passed on to the path additional information filler 25.
  • the path addition information filter 25 remove the
  • Additional path information from the VC-4 containers, leaving C-4 containers.
  • the additional path information filter 25 pass on the H4 bytes to the superframe evaluation 24.
  • the superframe evaluation 24 controls the demapper 27 with respect to the bit sequences m of the H4 bytes.
  • the demapper 27 has a controller 26 and a memory controller 28.
  • the demapper 27 has at least N buffers 30, where N is the number of STM-1 frames m the STM-N signal. N is a natural number and preferably has the value 4 or 16.
  • Containers in the demapper 27 are referred to the section 56 m Fig. 4.
  • the intermediate storage 30 in the demapper 27 are designed so large or, alternatively, so numerous that the
  • Decoder 20 can also fulfill its task according to the invention, namely to compensate for the running time difference of the individual virtually linked C-4 containers.
  • the individual C-4 container contents are also buffered and sorted according to the value of their H4 byte. Both positive and negative bit stuffing processes are taken into account and sorted according to the process.
  • the limit for the permissible transit time difference of individual C-4 containers in a VC-4-Xvc data packet chain can be extended to a maximum of ⁇ 16ms in accordance with the maximum permissible value range in the H4 byte.
  • the sorting process in the demapper according to the H4 bytes is controlled by the superframe evaluation 24. 9
  • the frame recognition of the H4 bytes is error-tolerant in the demapper 20.
  • An error-tolerant evaluation can be understood to mean that only a plurality of incorrectly received H4 bytes from successively following VC-4s unite at one or more positions in the STM-N frame
  • Trigger chaining alarm 62 the VC-4 in the same position within consecutive STM-N frames are always referred to as VC-4 following one another in time. H4 bytes are incorrect, for example, if individual ones follow one another in time
  • H4 for example 32 ms ( ⁇ 16ms) for H4 coding by means of 8 bits, have the same H4 byte value.
  • the expected or error-free received H4 byte H4 value of a VC-4 is considered, which is incremented by 1 to the H4 value of the previous VC-4.
  • the H4 value of the previous VC-4s can itself be an error-free received H4 byte or an incorrectly received but corrected H4 byte.
  • an H4 byte is regarded as an incorrectly received H4 byte that does not meet the above condition.
  • H4 byte is corrected by inserting the cyclically expected H4 value that is incremented to the processor value (corrected or received without errors) by 1.
  • Correction mode can be operated. If, during this variant of the resynchronization process, the state of N consecutive errors is reached for a further H4-byte sequence, the resynchronization process must be started again from the beginning, this new faulty VC-4 position or the corresponding H4- byte sequence is taken out of the correction mode.
  • a shorter time interval of, for example, 1 ms can also be used.
  • the then redundant information is preferably used for error detection and error correction using conventional methods. The statements on fault tolerance and alarming then apply accordingly.
  • the number N of faulty H4 bytes m FIG. 5 which trigger a chaining alarm is preferably between 2 and 10, in particular 5.
  • M is preferably between 2 and 4, in particular at 3.
  • the chaining alarm can either be triggered by the superframe evaluation 24 or, alternatively, by the demapper 27. For data packets in between with faulty H4 bytes, for example, the cyclically expected value of the H4 byte is assumed.
  • the H4 byte contains a bit sequence running cyclically from data packet chain to data packet chain
  • this bit sequence can of course be written in any other byte of the additional path information (POH), for example m the Z5 byte in the additional path information (POH).
  • the value range of a byte does not have to be cycled through either. Rather, any sequence of byte values can be used as long as the same sequence is only used by the encoder and decoder. Furthermore, the entire value range from 0 to 255 does not have to be used. If the entire value range is not exhausted, the redundancy can be used to correct transmission errors. 12
  • either a shorter or longer bit sequence of, for example, four bits or more bytes can be used instead of a byte, correctable runtime errors either becoming smaller or larger than the above-mentioned ⁇ 16 ms. If the maximum compensable delay time difference, which results from the product of the range of values of the bit sequence with the transmission time of a data packet chain, is not used, the redundant information is preferably used to detect and correct transmission errors.
  • IP Internet Protocol
  • PCM pulse code modulated

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

L'invention concerne un procédé permettant de transmettre des données utiles, d'une source de données à un collecteur de données, la transmission s'effectuant en paquets de données (54; VC-4) par l'intermédiaire d'une voie de transmission (14, 21). Ce procédé comprend les étapes suivantes: classement des données utiles en paquets de données utiles (C-4) ; insertion d'une zone de données de commande (POH) dans chaque paquet de données utiles (C-4), un paquet de données utiles (C-4) et la zone de données de commande (POH) correspondante constituant un paquet de données (54; VC-4); transmission des paquets de données (54; VC-4) par l'intermédiaire de la voie de transmission ; sortie et évaluation de la zone de données de commande (POH) de chaque paquet de données (54; VC-4), et sortie (27) des paquets de données (C-4) sous forme de données utiles. La zone de données de commande (POH) comprend une séquence de bits (H4) correspondant à une numérotation des paquets de données (54; VC-4). Les paquets de données (54; VC-4) reçus sont triés selon la séquence de bits (H4), avant que les paquets de données utiles (C-4) ne soient sortis.
PCT/DE1999/000575 1998-03-25 1999-03-04 Procede de transmission de donnees, codeur et decodeur WO1999049604A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA002325448A CA2325448A1 (fr) 1998-03-25 1999-03-04 Procede de transmission de donnees, codeur et decodeur
EP99913107A EP1064746A1 (fr) 1998-03-25 1999-03-04 Procede de transmission de donnees, codeur et decodeur

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE1998113168 DE19813168A1 (de) 1998-03-25 1998-03-25 Verfahren zur Datenübertragung, Codierer sowie Decodierer
DE19813168.2 1998-03-25

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Publication Number Publication Date
WO1999049604A1 true WO1999049604A1 (fr) 1999-09-30

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EP (1) EP1064746A1 (fr)
CA (1) CA2325448A1 (fr)
DE (1) DE19813168A1 (fr)
WO (1) WO1999049604A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100414899C (zh) * 2002-08-05 2008-08-27 华为技术有限公司 大传输延时的虚级联虚容器帧的处理方法
US9989861B2 (en) 2004-04-14 2018-06-05 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7903662B2 (en) 2005-07-28 2011-03-08 Cisco Technology, Inc. Virtual concatenation sequence mismatch defect detection

Citations (2)

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Publication number Priority date Publication date Assignee Title
US5018132A (en) * 1989-05-12 1991-05-21 Alcatel Na Network Systems Corp. SONET 4h byte receiver and filter
EP0453876A2 (fr) * 1990-04-21 1991-10-30 Alcatel SEL Aktiengesellschaft Méthode de synchronisation pour systèmes de signaux numériques d'une hiérarchie synchrone et circuit et procédé pour la reconaissance de différentes structures de données

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US5018132A (en) * 1989-05-12 1991-05-21 Alcatel Na Network Systems Corp. SONET 4h byte receiver and filter
EP0453876A2 (fr) * 1990-04-21 1991-10-30 Alcatel SEL Aktiengesellschaft Méthode de synchronisation pour systèmes de signaux numériques d'une hiérarchie synchrone et circuit et procédé pour la reconaissance de différentes structures de données

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Title
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SEOK CHANG KIM ET AL: "PARALLEL SHIFT REGISTER GENERATORS: THEORY AND APPLICATIONS TO PARALLEL SCRAMBLING IN MULTIBIT-INTERLEAVED MULTIPLEXING ENVIRONMENTS", IEEE TRANSACTIONS ON COMMUNICATIONS, vol. 43, no. 2/04, PART 03, 1 February 1995 (1995-02-01), pages 1844 - 1853, XP000505657, ISSN: 0090-6778 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100414899C (zh) * 2002-08-05 2008-08-27 华为技术有限公司 大传输延时的虚级联虚容器帧的处理方法
US9989861B2 (en) 2004-04-14 2018-06-05 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method

Also Published As

Publication number Publication date
DE19813168A1 (de) 1999-09-30
CA2325448A1 (fr) 1999-09-30
EP1064746A1 (fr) 2001-01-03

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