WO1999043032A3 - Halbleiterbauelement mit strukturiertem leadframe und verfahren zu dessen herstellung - Google Patents

Halbleiterbauelement mit strukturiertem leadframe und verfahren zu dessen herstellung Download PDF

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Publication number
WO1999043032A3
WO1999043032A3 PCT/DE1999/000464 DE9900464W WO9943032A3 WO 1999043032 A3 WO1999043032 A3 WO 1999043032A3 DE 9900464 W DE9900464 W DE 9900464W WO 9943032 A3 WO9943032 A3 WO 9943032A3
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WO
WIPO (PCT)
Prior art keywords
leadframe
semiconductor component
producing
same
structured
Prior art date
Application number
PCT/DE1999/000464
Other languages
English (en)
French (fr)
Other versions
WO1999043032A2 (de
Inventor
Alexandra Atzesdorfer
Achim Neu
Thies Janczek
Original Assignee
Siemens Ag
Alexandra Atzesdorfer
Achim Neu
Thies Janczek
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Alexandra Atzesdorfer, Achim Neu, Thies Janczek filed Critical Siemens Ag
Publication of WO1999043032A2 publication Critical patent/WO1999043032A2/de
Publication of WO1999043032A3 publication Critical patent/WO1999043032A3/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

Bei einem Halbleiterbauelement mit einem Leadframe (2) und einem mit diesem verbundenen Chip (7), der von einer isolierenden Pressmasse (9) eingekapselt ist, weist der Leadframe (2) zumindest in der Nähe einer Seitenwand der Pressmasse (9), aus der Anschlussbeinchen (4, 5) des Leadframes (2) austreten, eine das Eindringen von Pressmasse (9) ermöglichende Strukturierung, insbesondere in der Form von durchgehenden Löchern (10, 11) auf, wodurch eine Verankerung der Pressmasse (9) am Leadframe (2) geschaffen wird.
PCT/DE1999/000464 1998-02-20 1999-02-19 Halbleiterbauelement mit strukturiertem leadframe und verfahren zu dessen herstellung WO1999043032A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19807254.6 1998-02-20
DE19807254 1998-02-20

Publications (2)

Publication Number Publication Date
WO1999043032A2 WO1999043032A2 (de) 1999-08-26
WO1999043032A3 true WO1999043032A3 (de) 1999-11-25

Family

ID=7858463

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/000464 WO1999043032A2 (de) 1998-02-20 1999-02-19 Halbleiterbauelement mit strukturiertem leadframe und verfahren zu dessen herstellung

Country Status (1)

Country Link
WO (1) WO1999043032A2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9640467B2 (en) 2009-08-05 2017-05-02 Continental Teves Ag & Co. Ohg Sensor arrangement and chip comprising additional fixing pins

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62183548A (ja) * 1986-02-07 1987-08-11 Nec Corp 半導体装置
JPS63177543A (ja) * 1987-01-19 1988-07-21 Nec Corp 半導体装置用リ−ドフレ−ム
US4862246A (en) * 1984-09-26 1989-08-29 Hitachi, Ltd. Semiconductor device lead frame with etched through holes
JPH01278754A (ja) * 1988-05-02 1989-11-09 Matsushita Electron Corp 半導体装置用リードフレーム
JPH0214555A (ja) * 1989-05-19 1990-01-18 Hitachi Ltd 樹脂封止型半導体装置
JPH02285662A (ja) * 1989-04-27 1990-11-22 Hitachi Ltd 樹脂封止半導体及びその製造方法
JPH04225553A (ja) * 1990-12-27 1992-08-14 Mitsubishi Electric Corp 電子部品およびその製造方法
JPH05160183A (ja) * 1991-12-10 1993-06-25 Fujitsu Ltd 半導体装置の製造方法
US5459103A (en) * 1994-04-18 1995-10-17 Texas Instruments Incorporated Method of forming lead frame with strengthened encapsulation adhesion
JPH07326699A (ja) * 1994-05-31 1995-12-12 Daido Steel Co Ltd Ｉｃリードフレーム材の製造方法
JPH0846125A (ja) * 1994-07-29 1996-02-16 Nippon Steel Corp リードフレーム
US5622896A (en) * 1994-10-18 1997-04-22 U.S. Philips Corporation Method of manufacturing a thin silicon-oxide layer
JPH09148509A (ja) * 1995-11-22 1997-06-06 Goto Seisakusho:Kk 半導体装置用リードフレーム及びその表面処理方法
EP0867935A2 (de) * 1997-03-25 1998-09-30 Mitsui Chemicals, Inc. Kunststoffpackung, Halbleiteranordnung, und Verfahren zum Herstellen einer Kunststoffpackung
US5817544A (en) * 1996-01-16 1998-10-06 Olin Corporation Enhanced wire-bondable leadframe

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862246A (en) * 1984-09-26 1989-08-29 Hitachi, Ltd. Semiconductor device lead frame with etched through holes
JPS62183548A (ja) * 1986-02-07 1987-08-11 Nec Corp 半導体装置
JPS63177543A (ja) * 1987-01-19 1988-07-21 Nec Corp 半導体装置用リ−ドフレ−ム
JPH01278754A (ja) * 1988-05-02 1989-11-09 Matsushita Electron Corp 半導体装置用リードフレーム
JPH02285662A (ja) * 1989-04-27 1990-11-22 Hitachi Ltd 樹脂封止半導体及びその製造方法
JPH0214555A (ja) * 1989-05-19 1990-01-18 Hitachi Ltd 樹脂封止型半導体装置
JPH04225553A (ja) * 1990-12-27 1992-08-14 Mitsubishi Electric Corp 電子部品およびその製造方法
JPH05160183A (ja) * 1991-12-10 1993-06-25 Fujitsu Ltd 半導体装置の製造方法
US5459103A (en) * 1994-04-18 1995-10-17 Texas Instruments Incorporated Method of forming lead frame with strengthened encapsulation adhesion
JPH07326699A (ja) * 1994-05-31 1995-12-12 Daido Steel Co Ltd Ｉｃリードフレーム材の製造方法
JPH0846125A (ja) * 1994-07-29 1996-02-16 Nippon Steel Corp リードフレーム
US5622896A (en) * 1994-10-18 1997-04-22 U.S. Philips Corporation Method of manufacturing a thin silicon-oxide layer
JPH09148509A (ja) * 1995-11-22 1997-06-06 Goto Seisakusho:Kk 半導体装置用リードフレーム及びその表面処理方法
US5817544A (en) * 1996-01-16 1998-10-06 Olin Corporation Enhanced wire-bondable leadframe
EP0867935A2 (de) * 1997-03-25 1998-09-30 Mitsui Chemicals, Inc. Kunststoffpackung, Halbleiteranordnung, und Verfahren zum Herstellen einer Kunststoffpackung

Non-Patent Citations (10)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 012, no. 026 (E - 577) 26 January 1988 (1988-01-26) *
PATENT ABSTRACTS OF JAPAN vol. 012, no. 449 (E - 686) 25 November 1988 (1988-11-25) *
PATENT ABSTRACTS OF JAPAN vol. 014, no. 055 (E - 0882) 31 January 1990 (1990-01-31) *
PATENT ABSTRACTS OF JAPAN vol. 014, no. 156 (E - 0908) 26 March 1990 (1990-03-26) *
PATENT ABSTRACTS OF JAPAN vol. 015, no. 058 (E - 1032) 12 February 1991 (1991-02-12) *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 574 (E - 1298) 14 December 1992 (1992-12-14) *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 556 (E - 1444) 6 October 1993 (1993-10-06) *
PATENT ABSTRACTS OF JAPAN vol. 096, no. 004 30 April 1996 (1996-04-30) *
PATENT ABSTRACTS OF JAPAN vol. 096, no. 006 28 June 1996 (1996-06-28) *
PATENT ABSTRACTS OF JAPAN vol. 097, no. 010 31 October 1997 (1997-10-31) *

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