Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/202—FETs having static field-induced regions, e.g. static-induction transistors [SIT] or permeable base transistors [PBT]

Definitions

• the vertical static induction transistor exhibits higher breakdown voltage due to reduced field crowding and surface breakdown may be controlled by the use of guard rings or field plates, by way of example.
• a portion of the semiconductor material of the static induction transistor is deposited upon a substrate by epitaxial growth techniques such as vapor phase epitaxy during which process intentional impurity atoms of a dopant are added, as desired, to produce layers with predetermined dopant levels and conductivities.
• An improved static induction transistor which includes a semiconductor body having a substrate with a plurality of semiconductor layers thereon and including at least one source for supplying majority carriers and at least one drain, displaced from said source, for collecting said majority carriers. At least two gates are provided and are positioned relative to said semiconductor body for controlling flow of said majority carriers from said source.
• the semiconductor body has a first region, a channel region, contiguous to said source and gates in which said gates control flow of said majority carriers from said source to said drain.
• the semiconductor body also has a second region, a drift region, which extends from said first region to said drain.
• the first and second regions have predetermined impurity atoms of a dopant added, with said first region having a higher average doping concentration than said second region.
• BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates one type of known static induction transistor.
• Fig. 2 shows typical characteristic curves associated with a static induction transistor.
• Fig. 3 illustrates the doping concentration for the static induction transistor of Fig. 1.
• Fig. 4 shows characteristic curves for the static induction transistor of Fig. 3.
• Fig. 5 is a curve showing the drain-toil, source current as a function of gate-to-source voltage for a given load condition for the static induction transistor of Fig. 3.
• Fig.6 illustrates a lighter doping concentration for the static induction transistor of Fig. 1.
• Fig. 7 shows characteristic curves for the static induction transistor of Fig. 6.
• Fig. 8 is a curve showing the drain-to ⁇ source current as a function of gate-to-source voltage for a given load condition for the static induction transistor of Fig. 6.
• Fig.9 shows a doping profile for the static induction transistor of Fig. 3.
• Fig.10 shows a doping profile for the static induction transistor of Fig. 6.
• Fig. 11 shows a doping profile in accordance with the present invention.
• Fig.l represents a portion of a conventional static induction transistor in the form of a Schottky barrier recessed gate type static induction transistor 10, such as described in the aforementioned application S/N 08/708,447.
• the transistor includes a semiconductor body 12 of a selected conductivity type comprised of a plurality of layers including a substrate member 14 , which may act as the drain region for collecting majority carriers provided by source regions 16.
• the semiconductor body is of polytype 4H silicon carbide which offers improved performance over conventional materials such as silicon. This includes higher breakdown voltage, lower thermal impedance due to better thermal conductivity, higher frequency performance, higher maximum current higher operating temperature and improved reliability, particularly in harsh environments.
• silicon carbide is the preferred semiconductor, it is to be understood that the present invention is applicable to static induction transistors made of other materials such as silicon, gallium arsenide, gallium nitride and indium phosphide and other polytypes of silicon carbide, by way of example.
• the silicon carbide substrate member 14, cut from a grown silicon carbide boule, may have slight imperfections in its surface which could lead to breakdown during transistor operation. Accordingly, a silicon carbide buffer layer 17 may be deposited to provide a transition from a relatively low electric field in the substrate 14 to a relatively high electric field in the next deposited layer 18.
• This layer 18 includes a plurality of mesas 20 defining recesses 21 therebetween for receiving Schottky barrier gates 22 which extend along the bottom of the mesas, up the sidewalls thereof and onto the top portion of the mesa on either side of the source regions 16.
• the source regions include respective ohmic contacts 26 and the arrangement is covered with a protective oxide layer 28 through which apertures are provided for electrically connecting all of the source contacts 26 to a metallization layer 30. Electrical contact is made to the drain region 14 by means of ohmic contact 32.
• Layer 18 includes a first region 36 between the gates 22 and which extends from the source 16 to the bottom of the gate 22, or slightly below it, as indicated by the dotted line 37.
• This first region is where the gate controls the flow of majority carriers from the source and is termed herein the channel layer or channel region.
• a second region 38 extends from the first region to the drain 14 (to the top of buffer layer 17, if provided) and is the region where the majority carriers drift toward the drain and is termed herein the drift layer or drift region.
• Fig. 2 illustrates some typical characteristic curves associated with the static induction transistor of Fig. 1. Drain-to-source current I DS is plotted on the vertical axis and drain-to-source voltage V DS is plotted on the horizontal axis.
• V GS1 Very basically, at relatively low gate bias V GS1 the channel region depletes to a certain width from each gate leaving a channel through which ohmic current conduction takes place. This is represented by curve 50. As the drain bias increases, the channel becomes depleted and the form of conduction changes, after a thermionic emission mode at points 52, to a space charge limited mode as represented by curves 54.
• the above is a simplification and in reality some of the modes may be present simultaneously.
• a load line 56 is established, as a function of the load, and a quiescent operating point is selected.
• the operating point will move up and down the load line providing a corresponding varying drain-to-source current. It is critical therefore that the transconductance and voltage gain be constant as the input signal varies so as to reduce distortion.
• the voltage gain ⁇ of the device is the change in drain-to-source voltage for a given change in gate-to-source bias, at a given point on the load line.
• the semiconductor layer between the source 16 and buffer layer 17, constituting the channel and drift layers 36 and 38, has a relatively high uniform dopant level of around lxlO 15 cm “3 (atoms per cubic centimeter) , as indicated by the uniform stippling.
• Fig. 4 (as well as Figs. 5, 7, 8, 13 and 14) are a computer generated plot for a silicon carbide device having a mesa height of 1 ⁇ m, a mesa width of 1.5 ⁇ m, a channel layer thickness of 1.5 ⁇ m, a drift layer thickness of 4 ⁇ m and a uniform doping of lxlO 16 cm “3 .
• Gate biases of 2, 0, -2, -4, -6, -8 -10 and -12 are plotted.
• the operating range of the device is expected to traverse the load line as the gate bias changes.
• the gate bias is 2V
• the load line intersects the I-V characteristics at the maximum I DS value or I max .
• the gate bias is -12V
• there is very little drain-to- source current for V DS 200V, which would be the blocking voltage, or V max , for this particular gate bias.
• the blocking voltage is the highest drain-to-source voltage at which the device blocks drain-to-source current.
• V GS 2V and the largest reliable blocking voltage.
• I max and blocking voltage depend on the particular load line. Additionally, blocking voltage cannot be made arbitrarily large since large magnitudes of gate-to-source voltage soon approach the intrinsic breakdown field in the semiconductor in the vicinity of the gate and source contacts.
• Figure 5 plots the drain-to-source current as a function of V GS along the load line.
• a straight line is desirable, showing linearity in the device when it is used as an amplifier.
• the slope of the line that is,
• a potential solution is to lower the uniform doping to a value of, for example, 1 x 10 15 cm "3 , as depicted by the structure of Fig. 6 wherein the reduced stippling density corresponds to the reduced doping level.
• Plots for I DS vs. V DS , and I DS vs. V GS , for this lower doping value are seen in figures 7 and 8 respectively.
• the I DS vs. V GS curve of Fig. 8 is more linear than that of Fig. 5 for the higher dopant concentration case, and a lower V GS (approximately -3V vs. -12V) is required for a blocking voltage, or V max , of 200V.
• V max blocking voltage
• the value of I max has severely dropped. This would lead to less power output since power output, P, is (I max x V max )/8.
• a static induction transistor which has relatively high maximum drain-to-source current and high blocking voltage for maximum power, and has high, as well as relatively uniform, transconductance and voltage gain throughout the input signal range.
• Fig. 9 illustrates the doping concentration profile for the device of Fig.3 and shows a uniform doping of lxlO 16 cm "3 in both the channel and drift regions.
• Fig. 10 illustrates a doping concentration profile for the device of Fig. 6 and shows a uniform doping of lxlO 15 cm "3 .
• Fig. 11 illustrates a doping concentration profile in accordance with the present invention.
• Fig. 16 illustrates a static induction transistor 110 wherein the position of the source and drain regions have been reversed.
• the structure includes a source formed by substrate 112 and buffer layer 114.
• a plurality of mesas 116 defined in the n type semiconductor body include at the ends thereof respective drain regions 118.
• Gate regions 120 formed by ion implantation or other process are of p type conductivity and are defined in the semiconductor body between mesas 116. Suitable electrical connection is made to the structure by means of drain contacts and metallization 122 and 123, gate contacts 124 and source contact 125.
• Channel regions 130, between gates 120 are of a higher doping concentration than drift regions 132, providing a static induction transistor with superior performance, as previously described.

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• 1997
  • 1997-12-19 US US08/995,080 patent/US5945701A/en not_active Expired - Lifetime
• 1998
  • 1998-12-16 WO PCT/US1998/026755 patent/WO1999033118A1/en not_active Ceased
  • 1998-12-16 JP JP2000525932A patent/JP2001527296A/ja active Pending
  • 1998-12-16 EP EP98963988A patent/EP1040524A1/en not_active Ceased

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