WO1999012199A1 - Circuit integre encapsule - Google Patents

Circuit integre encapsule Download PDF

Info

Publication number
WO1999012199A1
WO1999012199A1 PCT/DE1998/002207 DE9802207W WO9912199A1 WO 1999012199 A1 WO1999012199 A1 WO 1999012199A1 DE 9802207 W DE9802207 W DE 9802207W WO 9912199 A1 WO9912199 A1 WO 9912199A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
packaged integrated
cover
chip
circuit according
Prior art date
Application number
PCT/DE1998/002207
Other languages
German (de)
English (en)
Inventor
Detlef Houdeau
Peter Stampka
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1999012199A1 publication Critical patent/WO1999012199A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a packaged integrated circuit with a semiconductor chip, in which at least the surface having the electrical circuit is provided with a non-conductive cover.
  • Such a packaged integrated circuit is known from WO 95/19645.
  • the cover there is typically formed with glass, aluminum oxide ceramic, byrillium oxide ceramic or sapphire. Such a cover is intended to protect the integrated circuit from optical examination or mechanical damage but also from a chemical attack.
  • the problem is solved in that the side of the cover facing a chip surface is provided with etching structures in order to achieve better adhesion to a connecting substance connecting the chip and the cover.
  • pockets are formed into which an adhesive advantageously used as a connecting material between the chip and the cover can penetrate and, due to the positive fit thus achieved, to a particularly good connection leads between chip and cover.
  • an adhesive advantageously used as a connecting material between the chip and the cover can penetrate and, due to the positive fit thus achieved, to a particularly good connection leads between chip and cover.
  • One advantage of these adhesive bags is the increased percentage of surface area. Furthermore, an increased shear strength of the adhesive layer is set.
  • tungsten carbide e.g. WC-6C0
  • WC-6C0 tungsten carbide
  • Wolfang carbide which is less sensitive to brittle fracture, is extremely stable against chemical and thermal influences. The stiffness mentioned above means that a sandwich structure in which a semiconductor chip is arranged between two tungsten carbide covers withstands the mechanical loads on the chip, for example in chip card applications.
  • eutectically bondable that is to say weldable
  • material can be used as the connecting material. This material can be welded to a previously metallized chip side.
  • the tungsten carbide contains borosilicate glass as a filler in order to enable anodic bonding of the cover. Since the cover is made in one piece and is only then connected to the semiconductor chip by means of the connecting material, recesses or openings can be provided in order to allow contacting of the chip, as is taught, for example, in WO 95/19645 . In an advantageous manner, however, the chip connections are led out to the side, so that no processing of the cover is necessary.
  • the cover can already be applied to the wafer and serve as a carrier for the latter.
  • the sawing of the bare wafer and the associated sawing edge problems, which lead to crack sensitivity, are eliminated.
  • the microcracks that frequently occur when the individual chips are removed from the wafer composite can also be prevented.
  • a semiconductor chip is provided on both main surfaces with a tungsten carbide cover which is etched according to the invention by means of a connecting material, a chip safe is formed in which the semiconductor chip and the integrated circuits implemented thereon are optimally protected, so that they can be used particularly advantageously in chip card applications which are particularly critical to security .

Abstract

L'invention concerne un circuit intégré encapsulé comportant une puce semi-conductrice, dans lequel au moins la surface présentant le circuit électrique est pourvue d'un revêtement non conducteur. La face du revêtement tournée vers une surface de puce est munie de motifs gravés, en vue d'assurer une meilleure adhérence avec une substance de liaison reliant la puce et le revêtement. Ce dernier est avantageusement formé de carbure de tungstène (par exemple WC-6Co).
PCT/DE1998/002207 1997-09-03 1998-07-31 Circuit integre encapsule WO1999012199A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE1997138549 DE19738549C1 (de) 1997-09-03 1997-09-03 Verpackte integrierte Schaltung
DE19738549.4 1997-09-03

Publications (1)

Publication Number Publication Date
WO1999012199A1 true WO1999012199A1 (fr) 1999-03-11

Family

ID=7841093

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1998/002207 WO1999012199A1 (fr) 1997-09-03 1998-07-31 Circuit integre encapsule

Country Status (2)

Country Link
DE (1) DE19738549C1 (fr)
WO (1) WO1999012199A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01309333A (ja) * 1988-06-07 1989-12-13 Nec Corp 樹脂封止型半導体装置
JPH0669381A (ja) * 1992-08-20 1994-03-11 Nec Corp 半導体集積回路装置
WO1995019645A1 (fr) * 1994-01-17 1995-07-20 Shellcase Ltd. Procedes et appareil de production de dispositifs a circuits integres
JPH0870067A (ja) * 1994-08-26 1996-03-12 Nippon Steel Corp 半導体装置
US5578867A (en) * 1994-03-11 1996-11-26 Ramtron International Corporation Passivation method and structure using hard ceramic materials or the like
DE19649652A1 (de) * 1996-11-29 1998-06-04 Siemens Ag Halbleiterchip und Wafer mit Schutzschicht, insbesondere aus Keramik

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01309333A (ja) * 1988-06-07 1989-12-13 Nec Corp 樹脂封止型半導体装置
JPH0669381A (ja) * 1992-08-20 1994-03-11 Nec Corp 半導体集積回路装置
WO1995019645A1 (fr) * 1994-01-17 1995-07-20 Shellcase Ltd. Procedes et appareil de production de dispositifs a circuits integres
US5578867A (en) * 1994-03-11 1996-11-26 Ramtron International Corporation Passivation method and structure using hard ceramic materials or the like
JPH0870067A (ja) * 1994-08-26 1996-03-12 Nippon Steel Corp 半導体装置
DE19649652A1 (de) * 1996-11-29 1998-06-04 Siemens Ag Halbleiterchip und Wafer mit Schutzschicht, insbesondere aus Keramik

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 014, no. 108 (E - 0896) 27 February 1990 (1990-02-27) *
PATENT ABSTRACTS OF JAPAN vol. 018, no. 311 (E - 1561) 14 June 1994 (1994-06-14) *
PATENT ABSTRACTS OF JAPAN vol. 096, no. 007 31 July 1996 (1996-07-31) *

Also Published As

Publication number Publication date
DE19738549C1 (de) 1998-12-10

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