WO1998043440A1 - Image processing device and still image pickup device, and method for processing image - Google Patents
Image processing device and still image pickup device, and method for processing image Download PDFInfo
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- WO1998043440A1 WO1998043440A1 PCT/JP1998/001214 JP9801214W WO9843440A1 WO 1998043440 A1 WO1998043440 A1 WO 1998043440A1 JP 9801214 W JP9801214 W JP 9801214W WO 9843440 A1 WO9843440 A1 WO 9843440A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/46—Colour picture communication systems
- H04N1/64—Systems for the transmission or the storage of the colour picture signal; Details therefor, e.g. coding or decoding means therefor
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/46—Colour picture communication systems
- H04N1/64—Systems for the transmission or the storage of the colour picture signal; Details therefor, e.g. coding or decoding means therefor
- H04N1/648—Transmitting or storing the primary (additive or subtractive) colour signals; Compression thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
- H04N19/98—Adaptive-dynamic-range coding [ADRC]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
- H04N5/77—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N11/00—Colour television systems
- H04N11/04—Colour television systems using pulse code modulation
- H04N11/042—Codec means
- H04N11/044—Codec means involving transform coding
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/78—Television signal recording using magnetic recording
- H04N5/781—Television signal recording using magnetic recording on disks or drums
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/84—Television signal recording using optical recording
- H04N5/85—Television signal recording using optical recording on discs or drums
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
- H04N9/804—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components
- H04N9/8042—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components involving data reduction
- H04N9/8047—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components involving data reduction using transform coding
Definitions
- the present invention relates to an image processing apparatus, a still image capturing apparatus, and an image processing method for encoding, compressing, and storing in a memory an output signal of a predetermined number of pixels, which is output by mixing a plurality of color components.
- a still image pickup device is provided to obtain three color image signals.
- pixel interpolation processing is performed using signals of adjacent pixels in order to obtain three color image signals for each pixel.
- pixel interpolation processing it is easier to process data as a digital signal, but if the image signal is digitized as it is, the amount of information will be enormous.
- the compression capacity and the storage capacity of the encoding memory for recording image signals and the signal transmission time are reduced.
- an encoding circuit is provided for each color. The signal compression is performed by the encoding circuit.
- FIG. 18 is a diagram showing a method of extracting a color signal of the still image pickup device disclosed in Japanese Patent Application Laid-Open No. 4-170886, in which 20 is a stripe of three colors.
- An image sensor with a color filter on the surface 21 a extracted only the R component in the output signal of the image sensor 20, 21 b extracted only the G component in the output signal of the image sensor 20
- Reference numeral 21c denotes a signal obtained by extracting only the B component from the output signal of the image sensor 20.
- this conventional still image pickup device takes out the output signal of the image pickup device 20 for each of the R, G, and B color components, converts them into digital signals, and then converts the signals into one system.
- the compression circuit sequentially compresses the signal for each color component and records it for each color in an encoding memory such as a floppy disk or IC card.
- the conventional still image pickup device is configured as described above, it is necessary to read the image signal directly from the image pickup device for each color, and a dedicated image pickup device capable of reading each color individually and dedicated hardware therefor. Had to be provided.
- the encoding circuit requires only one system and can be simplified, there is a problem that a large memory capacity is required because the encoding memory must store all the color signal components for one frame. Was.
- a still image capturing device when configured using an image processing device, it takes a certain amount of time to encode and decode the image signal, so that it takes some time to display the captured image. There was a problem that would be hung.
- the present invention has been made to solve the above problems, and provides a still image pickup apparatus that can read color image signals for each color with a normal image pickup device without using a special image pickup device.
- the purpose is to:
- Another object of the present invention is to provide an image processing apparatus and an image processing method that can be realized by using a single-system encoding circuit and a small-capacity encoding memory.
- Still another object of the present invention is to obtain a still image pickup device capable of high-speed continuous shooting.
- Still another object of the present invention is to obtain a still image pickup device capable of obtaining a high-definition reproduced image.
- Still another object of the present invention is to provide a still image pickup device capable of displaying an image pickup screen at high speed. Disclosure of the invention
- An image processing apparatus includes: a pixel rearranging unit configured to rearrange an image signal of a predetermined number of pixels in which a plurality of color components are mixed into a set of unit blocks composed of image signal components of the same color; A fixed-length encoding unit that performs fixed-length encoding on the image signal rearranged by the rearranging unit for each unit block; and an image signal that is fixed-length encoded by the fixed-length encoding unit. And an encoding memory for storing the code.
- an image signal in which a plurality of color components in a block are mixed is arranged only in a small-capacity line buffer memory that can be combined into a unit block for each single color component existing in a close position.
- coding can be performed using only color image signal data for each color, and furthermore, there is an effect that it can be realized using a single block coding circuit and a small capacity coding memory.
- a large amount of image data can be stored in the encoding memory without increasing the capacity of the special encoding memory, which has the effect of enabling high-speed continuous shooting.
- the fixed-length encoding means performs fixed-length encoding at a different compression ratio for each color component.
- An image processing apparatus is provided with a selector for selecting and outputting a fixed-length encoded image signal and a non-fixed-length encoded image signal at a stage preceding an encoding memory.
- the pixel rearranging means when the unit block is configured as a block of pixels composed of m rows and n columns (m and n are natural numbers), the pixel rearranging means has 2 m lines. It has a number of line buffer memories.
- m is 4.
- m is 2a (a is a natural number), and the pixel rearranging means rearranges the image signals so that the unit block includes a rows and 2 n columns.
- 111 is 2 & (a is a natural number), and the pixel rearranging means rearranges the red image signal and the blue image signal so that the unit block is composed of a rows and 2 n columns.
- the green image signals are rearranged such that the unit blocks are composed of 2a rows and n columns.
- An image processing apparatus comprises: fixed-length decoding means for reading out an image signal stored in an encoding memory and performing fixed-length decoding; and reordering means for sorting the image signal decoded by the fixed-length decoding means.
- Pixel reverse rearrangement means for rearranging in the reverse order to restore the original image signal, and signal processing means for performing signal processing on the original image signal restored by the pixel reverse rearrangement means.
- the image processing device further includes a frame memory for storing the image signal processed by the signal processing means.
- the image processing apparatus further includes display means for displaying an image signal processed by the signal processing means.
- the signal processing unit reads out only a part of the fixed-length-encoded image signal stored in the encoding memory and displays it on the display unit without performing decoding. Things.
- a still image capturing apparatus includes: a single-panel or single-tube imaging unit that captures an image of an object having a plurality of color components and outputs an image signal in which a plurality of color components are mixed; A pixel rearrangement unit that rearranges an image signal of a predetermined number of pixels output from the imaging unit into a set of unit blocks composed of image signal components of the same color; and an image signal rearranged by the pixel rearrangement unit.
- Fixed-length coding means for performing fixed-length coding for each of the unit blocks, and a coding memory for storing an image signal fixed-length coded by the fixed-length coding means.
- a still image capturing apparatus arranges a fixed-length decoding unit that reads an image signal stored in an encoding memory and performs fixed-length decoding, and an image signal decoded by the fixed-length decoding unit.
- a pixel reverse rearrangement means for rearranging in the reverse order of the rearrangement means to restore the image signal in the original order; and a signal for performing signal processing on the image signal in the original order restored by the pixel reverse rearrangement means Processing means.
- the still image capturing apparatus further includes a frame memory for storing the image signal subjected to the signal processing by the signal processing means.
- each processing of fixed-length decoding, reverse pixel reordering, signal processing, and variable-length coding can be realized by software, which makes it possible to implement hardware in terms of versatility, flexibility, and cost. There is an effect that can be more advantageous than processing.
- An image processing method includes a pixel rearranging step of rearranging an image signal of a predetermined number of pixels in which a plurality of color components are mixed into a set of unit blocks composed of image signal components of the same color.
- An image processing method includes: a fixed-length decoding step of performing fixed-length decoding on an image signal fixed-length coded by a fixed-length coding step; And a signal processing step of rearranging the image signal decoded by the fixed-length decoding step in the reverse order of the rearrangement step to restore the output signal in the original order.
- FIG. 1 is a configuration diagram showing a still image capturing apparatus according to Embodiment 1 of the present invention.
- FIG. 2 is a diagram showing a color arrangement of a color filter formed on the front surface of the imaging light incidence surface of the imaging device according to the first embodiment of the present invention.
- FIG. 3 is a configuration diagram showing an internal configuration of the pixel rearrangement circuit according to the first embodiment of the present invention.
- FIG. 4 is a diagram showing a state of a block where the pixel rearranging circuit according to the first embodiment of the present invention rearranges.
- FIG. 5 is a diagram showing a result of rearrangement by the pixel rearrangement circuit according to the first embodiment of the present invention.
- FIG. 6 is a diagram showing addresses when the color image signals in the unit block rearranged by the pixel rearranging circuit according to the first embodiment of the present invention are encoded by a fixed-length encoding circuit. .
- FIG. 7 is a diagram showing a quantization level at which the intensity of the image signal of each pixel is hierarchized by the pixel rearranging circuit according to the first embodiment of the present invention.
- FIG. 8 is a flowchart showing an encoding procedure according to the first embodiment of the present invention.
- FIG. 9 is a flowchart showing an encoding procedure according to the first embodiment of the present invention.
- FIG. 10 is a diagram showing a state in which image data for each unit block encoded by the fixed-length encoding circuit according to Embodiment 1 of the present invention is stored in an encoding memory.
- FIG. 11 is a diagram showing the storage state of each block in FIG. 9 for the entire image of one field.
- FIG. 12 is a diagram showing a memory capacity required for storing data encoded by the fixed-length encoding circuit according to the first embodiment of the present invention in an encoding memory.
- FIG. 13 is a diagram showing a memory capacity necessary for storing one frame of image signal in an encoding memory conforming to the VGA standard according to the first embodiment of the present invention.
- FIG. 14 is a flowchart showing the operation of the fixed-length decoding circuit according to the first embodiment of the present invention.
- FIG. 15 is a diagram showing a result of rearranging color image data in a line buffer of a rearranging circuit of a still image capturing apparatus according to Embodiment 2 of the present invention.
- FIG. 16 is a diagram showing a result of rearranging empty image data in a line buffer of a rearranging circuit of a still image capturing apparatus according to Embodiment 3 of the present invention.
- FIG. 17 is a configuration diagram of a still image capturing apparatus according to Embodiment 4 of the present invention.
- FIG. 18 is a diagram showing a method of extracting a color signal of a conventional still image pickup device.
- FIG. 1 is a configuration diagram showing a still image capturing apparatus according to Embodiment 1 of the present invention.
- reference numeral 1 denotes a CCD or the like which includes color filters of a plurality of colors and outputs pixel signals in a dot-sequential manner.
- 2 is an analog signal processing circuit for amplifying and filtering the output signal of the image sensor 1
- 3 is an analog signal output from the analog signal processing circuit 2.
- the A / D converter that converts the signal to a digital signal
- 4 is the color conversion by rearranging the output signals of the pixels that have the R, G, and B color components output from the A / D converter 3.
- Reference numeral 7 denotes a fixed-length decoding circuit (fixed-length decoding means) for reading encoded data from the encoding memory 6 and performing fixed-length decoding
- 8 denotes a data decoded by the fixed-length decoding circuit 7.
- the pixel rearrangement circuit 4 performs an inverse rearrangement process on the data rearranged by the pixel rearrangement circuit 4 and rearranges the pixel signals in the same order as when the pixel signals are read out in the scanning line direction.
- signal processing circuits signal processing means
- a frame memory for storing the signal corrected by the signal processing circuit 9, 11 is for reading the data stored in the frame memory 10, and JPEG (Joint P hotographic) for secondary storage.
- Code using a variable-length coding method such as the 12 is a display device (display means) such as a CRT that displays the data read from the frame memory 9 as an image
- 13 is a floppy disk, hard disk, flash memory, etc.
- Analog signal processing circuit 2 A / D converter 3, pixel rearranging circuit 4, fixed-length encoding circuit 5, encoding memory 6, fixed-length decoding circuit 7, pixel reverse rearranging circuit 8, signal processing circuit 9,
- the frame memory 10 constitutes the image processing device 14.
- FIG. 2 is a diagram showing a color array of color filters formed on the front surface of the image pickup light incident surface of the image pickup device 1 according to the first embodiment of the present invention, wherein each color of G, R, and B is shown.
- the components are arranged in a mosaic shape, and the minimum unit of the color array pattern is composed of 4 pixels, 2 pixels vertically and 2 pixels horizontally.
- FIG. 3 is a configuration diagram showing an internal configuration of the pixel rearranging circuit 4.
- 41 is a line buffer A (line buffer memory) capable of storing eight lines of image data
- 42 is a line buffer B (similarly capable of storing eight lines of image data).
- the line buffers A41 and B42 constitute a toggle line buffer.
- Reference numeral 43 denotes a line buffer controller for controlling the write and read operations of the line buffers A41 and B42.
- the imaging device 1 captures an image of a subject, and outputs an image signal corresponding to the incident light filtered by the color filter shown in FIG. 2 in a dot-sequential manner in the scanning line direction for each pixel.
- This color image signal is amplified by the analog signal processing circuit 2 and is filtered to remove a noise component.
- it is converted into a digital signal by the A / D converter 3 and input to the pixel rearranging circuit 4.
- FIG. 4 is a diagram showing a state of a block for performing the rearrangement.
- the screen of the image pickup device 1 has eight blocks each of eight pixels in the vertical and horizontal directions as one block.
- the processed image signals for eight pixels in the vertical direction are input to the line buffers A41 and B42 as a group of image signals.
- FIG. 5 is a diagram showing a result of the sorting by the pixel sorting circuit 4.
- the G component is collected and arranged in the upper left address and lower right address of the block, and the B component is in the lower left address and the R component is in the upper right address. Collected and arranged.
- FIG. 6 is a diagram showing addresses when the color image signals in the unit blocks rearranged by the pixel rearranging circuit 4 are encoded by the fixed-length encoding circuit 5.
- Fig. 6 shows a unit block that is a block of image signals of the same color for each of 4 pixels in the vertical and horizontal directions. This indicates that a quantization level described later is added to the address image signal.
- FIG. 7 shows a quantization level at which the pixel rearrangement circuit 4 hierarchizes (quantizes) the intensity of the image signal of each pixel.
- L min is the minimum value in the image signal intensity of the four pixels shown in FIG. 6
- L max is the maximum value in the image signal intensity of the same four pixels
- P 1 is the maximum value L max and the minimum value L min and 1/8 values from the bottom
- P 2 is the 1/8 value from the top
- Q 1 is the average value of pixels with signal strength between L min
- P 1 8 is an average value of pixels having a signal intensity equal to or less than L max and greater than P 2.
- LD is a gradation width index in a unit block, and is equal to Q8-Q1.
- L1 to L7 are the values obtained by dividing the gradation width index LD into eight equal parts, arranged in ascending order. It is.
- LA is the average level of image data in a unit block (Q 1 + Q
- ⁇ i j k represents a quantization level for each pixel.
- FIGS. 8 and 9 are flowcharts showing an encoding procedure according to Embodiment 1 of the present invention. Hereinafter, the encoding procedure will be described with reference to this flowchart.
- the fixed-length encoding circuit 5 reads the image data in the unit block rearranged by the pixel rearranging circuit 4 as shown in (2) of FIG. 5 (step ST1).
- the signal intensities of the read image data of 4 ⁇ 4 pixels are calculated, and P 1, P 2, Q 1, Q 8, LA, LD, L 1 to L are sequentially calculated according to the following equations. Find the value of 7 (Step ST2 to Step ST1 3)
- LA (Q l + Q 8) / 2
- the expression of Ql means to calculate the average value of pixels with signal strength of Lmin or more and PI or less
- the expression of Q8 means to calculate average value of pixels with signal strength of Lmax or less and P2 or more. I do.
- the quantization level ⁇ ijk of this pixel is set to a binary number of 0000 (step ST17).
- m is incremented by 1 (step ST31), and it is determined whether or not m is 4 or less (step ST32). If m is 4 or less, the pixel value of that pixel is compared again with L1 (step ST16).
- n is incremented by 1 (step ST33), and it is determined whether or not the incremented n is 4 or less (step ST34). . If n is 4 or less, the pixel value of that pixel is compared again with L1 (step ST16).
- step ST18 it is determined whether or not the pixel value is smaller than L2 (step ST18). If the pixel value Xmn is smaller than L2, the quantization of this pixel is performed. Set the level ⁇ ijk to binary 0 0 1 (step ST 19). Next, m is incremented by 1 (step ST31), and it is determined whether or not m is 4 or less (step ST32). If m is 4 or less, the pixel value of that pixel is compared again with L 1 (step ST 16). If m is greater than 4, n is incremented by 1 (step ST33), and it is determined whether or not the incremented n is 4 or less (step ST34). If n is 4 or less, the pixel value of that pixel is compared with L 1 again (step ST 16).
- the pixel values are L1 to L2, L2 to L3, L3 to LA, LA to L5, L5 to L6, and L6 to L7.
- the encoded data of the unit block are L A, L D, and ⁇ ijk for each pixel.
- FIG. 10 is a diagram showing a state where the image data of each unit block encoded by the fixed-length encoding circuit 5 is stored in the encoding memory 6.
- the image data of one block rearranged by the pixel rearranging circuit 4 as shown in (1) in FIG. 10 is encoded data (each image) in color units as shown in (2) in FIG.
- the number of the signal is indicated by adding an e (for example, the encoded data of the image signal G 1 is indicated by G 1 e).
- Fig. 11 shows the storage state of this block unit for the whole image of one field.
- FIG. 12 is a diagram showing a memory capacity required for storing data encoded by the fixed-length encoding circuit 5 in the encoding memory 6.
- the encoded data has the average level LA Is 8 bits (1 byte), gradation width index LD is 8 bits (1 byte), quantization level 0 ijk is 3 bits X 16 pixels (number of pixels in 1 unit block) is 4 Since it is 8 bits (6 bytes), one unit block requires only a total of 64 bits (8 bytes).
- 8 X 16 1 2 8 (16 bytes) of memory is required, and the data compression ratio is 1/2.
- the encoded 1 unit block A 10-byte memory capacity is required to store the image data.
- a 3-byte memory capacity is required for the average level LA and the gradation width index LD.
- the required memory capacity is 9 bytes.
- FIG. 13 is a diagram showing the memory capacity required to store one frame of image signal in the encoding memory 6 corresponding to the VGA (VariableGraphicsArray) standard.
- the image data of one pixel is represented by 8 bits.
- the total memory capacity required for storing the encoded data is 1228800 bits (153600 bytes) in total.
- the total memory capacity required to store the encoded data is 192000 bytes.
- the memory capacity required to store the encoded data The total is 17 28 00 bytes.
- the color image signals are rearranged by color, encoded by one encoding circuit, and the image data stored in the encoding memory 6 is reproduced and displayed.
- the image data must be read and decoded by the fixed-length decoding circuit 7.
- FIG. 14 is a flowchart showing the operation of the fixed-length decoding circuit 7.
- the fixed-length decoding operation of the fixed-length decoding circuit 7 will be described with reference to this flowchart.
- the fixed-length decoding circuit 7 When the fixed-length decoding operation is started, the fixed-length decoding circuit 7 first sets the vertical coordinate value n to 1 (step ST40), and then sets the horizontal coordinate value m to 1. (Step ST41). That is, the address of the coordinate value (1, 1) in a certain unit block is designated by the operations of steps ST40 and ST41.
- the fixed-length decoding circuit 7 determines the number of quantization levels ⁇ ijk of the specified address (steps ST 42, ST 44, ST 46, ST 48, ST 50, ST 52, ST 54), the signal intensity ⁇ mn (coordinate value (1, 1)) of the pixel based on the average value level LA and the gradation width index LD according to each determined quantization level ⁇ ijk If the pixel is the pixel of the above, Y11) is obtained (steps ST43, ST45, ST47, ST49, ST51, ST53, S ⁇ 55, ST56).
- step ST57, ST58 After obtaining the signal strength of the pixel (1, 1), the pixel is moved horizontally by one (step ST57, ST58), and the signal strength of the pixel (2, 1) is calculated in the same procedure. Decryption is performed (step ST42 to ST56).
- step ST58 After decoding the signal intensity for the uppermost pixel in the unit block in this way (step ST58), the vertical coordinate value is incremented by 1 (step ST59). Then, the signal strength of the next pixel is decoded in the same manner (steps ST42 to ST58).
- the signal intensities are decoded for all the pixels in the unit block (steps ST41 to ST60), and the decoding operation ends.
- the data decoded by the fixed-length decoding circuit 7 is subjected to reverse rearrangement processing on the data rearranged by the pixel rearrangement circuit 4, and the pixel signal is converted. Sort in the same order as when reading in the scanning line direction.
- the image data whose arrangement order is restored by the pixel reverse rearrangement circuit 8 is subjected to various kinds of image processing such as pixel interpolation, gradation correction, and error correction in a signal processing circuit 9.
- the image signals that are arranged in the same manner as the original image signals in the dot sequence in the scanning line direction and subjected to image processing are stored in the frame memory 10.
- the image signal stored in the frame memory 10 is read out to the display device 12 and displayed as an image.Then, the signal is compressed again by the variable length coding circuit 11 and stored in the secondary storage device 13 for storage. Is done.
- an image sensor capable of special reading as the image sensor 1 and image signals are transmitted in a normal dot-sequential manner.
- An image sensor that outputs signals can be used, and encoding can be performed using only the color image signal data for each color in the block. Encoding can be performed without receiving the signal. Further, an effect that can be realized by using a single-system coding circuit and a small-capacity coding memory is obtained.
- the image data is stored in the encoding memory after signal compression, a large amount of image data can be stored in the encoding memory without increasing the capacity of the special encoding memory. Evening can be stored, which has the effect of enabling high-speed continuous shooting.
- the image before and after the continuous shooting during continuous shooting is optically shifted by 1 / c (c is an integer of 2 or more) pixels, and the number of pixels is increased by pixel interpolation or the like to increase the number of pixels.
- c is an integer of 2 or more
- the processing by each of the fixed-length decoding circuit 7, the pixel reverse-parallel conversion circuit 8, the signal processing circuit 9, and the variable-length coding circuit 11 is realized by hardware.
- each of these processes does not necessarily require real-time processing, it may be realized by software processing. Processing by software is more advantageous than hardware processing in terms of versatility, flexibility, and cost.
- the frame memory 10 is necessarily provided. It is not necessary, and the encoding memory 6 can function as the frame memory 10. That is, fixed-length coding By using the method, an effect that the frame memory 10 can be reduced can be obtained.
- the gradation width index LD is divided into eight equal parts and encoded.
- the quantization level ⁇ ijk may be changed for each color.
- the quantization level of G may be 8 steps of 3 bits, R and B may be 4 steps of 2 bits, or the quantization level of G may be 8 steps of 3 bits, and R B may have two stages of 1 bit.
- the quantization level of G may be 4 levels of 2 bits;; and B may be 2 levels of 1 bit, or the quantization level may be 4 bits or more.
- the arrangement of the unit blocks shown in FIGS. 4, 5, and 10 in a block of 8 pixels in length and width is merely an example, and it is a matter of course that other arrangements may be made.
- the fixed-length coding method is only an example here, and the same effect can be obtained even if the method of calculating the threshold value or the method of calculating the quantization level is different. What is important in the coding method of the present invention is that the coding method is completed within a block and the code length is fixed.
- the signal intensities of all the pixels in the unit block are averaged at a level LA. If the image is displayed only with the luminance signal, the resolution of the displayed image will be reduced to 1/16, but the decoding and the pixels in the block will be performed.
- Embodiment 2 This eliminates the need for overnight sorting, making it possible to display images at extremely high speed. Furthermore, if the unit block is processed as a signal of one pixel whose signal strength is the average value level LA, the image captured as one frame image is displayed at 1/16 the size of the display screen of the display device 11. This allows 16-screen multi-screen display. In these displays, the color information, resolution information, etc. are reduced, but this is effective for applications where only the rough contents of the image need to be known. The effect is obtained that can be used as a short display mode.
- Embodiment 2 Embodiment 2
- FIG. 15 is a diagram showing a result of rearranging empty images in a line buffer of a rearranging circuit of a still image capturing apparatus according to Embodiment 2 of the present invention.
- the other parts of the second embodiment are the same as those of the first embodiment, and a description thereof will be omitted.
- the unit block is composed of 2 ⁇ 8 pixels
- the line buffer needs to be four lines at a time, and the effect of reducing the capacity of the line buffer can be obtained.
- the fixed-length encoding / decoding processing is the same as that of the first embodiment except that the reference position (coordinate calculation) of the pixel in the unit block is 4 ⁇ 4 pixels.
- FIG. 16 is a diagram showing a result of rearrangement of all images in the line buffer of the rearrangement circuit of the still image capturing apparatus according to Embodiment 3 of the present invention.
- the other parts of the third embodiment are the same as those of the first embodiment, and a description thereof will not be repeated.
- the unit block of the R signal and the B signal is composed of 2 ⁇ 8 pixels
- the unit block of the G signal, in which the image quality is conspicuous is composed of 4 ⁇ 4.
- encoding / decoding is performed by two types of unit blocks. Two systems are required according to the size (4 x 4 and 2 x 8), but the effect of using a line buffer with a small capacity is only 4 lines each as in the second embodiment. In addition, by performing a 4 ⁇ 4 unit block process on the G signal in which the image quality is conspicuous, an effect of obtaining a display image with little image quality deterioration can be obtained.
- FIG. 17 is a configuration diagram of a still image capturing apparatus according to Embodiment 4 of the present invention.
- the same components as those of the still image capturing apparatus according to Embodiment 1 in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
- reference numerals 15 and 16 denote selectors for selecting and outputting one input signal from a plurality of input signals.
- selectors 15 and 16 for selecting and outputting an input signal are provided so that a case where fixed length coding is performed and a case where fixed length coding is not performed can be selected.
- the fixed-length coding When the fixed-length coding is not performed, one frame of image signal is stored in the coding memory 6 so that it can be used particularly for photographing that does not require high speed.
- image signals for two frames are stored in the encoding memory 6 for one frame.
- the effect of enabling high-speed continuous shooting can be obtained.
- the read-out image data is decoded to a fixed-length by the fixed-length decoding circuit 7 and the pixel is rearranged by the pixel rearrangement circuit 8. Do.
- the capacity of the encoding memory 6 is increased, or another memory such as a floppy disk or a hard disk is provided together with the encoding memory. May be provided.
- the access speed of memories such as floppy disks and hard disks is slower than that of semiconductor memories, and it is difficult to directly store the output signal from the image sensor 1 that is output at high speed. By doing so, the amount of data is reduced and the apparent transfer rate is reduced, so that storage becomes easier. In this case, continuous capture of at least a large number of images is prioritized, and this is effective for applications where image processing and display are secondary.
- the fourth embodiment it is possible to obtain an effect that the display method on the display device 11 can be changed depending on whether or not high-speed continuous shooting is performed.
- an R, G, B image signal system has been described as an example of an image signal to be encoded.
- the present invention is not limited to other image signals such as a complementary color image signal system and a luminance image signal system. Similar effects can be obtained for signal-based image processing.
- an example in which the image processing apparatus is applied to a still image capturing apparatus as a still camera has been described.
- the application field of the image processing apparatus is not limited to this, and a predetermined mixed image including a plurality of color components is used. Any device that outputs an output signal of the number of pixels may be used.
- the present invention can be applied to devices such as a facsimile device, a copier device, and a printer. Industrial applicability
- the image processing apparatus the still image capturing apparatus, and the image processing method according to the present invention provide an apparatus for encoding, compressing, and storing an image signal having a plurality of color components in a memory. It is suitable for realizing high-speed continuous shooting, high-definition high-speed reproduction, etc. using elements and small-capacity memory.
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98909793A EP0907294A4 (en) | 1997-03-21 | 1998-03-20 | IMAGE PROCESSING DEVICE, FIXED SHOOTING DEVICE AND IMAGE PROCESSING METHOD |
US09/171,100 US6269183B1 (en) | 1997-03-21 | 1998-03-20 | Image processing device and still image pickup device, and method for processing image |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9/68788 | 1997-03-21 | ||
JP6878897A JPH10271529A (ja) | 1997-03-21 | 1997-03-21 | 画像処理装置及び静止画像撮像装置並びに画像処理方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998043440A1 true WO1998043440A1 (en) | 1998-10-01 |
Family
ID=13383822
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1998/001214 WO1998043440A1 (en) | 1997-03-21 | 1998-03-20 | Image processing device and still image pickup device, and method for processing image |
Country Status (5)
Country | Link |
---|---|
US (1) | US6269183B1 (ja) |
EP (1) | EP0907294A4 (ja) |
JP (1) | JPH10271529A (ja) |
CN (1) | CN1119031C (ja) |
WO (1) | WO1998043440A1 (ja) |
Families Citing this family (18)
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JP3289712B2 (ja) * | 1999-09-24 | 2002-06-10 | 日本電気株式会社 | ディジタル画像データの圧縮方法及びその装置 |
TW508940B (en) * | 2000-03-28 | 2002-11-01 | Omnivision Tech Inc | Method and apparatus for color image date processing and compression |
US7188778B2 (en) * | 2001-09-17 | 2007-03-13 | Codemagic | Machine-readable symbol and related method |
US7102789B2 (en) * | 2001-09-17 | 2006-09-05 | Sharp Laboratories Of America, Inc. | Method for rendering an image comprising multi-level pixels |
JP3956360B2 (ja) * | 2002-09-30 | 2007-08-08 | 株式会社リコー | 撮像装置及び画像処理方法 |
AU2002368463A1 (en) * | 2002-12-18 | 2004-07-09 | Nokia Corporation | Image data compression device and decompression device and image data compression program and decompression program |
JP4189252B2 (ja) * | 2003-04-02 | 2008-12-03 | パナソニック株式会社 | 画像処理装置及びカメラ |
KR100834439B1 (ko) * | 2004-05-29 | 2008-06-04 | 삼성전자주식회사 | 그래픽 데이터 압축 및 복원 장치와 그 방법 |
JP4079122B2 (ja) * | 2004-06-10 | 2008-04-23 | 三菱電機株式会社 | 液晶駆動用画像処理回路、および液晶駆動用画像処理方法 |
JP4151684B2 (ja) * | 2005-01-26 | 2008-09-17 | ソニー株式会社 | 符号化装置、符号化方法および符号化プログラム、並びに撮像装置 |
US7719579B2 (en) * | 2005-05-24 | 2010-05-18 | Zoran Corporation | Digital camera architecture with improved performance |
JP4508132B2 (ja) * | 2006-02-27 | 2010-07-21 | ソニー株式会社 | 撮像装置、撮像回路、および撮像方法 |
JP4494490B2 (ja) * | 2008-04-07 | 2010-06-30 | アキュートロジック株式会社 | 動画処理装置及び動画処理方法、動画処理プログラム |
US8942490B2 (en) * | 2008-07-08 | 2015-01-27 | Yin-Chun Blue Lan | Method of high performance image compression |
EP2613552A3 (en) * | 2011-11-17 | 2016-11-09 | Axell Corporation | Method for moving image reproduction processing and mobile information terminal using the method |
JP6053321B2 (ja) * | 2012-05-16 | 2016-12-27 | オリンパス株式会社 | 固体撮像装置 |
CN107018297B (zh) * | 2015-11-27 | 2020-10-13 | 钰立微电子股份有限公司 | 图像获取装置 |
CN110996127B (zh) * | 2019-11-25 | 2022-12-09 | 西安万像电子科技有限公司 | 图像编解码方法、设备及系统 |
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JPH04170886A (ja) * | 1990-11-05 | 1992-06-18 | Canon Inc | 撮像装置及び記録再生方式 |
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JPH0690435A (ja) * | 1992-09-07 | 1994-03-29 | Canon Inc | 画像再生装置 |
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JPH04298170A (ja) | 1991-03-27 | 1992-10-21 | Konica Corp | ディジタルスチルビデオカメラ |
JPH057340A (ja) | 1991-06-20 | 1993-01-14 | Canon Inc | 撮像装置 |
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JPH07274006A (ja) | 1994-03-28 | 1995-10-20 | Mitsubishi Electric Corp | 画像処理装置及びスキャナ装置及びプリンタ装置及びディジタル複写機及びディスプレイ装置 |
JPH07322075A (ja) | 1994-03-29 | 1995-12-08 | Mitsubishi Electric Corp | 画像処理装置及びスキャナ装置及びプリンタ装置及びディジタル複写機及びディスプレイ装置 |
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- 1997-03-21 JP JP6878897A patent/JPH10271529A/ja not_active Abandoned
-
1998
- 1998-03-20 EP EP98909793A patent/EP0907294A4/en not_active Withdrawn
- 1998-03-20 CN CN98800338A patent/CN1119031C/zh not_active Expired - Fee Related
- 1998-03-20 US US09/171,100 patent/US6269183B1/en not_active Expired - Fee Related
- 1998-03-20 WO PCT/JP1998/001214 patent/WO1998043440A1/ja not_active Application Discontinuation
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JPH04170886A (ja) * | 1990-11-05 | 1992-06-18 | Canon Inc | 撮像装置及び記録再生方式 |
JPH0654209A (ja) * | 1992-08-03 | 1994-02-25 | Mitsubishi Electric Corp | 画像圧縮・伸長回路 |
JPH0690435A (ja) * | 1992-09-07 | 1994-03-29 | Canon Inc | 画像再生装置 |
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Also Published As
Publication number | Publication date |
---|---|
EP0907294A1 (en) | 1999-04-07 |
EP0907294A4 (en) | 2004-05-26 |
CN1119031C (zh) | 2003-08-20 |
CN1220806A (zh) | 1999-06-23 |
US6269183B1 (en) | 2001-07-31 |
JPH10271529A (ja) | 1998-10-09 |
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