WO1998032164A1 - Procede de production de films pelliculaires de silicium - Google Patents

Procede de production de films pelliculaires de silicium Download PDF

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Publication number
WO1998032164A1
WO1998032164A1 PCT/AU1998/000027 AU9800027W WO9832164A1 WO 1998032164 A1 WO1998032164 A1 WO 1998032164A1 AU 9800027 W AU9800027 W AU 9800027W WO 9832164 A1 WO9832164 A1 WO 9832164A1
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WIPO (PCT)
Prior art keywords
film
substrate
layer
etchant
regions
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PCT/AU1998/000027
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English (en)
Inventor
Klaus Johannes Weber
Andrew William Blakers
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Boral Energy Limited
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Application filed by Boral Energy Limited filed Critical Boral Energy Limited
Priority to CA 2278174 priority Critical patent/CA2278174A1/fr
Priority to AU55440/98A priority patent/AU743826B2/en
Priority to JP53341198A priority patent/JP2001508947A/ja
Priority to EP98900480A priority patent/EP0970514A4/fr
Publication of WO1998032164A1 publication Critical patent/WO1998032164A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This invention relates to an improved method of production of single crystalline layers of silicon of arbitrary size and shape, suitable for processing into silicon solar cells and other semiconductor devices.
  • Silicon films several tens of microns thick are an excellent material on which to fabricate highly efficient solar cells.
  • the silicon material should be single crystalline, or the grains of the multicrystalline material should be as large as possible.
  • Single crystal silicon can be obtained by the Czochralski (Cz) or floating zone (FZ) techniques, while large grained multicrystalline silicon can be obtained by casting techniques. All these methods produce large blocks of silicon which have to be sliced to produce wafers suitable for solar cells. Half the silicon is wasted as sawdust during slicing. The wafers are expensive and usually several hundred microns thick.
  • a procedure is in use for gallium arsenide devices, which relies on the large selectivity of some etchants for AlAs over GaAs and some AlGaAs compounds.
  • AlGaAs is grown on a GaAs wafer followed by GaAs and/or AlGaAs. Black wax applied to the upper GaAs/AlGaAs layer places it under tension.
  • the structure is then immersed in a suitable etchant, which etches AlAs laterally without significantly etching the GaAs or AlGaAs layers. After a long period the top GaAs layer floats off.
  • the process is not suitable for silicon because no known silicon etchant has the large selectivity that is available for the GaAs/AlAs system.
  • a masking layer is deposited on a single crystal substrate, usually GaAs.
  • Line openings formed in the masking layer provide the seeds for subsequent epitaxial growth.
  • the epitaxial layers overgrow the line seed openings laterally and eventually impinge on each other to produce a continuous epitaxial film.
  • the masking layer is completely buried beneath the epitaxial layer.
  • the epitaxial layer is then attached to a suitable secondary substrate. If the regions where the epitaxial layer is attached to the substrate are sufficiently narrow, and if the adhesion of the epitaxial layer to the masking layer is sufficiently weak, the epitaxial layer can be cleaved off the substrate. The process has not been successfully applied to silicon.
  • ZMR zone melting recrystallization
  • this invention provides a method of producing thin single crystal silicon films, said method including the steps of forming a single crystal substrate; depositing or forming a thin single crystal silicon film having the same crystal orientation as said substrate in, on or adjacent to said substrate and providing a plurality of spaced apart etchant access regions through said film or substrate and causing liftoff of said film by simultaneous etching via said etchant access regions, the amount of etching required and the degree of access for etchant providing for detachment without significant degradation of said film.
  • a buffer layer of silicon having the same crystal orientation as the substrate and containing concentrations of impurities resulting in the buffer layer having a significantly faster etch rate in a selected etchant than either the film or the substrate is epitaxially grown or formed between the substrate and film, said etchant access regions providing for selective etching of the buffer layer.
  • an etch stop layer of silicon having the same crystal orientation as the substrate and containing concentrations of impurities which result in the etch stop layer having a significantly slower etch rate in a selected etchant than the silicon of the substrate or film is epitaxially grown or formed on or in the substrate or film to define the etchant access regions.
  • a masking layer of non silicon material is deposited and patterned oil the substrate to define attachment regions of exposed substrate, the attachment regions having at least one dimension small in comparison to spacings between adjacent regions, and the film is deposited on the substrate at the attachment regions.
  • a masking layer of non silicon material is preferably deposited and patterned on the substrate or buffer layer to define attachment regions of exposed substrate or buffer layer.
  • the masking layer is deposited and patterned on a surface of the substrate, followed by deposition of the buffer layer at the attachment regions and the film is then deposited on the buffer layer.
  • the substrate can be formed with a plurality of apertures extending through the entire thickness of the substrate. The apertures can be formed by means of reactive ion etching or laser ablation.
  • the buffer layer is formed or deposited on or in the substrate, the masking layer is deposited and patterned on the buffer layer, the film is deposited on the buffer layer at the attachment regions, and the masking layer is removed prior to liftoff of said film.
  • the method can include the further steps of depositing the film by chemical vapour deposition so that polycrystalline silicon is deposited on said masking layer and subsequently removing the polycrystalline silicon in an etchant which does not significantly attack the single crystal layers constituting the substrate, buffer and film, the removal of the polycrystalline film and the removal of said masking layer creates the etchant access regions.
  • the buffer layer is formed or deposited substantially continuously over a surface of the substrate, the film is deposited on the buffer layer and the etchant access regions are formed through the film.
  • the buffer layer is preferably doped p type to a concentration of about 5 x 10 19 cm "3 and the anisotropic etchant is ethylenediamine procatechol.
  • the buffer layer can be formed by selectively doping the surface of the substrate. In other forms of the invention the buffer layer is deposited on a surface of the substrate.
  • a masking layer of non silicon material is deposited and patterned on the substrate to define attachment regions of exposed substrate, the film is subsequently deposited on the substrate at the attachment regions and at least part of the masking layer is removed prior to liftoff of the film.
  • the film is deposited on the substrate such that holes remaining in the film following deposition form at least part of the etchant access regions.
  • the film forms said etch stop layer.
  • the etch stop layer can be formed or deposited in or on the film to protect a corresponding part of said film from being etched during selective etching to effect liftoff of the film.
  • the etch stop layer is formed by means of a phosphorus diffusion into the film.
  • the film is formed in the substrate by selectively doping part of the substrate with a suitable dopant, the film acting as an etch stop layer during subsequent etching to effect liftoff of the film with those regions of the substrate not doped forming the plurality of etchant access regions.
  • the substrate is preferably p type and said film is preferably n type and the liftoff is effected by electrochemical etching in an aqueous, hydrofluoric acid containing etchant which does not significantly etch n type silicon.
  • the etch stop layer preferably is formed by means of a phosphorus diffusion into the substrate.
  • an epitaxial layer is grown on the film following liftoff but prior to final detachment of the film from the substrate.
  • the film is formed from part of the substrate.
  • the invention preferably includes the further steps of forming blind access apertures in the substrate, doping the exposed aperture surfaces of the substrate to form a doped lining layer, removing the lining layer at the blind end of the apertures to expose the substrate and etching the substrate to provide for liftoff of the film, the doped lining layer forming part of the film and acting as an etch stop layer during the etching to provide for liftoff of the film.
  • the substrate is p type and the lining layer is n type and liftoff is effected by electrochemical etching in an aqueous, hydrofluoric acid containing etchant which does not significantly etch n type silicon.
  • the doped lining layer is preferably formed by means of a phosphorus diffusion.
  • the amount of substrate being etched to provide for liftoff of the film is small compared to the overall thickness of the substrate.
  • the masking layer is removed prior to liftoff of the film, the removal of the masking layer forming cavities between the film and the substrate, with the cavities forming at least part of the etchant access regions.
  • the film is deposited on the substrate such that holes in the film form the etchant access regions.
  • the amount of overgrowth of the film over the masking layer is preferably limited, and the invention preferably further including the steps of etching the film at or adjacent the attachment regions to effect liftoff, the dimensions of the attachment regions providing for liftoff without significant degradation of the film.
  • the substrate is of (100) orientation and said attachment regions form two mutually perpendicular sets of equally spaced elongate regions in the ⁇ 110> directions of the substrate and growth of the buffer layer and the film is carried out by liquid phase epitaxy, resulting in a highly textured film surface displaying faces orientated close to ⁇ 111 ⁇ crystallographic planes.
  • the third form of the invention preferably includes the further steps of depositing the film by chemical vapour deposition, so that polycrystalline silicon is deposited on the masking layer; and subsequently removing said polycrystalline silicon in an etchant which does not significantly attack the single crystal layers constituting the substrate, buffer and film, removal of said polycrystalline film and the removal of said masking layer creating the etchant access regions.
  • the substrate is preferably of near (111) orientation and the film overgrows the masking layer essentially without leaving a gap between the masking layer and said film.
  • the etchant access regions are less densely spread than the remaining etchant access regions so that at least part of the film or substrate is not completely etched through when liftoff is complete and provides a physical connection between said film and substrate.
  • the etchant access regions preferably form a regular array.
  • Liquid phase epitaxy LPE
  • chemical vapour deposition CVD
  • Either wet chemical etching or gas phase etching can be used to perform the various etching steps.
  • the silicon substrate is only exposed in well defined attachment regions on the surface of the substrate. This can be achieved by patterning the substrate with the masking layer. Growth of the epitaxial film or buffer layer occurs only out of the regions where the silicon substrate is exposed, and in such a way that the epitaxial silicon film or layer forms a continuous structure. Following growth, the epitaxial layer is detached from the substrate with a suitable etchant, which is brought in contact with those regions where the epitaxial layer is attached to the silicon of the substrate through numerous holes in the substrate or in the epitaxial layer, or by cleaving the epitaxial layer off the substrate.
  • the epitaxial layer can be several microns to more than 100 microns thick.
  • the substrate forms the film and in some forms the substrate only acts as a growth template. In both cases the substrates can be re-used.
  • Handling of the epitaxial layers can be done either by growing the layers sufficiently thick so that they are self supporting, or by carrying out the processing while the layer is still attached to the substrate. In the latter case, the layer is attached to a supporting superstrate prior to final detachment from the substrate.
  • the films are perforated, in other words, they contain a plurality of holes. Advantage can be taken of these holes in the fabrication of solar cells.
  • a metal grid is required on the sunward facing or 'top' side of the cell in order to collect one type of carriers (electrons or holes) which are generated by the action of sunlight, with the other type of carrier being collected by an electrical contact on the reverse, or 'bottom' side of the cell.
  • carriers electrosprays
  • the presence of a metal grid on the sunward side of the cell leads to the shadowing of a part of the underlying cell from sunlight and consequently in a loss of electrical energy and energy conversion efficiency of the cell.
  • a perforated silicon layer is used for fabrication of the solar cell, it is possible to position both sets of metal contact grids on the bottom side of the cell.
  • a further advantage arising out of the fact that the films are perforated, is that solar cells can be made semi-transparent, and that the amount of transparency can be easily varied. This can be of benefit where the films are used for the fabrication of solar cells for special applications, such as for buildings, where a certain degree of transparency is desirable.
  • the resulting film surface is highly textured with faces whose orientation is close to that of ⁇ 111 ⁇ crystallographic planes. This type of texturing is desirable for the case where the films are used for the fabrication of solar cells as it significantly increases the average probability of absorption of a ray of sunlight in the film, and therefore significantly increases the conversion efficiency potential of the solar cells.
  • the present invention provides a method to grow thin silicon epitaxial films on a pre-existing silicon template, lift off the epitaxial film and then re-use the template.
  • the substrate is slowly consumed but can be made thick enough to be used many times.
  • the methods of this invention have the potential to lower the cost of producing the silicon films as well as increase the efficiency of the solar cells made on the films, since the resulting film thickness is closer to the optimal thickness for solar cells.
  • the large area growth and liftoff of silicon films grown epitaxially on a silicon substrate, followed by re-use of that substrate, has not been carried out previously.
  • Figure 1 shows a perspective view of a part of a silicon wafer after growth of the silicon buffer layer and deposition of the masking layer but prior to growth of a liftoff layer according to one embodiment of the invention
  • Figure 2 shows a cross sectional view of the structure resulting after growth of a liftoff layer on the substrate shown in Figure 1 ;
  • Figure 3 shows a perspective view of the structure shown in Figure 2;
  • Figure 4 shows a perspective view of a part of a silicon wafer prior to growth of buffer and liftoff layers according to another embodiment of the invention
  • Figure 5 shows a cross sectional view of the structure resulting after growth of a heavily doped silicon buffer layer, followed by a liftoff layer, on the substrate shown in Figure 3;
  • Figure 6 shows a perspective view of a part of a silicon wafer prior to growth of buffer or liftoff layers according to another embodiment of the invention
  • Figure 7 shows a perspective view of a part of a silicon wafer following deposition of a patterned masking layer but prior to growth of a liftoff layers according to another embodiment of the invention
  • Figure 8 shows a cross-sectional view of the structure resulting after growth of the liftoff layer on the substrate shown in Figure 7;
  • Figure 9 shows a perspective view of a part of a silicon wafer deposition and patterning of the masking layer according to another- embodiment of the invention;
  • Figure 10 shows a cross sectional view of the structure resulting after growth of an epitaxial liftoff layer on a (111) oriented silicon wafer patterned with a masking layer to form a pattern similar to that shown in Figure 1 ;
  • Figure 11 shows a cross sectional view of a part of a silicon wafer prior to growth of the liftoff layer according to another embodiment of the invention;
  • Figure 12 shows a plan view of the wafer of Figure 9
  • Figure 13 shows a cross sectional view of the structure resulting after growth of a liftoff layer, on the substrate shown in Figure 11 ; and Figure 14 shows a plan view of a corner of a silicon wafer prior to growth of the liftoff layer according to another embodiment of the invention.
  • Figure 15 shows a plan view of part of a silicon wafer used in another embodiment of the method of this invention.
  • Figure 16 shows a cross-sectional view of the wafer shown in Figure 15
  • Figure 17 is a cross-sectional view similar to Figure 16 schematically showing an etching step in the method according to the embodiment of this invention
  • Figure 18 is a plan view of a corner of a wafer of the kind shown in part in Figure 15;
  • Figure 19 is a cross-sectional view of a structure resulting after the growth of a epitaxial layer on the structure shown in Figure 17;
  • Figure 20 is a cross-sectional view of a silicon wafer on which a buffer layer and epitaxial layer have been grown in accordance with a method of a further embodiment of this invention;
  • Figure 21 is a plan view of the structure shown in Figure 20 after deposition and patterning of an etch protect layer;
  • Figure 22 is a cross-sectional view of the structure found in Figure 21 after aniso tropic etching;
  • Figure 23 is a cross-sectional view of the structure of Figure 22 after further etching to detach the epitaxial layer;
  • Figure 24 is a plan view of a silicon wager after deposition and patterning of an etch protect layer as used in a further embodiment of this invention.
  • Figure 25 is a cross-sectional view of the structure shown in Figure 24 after aniso tropic etching
  • Figure 26 is a cross-sectional view of the structure shown in Figure 25 after further doping and etching;
  • Figure 27 is a cross-sectional view similar to Figure 26 schematically showing a detaching etching process;
  • Figure 28 is a cross-sectional view of the resulting detached silicon film
  • Figure 29 is a cross-sectional view of a structure formed as part of a method according to a further embodiment of this invention.
  • Figure 30 is a plan view of the structure shown in Figure 29;
  • Figure 31 is a cross-sectional view of a structure formed during performance of a method according to another embodiment of this invention;
  • Figure 32 is a plan view of the structure shown in Figure 31 ;
  • Figure 33 is a cross-sectional view of a structure formed during performance of a method according to yet another embodiment of the inventions.
  • Figure 34 is a cross-sectional view of a structure formed during performance of a method according to yet another embodiment of the invention.
  • Figure 35 is a schematic cross-sectional view of solar cell produced using a thin silicon film formed according to the method of this invention.
  • a thin single crystal silicon film which is detached from the substrate and subsequently used for the fabrication of devices, for example solar cells. It has the same crystallographic orientation as the substrate. In some cases an epitaxial layer is grown on the liftoff layer following liftoff but prior to final detachment from the substrate.
  • the process of physically separating the liftoff layer from the substrate This can occur at the same time as liftoff, or at some stage following liftoff.
  • a layer of non-silicon material such as SiO 2 , which prevents the growth of an epitaxial layer of silicon on top of it.
  • Buffer layer A layer of silicon between the silicon substrate and the liftoff layer, and containing concentrations of impurities which result in a significantly faster etch rate in the etchant used for liftoff of the liftoff layer from the substrate, than the etch rate of either liftoff layer or substrate in that etchant. This results in the preferential etching of the buffer layer.
  • the buffer layer has the same crystallographic orientation as both the liftoff layer and the substrate.
  • the etch stop layer has the same crystallographic orientation as the substrate and always forms part of the liftoff layer.
  • Etch protect layer A layer of non-silicon material deposited and patterned on top of a silicon surface for the purpose of protecting the silicon immediately underlying the etch protect layer from being etched during a subsequent selective etching step.
  • Selective etching The process by which two materials which are simultaneously exposed to the same etchant, are etched at significantly different rates, as a result of differences in the physical or chemical properties of the bulk or the surfaces of the two materials.
  • Relevant examples of material/etchant systems which display such selective behaviour are the following:
  • LPE liquid phase epitaxy
  • Figure 1 shows a substrate 1 formed from undoped silicon of (100) orientation.
  • An epitaxial buffer layer 2 has been grown on the substrate, followed by deposition and patterning of a suitable masking layer 3.
  • the buffer layer 2 could have been formed by means of a boron diffusion into the substrate.
  • the buffer layer 2 is typically 10 ⁇ m thick, while the masking layer 3 is typically 0.1 ⁇ m thick.
  • Elongate regions 4 of exposed substrate defined by the masking layer 3 run along the ⁇ 110> directions. The regions 4 are typically 10 ⁇ wide and spaced 100 ⁇ m apart.
  • the buffer layer 2 consists of a layer of p type silicon which has been doped to about 5 x 10 18 cm " 3 with a suitable dopant such as gallium, while the substrate is much more lightly doped.
  • the masking layer 3 can be SiO 2 .
  • the areas in which the silicon substrate is exposed form a continuous mesh. The continuous mesh results in a continuous supply of atomic attachment sites during growth of the liftoff layer and ensures that the whole structure can overgrow without two epitaxial growth fronts impinging on one another, with a possible introduction of structural defects, such as dislocations.
  • Figures 2 and 3 show the structure resulting after epitaxial growth of a p type liftoff layer 5 on the substrate 1.
  • the liftoff layer 5 is typically 50 - 100 ⁇ m thick and is more lightly doped than the buffer layer 2.
  • the cross sectional view is along a ⁇ 110> direction. Growth of the liftoff layer 5 has occurred only in those regions not covered by the masking layer 3. It can be seen that the liftoff layer 5 displays a diamond shape in the cross sectional view.
  • the liftoff layer 5 is bounded by faces with near ⁇ 111 ⁇ orientations. Growth has been terminated in time to ensure that an array of holes 6 remains in the liftoff layer to provide etchant access regions.
  • the masking layer 3 is removed with a suitable etchant which does not significantly attack any of the silicon layers 1,2,5, such as a mixture of HF and H 2 O in the case where the masking layer 3 is SiO 2 . Access is provided through the holes 6 in the liftoff layer 5.
  • the buffer layer 2 is then removed with an etchant which etches the heavily doped silicon faster than the more lightly doped silicon of the substrate 1 or the liftoff layer 5. Access is again provided through the array of holes 6 in the liftoff layer.
  • One suitable etchant is the mixture HF:HNO 3 :CH 3 COOH in the ratio 1:3:8.
  • the etchant initially contacts the heavily doped buffer layer 2 in the regions where the masking layer prevented growth of the liftoff layer and gradually undercuts the liftoff layer 5 until the buffer layer 2 has been completely removed.
  • the resultant structure is textured. Advantage can be taken of this for purposes such as the reflection control of light in a solar cell, for example.
  • Figure 4 shows a substrate 1 formed from undoped silicon of (100) orientation.
  • a masking layer 3 has been deposited and patterned on the substrate 1.
  • the masking layer 3 defines two mutually perpendicular sets of elongate regions 4 of exposed substrate which run along ⁇ 110> directions.
  • Figure 5 shows the structure resulting after growth of a silicon buffer layer 2 and a liftoff layer 5 on the substrate of Figure 4 .
  • the cross sectional view is along a ⁇ 110 > direction. Growth of the epitaxial buffer 2 and liftoff layer 5 has occurred only in those attachment regions 4 not covered by the masking layer 3. Growth has been terminated in time to ensure that an array of holes 6 remains in the liftoff layer 5 to provide etchant access regions.
  • the buffer layer 2 consists of p type silicon which has been doped to at least 5 x 10 18 cm " 3 with a suitable dopant such as gallium, while the liftoff layer 5 is more lightly doped.
  • the masking layer 3 can be removed with a suitable etchant which does not significantly attack any of the silicon layers 1, 2, 5, although removal of the masking layer 3 is not essential. If the masking layer 3 is not removed, it can be re-used for the growth of subsequent liftoff layers.
  • the buffer layer 2 is removed with an etchant which etches the heavily doped silicon faster than the more lightly doped silicon of the substrate 1 or the liftoff layer 5, in order to effect liftoff of the liftoff layer 5.
  • Example 3 The substrate 1 shown in Figure 6 is undoped silicon of (100) orientation.
  • a masking layer 3 has been deposited and patterned on the substrate.
  • mutually perpendicular sets of elongate regions 4 of exposed substrate run in ⁇ 110> directions.
  • the structure is identical to that shown in Figure 4, except that the elongate regions 4 are much narrower, typically 1 ⁇ m wide.
  • Growth of the epitaxial layers (not shown) on this structure proceeds as described above in relation to Example 2 with the difference that the elongate attachment regions 4 where the epitaxial layer is attached to the substrate are much narrower. Liftoff is carried out as described above in Example 2. However, even if no buffer layer is grown, the epitaxial layer can still be lifted off the substrate with a silicon etchant, due the narrowness of the attachment regions which have to be etched through.
  • the substrate 1 shown in Figure 7 is p type silicon of (100) orientation which has been doped to at least 5 x 10 18 cm " 3 with a suitable dopant such as boron.
  • a masking layer 3 has been deposited and patterned on the substrate. The masking layer defines mutually perpendicular sets of elongate regions 4 of exposed substrate running along ⁇ 110 > directions.
  • Figure 8 shows the structure resulting after growth of a liftoff layer 5 on the substrate of Figure 7.
  • the cross sectional view is along a ⁇ 110> direction.
  • the masking layer 3 is removed with a suitable etchant which does not significantly attack any of the silicon layers 1 , 5.
  • Holes 6 in the lift off layer 5 form etchant access regions.
  • Some of the substrate is etched with an etchant which etches the heavily doped silicon of the substrate 1 faster than the more lightly doped silicon of the liftoff layer 5.
  • the liftoff layer 5 therefore acts as an etch stop layer.
  • the thickness of the layer of substrate that is etched away is small compared to the initial substrate thickness and therefore the substrate can be re-used many times.
  • Figure 9 shows a silicon substrate 1 in which array of holes 6 has been created by laser ablation or reactive ion etching.
  • the holes have typical dimensions of 50 ⁇ m by 50 ⁇ m.
  • a masking layer 3 has been deposited and patterned on the substrate 1 to define attachment regions 4 of exposed substrate.
  • the inside of the holes 6 has also been coated with the masking layer 3.
  • Growth of the epitaxial buffer and liftoff layers proceeds as described in the preceding examples. Growth of the liftoff layer may be continued until it forms a closed structure.
  • Etchant access regions for etchant solutions required to lift off the liftoff layer and/or the masking layer are provided by holes 6 in the substrate 1.
  • a (111) oriented silicon substrate 1 is shown in cross section in Figure 10, patterned with a thick masking layer 3 to produce a pattern similar to that shown in Figure 1.
  • the masking layer 3 is typically 1 ⁇ m thick, and elongate openings 4 in the masking layer 3 are typically 1 ⁇ m wide.
  • An epitaxial liftoff layer 5 has overgrown the masking layer without creating a cavity. In this way, solvent entrapment, which can occur in structures such as that shown in Figure 3 if grown by LPE, can be avoided.
  • the masking layer 3 is first removed using an etchant which etches the masking layer 3 but not either of the silicon layers 1, 5.
  • Removal of the masking layer 3 creates etchant access regions or cavities between the substrate and the liftoff layer.
  • a silicon etchant is poured into the cavities. After some time the etchant removes the regions where the liftoff layer 5 is attached to the substrate. Due to the narrowness of the attachment regions, liftoff can be carried out without substantially etching the liftoff layer 5.
  • Figures 11 and 12 show an undoped (100) oriented silicon substrate 1 textured to produce square base upright pyramids 7 on the substrate surface.
  • the view is in a ⁇ 110 > direction.
  • the sidewalls of the pyramids 7 have ⁇ 111 ⁇ orientations.
  • the bases of the pyramids 7 run along ⁇ 110 > directions.
  • the texturing can be achieved, for example, through the use of a potassium hydroxide (KOH) solution which etches the ⁇ 111 ⁇ planes of silicon much slower than other planes.
  • KOH potassium hydroxide
  • a masking layer 3 is deposited to define attachment regions 4 of silicon substrate exposed in narrow lines which run along the bases of the pyramids 7 in ⁇ 110> directions.
  • the attachment regions 4 are typically 1 ⁇ m wide.
  • Figure 13 shows an epitaxial liftoff layer 5 grown on the substrate shown in Figures 11 and 12. The view is in a ⁇ 110 > direction. If growth is carried out by LPE, entrapment of solvent may be kept very small with this structure.
  • the masking layer 3 is removed by an etch which does not etch either of the silicon layers 1 , 5. Removal of the masking layer 3 creates etchant access regions or cavities between the substrate and the liftoff layer. A silicon etchant is poured into the cavities so formed. After some time the etchant removes the regions where the liftoff layer 5 is attached to the substrate. Due to the narrowness of the attachment regions, the liftoff layer 5 is not significantly etched. - U
  • Figure 14 shows a substrate 1 formed from silicon of (100) orientation.
  • a masking layer 3 has been deposited and patterned on the substrate 1.
  • Attachment regions 4 of exposed substrate are defined by the masking layer and run in ⁇ 110 > directions. Growth of the epitaxial buffer and liftoff layers (not shown) on this substrate is carried out as described in the preceding examples.
  • the attachment regions 4 are wider at the substrate 1 edges than in the inner parts of the substrate. Consequently, etchant access regions formed by removing the masking layer 3 are less densely spaced at the periphery of the substrate 1.
  • a suitable etchant is used to remove the buffer layer, the liftoff layer is detached from the substrate in the inner regions of the substrate before it is detached at the edges.
  • Etching can be stopped at this stage and the epitaxial layer can be processed.
  • the liftoff layer is not attached to the substrate 1 anywhere except at the edges, but it is still supported by the substrate 1.
  • the liftoff layer can be attached to a suitable superstate such as glass, and the regions of the liftoff layer which are still attached to the substrate are removed. This can be done, for example, by dicing through the liftoff layer at the edges. This approach provides a means of processing liftoff layers which are too thin to be self supporting.
  • Example 9 Figures 15 and 16 show a single crystal silicon substrate 1 of arbitrary crystal orientation.
  • the substrate is p type with a dopant concentration of typically 10 17 cm ' 3 .
  • a selective phosphorus diffusion has been made into the substrate 1 after suitable photolithographic masking (not shown), to create a moderately doped n type layer, which forms the liftoff layer 5.
  • the p type areas 8 remaining on the surface of the substrate 1 following the phosphorus diffusion are typically 4 ⁇ m across and are spaced apart by typically 10 ⁇ m.
  • the liftoff layer 5 is typically 4 ⁇ m deep.
  • the wafer is etched in an electro-chemical etchant consisting of, for example, 5 % aqueous hydrogen fluoride which attacks p-type silicon of the substrate 1 but does not significantly etch moderately doped n-type silicon of the liftoff layer 5.
  • the liftoff layer 5 acts as an etch stop layer.
  • the etching process proceeds to remove a layer of the substrate through the exposed p type areas 8 surrounded by the liftoff layer 5 which form etchant access regions.
  • the etching eventually removes all the substrate 1 from below the liftoff layer, thus lifting off the liftoff layer 5, as schematically shown in Figure 17 .
  • the liftoff layer 5 is kept attached to the substrate 1 by using a slightly different pattern at the wafer corners as shown in Figure 18 and described above in Example 8. That is, a greater distance is provided between the exposed p type areas 8 of the substrate so that the etchant takes longer to completely undercut the liftoff layer 5 adjacent those areas.
  • an epitaxial layer 9 can be grown on the liftoff layer as shown in Figure 19.
  • the composite epitaxial layer 9 and liftoff layer 5 can be detached from the substrate 1 by the application of a small shear force sufficient to break through the remaining corner attachment regions, or by cutting through the remaining attachment regions.
  • the substrate 1 is etched slightly during this process but can be reused many times as the amount of silicon lost during the production of each layer is only of the order of 10 ⁇ m, and the substrate can be made greater than 500 ⁇ m thick.
  • a p-type epitaxial buffer layer 2, doped to greater than 10 19 cm “3 is grown on an n-type silicon substrate 1 of (110) orientation followed by an n-type epitaxial liftoff layer 5. Both the substrate 1 and the liftoff layer 5 are doped to a concentration of typically 10 17 cm “ 3 .
  • the resulting structure is shown in Figure 20.
  • the cross sectional view is along the [1 -1 -2] direction.
  • the buffer layer 2 is typically 20 ⁇ m thick and the liftoff layer 4 is typically 50 ⁇ m thick.
  • An etch protect layer 10 of silicon dioxide (SiO 2 ) or other suitable material is deposited and patterned on the surface of the liftoff layer 5 using photolithographic techniques to define elongate strips 11 of exposed substrate 1.
  • the pattern is characterised by staggered arrangements of strips 11 typically 400 ⁇ m long and 10 ⁇ m wide.
  • the strips 11 are oriented along the [1 -1 -2] direction.
  • the lines of strips 11 are typically spaced by 30 ⁇ m.
  • the structure is etched in an anisotropic etchant such as ethylenediamine pyrocatechol (EDP).
  • EDP ethylenediamine pyrocatechol
  • the anisotropic etchant has the characteristics that it etches the silicon (111) planes very slowly compared to other crystal planes, it essentially stops etching at heavily doped p-type layers and it etches the SiO 2 etch protect layer much more slowly than silicon.
  • blind slots 12 with two parallel vertical sidewalls 13 are etched in the liftoff layer 5 where the strips 11 are formed in the masking layer 1.
  • the resulting structure is shown in Figure 22, where the view is along the [1 -1 -2] direction. Slots 12 with two parallel vertical sidewalls 13 have been formed in the liftoff layer 5 to provide etchant access regions to the buffer layer 2.
  • An electro-chemical etchant is used to etch the buffer layer 2, the etchant having the characteristic of attacking p-type silicon but not significantly etching moderately doped n-type silicon. Consequently the buffer layer 2 is etched away to lift off the liftoff layer 5 from the substrate 1. This is schematically illustrated in Figure 23. It will be apparent that the staggered slot configuration is such that the liftoff layer 5 is continuous.
  • An n-type region 14 is created on the surface of a moderately doped p-type (110) oriented silicon substrate 1, by means of a phosphorus diffusion.
  • An etch protect layer 10 of silicon dioxide or other suitable material is deposited on the surface and patterned using photolithographic techniques to produce the staggered pattern of strips 11 shown in Figure 24.
  • the strips 11 are typically 400 ⁇ m long, 10 ⁇ m wide, spaced 20 ⁇ m apart and are oriented along the [1 -1 -2] direction.
  • the upper surface of the structure is similar to that shown in Figure 21.
  • the structure is etched with an anisotropic etchant such as EDP to form slots 12 which partly form etchant access regions.
  • Figure 25 shows the structure following etching, with the slots 12 extending typically 70 ⁇ m deep into the substrate 1.
  • the view is along the [1 -1 -2] direction.
  • Another phosphorus diffusion is made with phosphorus driven into the substrate 1 at a high temperature to produce a moderately doped n-type region 14 typically 2 ⁇ m deep.
  • the second phosphorus diffusion is driven in sufficiently deep that a significant amount of phosphorus penetrates through the etch protect layer and into the underlying substrate silicon, then the first phosphorus diffusion may be omitted.
  • the structure is again etched in an antistrophic etchant such as EDP.
  • etching is continued until the n type region (not shown) at the bottom or blind end 15 of the slots 12 is completely etched through resulting in the structure shown in Figure 26.
  • An electro-chemical etch which attacks p-type silicon but does not significantly etch moderately doped n-type silicon is then used to etch through part (shown at 16) of the substrate 1 as schematically shown in Figure 27.
  • the n doped layer 14 acts as an etch stop during the electrochemical etching. This results in the liftoff of a thin silicon layer 5 as shown in Figure 28.
  • the arrangement of the slots 12 is such that the layer is continuous.
  • Example 12 Oxide dots 3 having a thickness of about 1 ⁇ m are deposited on the surface of an n-type silicon substrate 1 , to act as a masking layer.
  • the dots 3 are typically 30 ⁇ m in diameter and are spaced typically 200 ⁇ m apart.
  • a p-type silicon buffer layer 2 is grown on the substrate 1 in such a way that the buffer layer 2 does not substantially grow over the oxide dots 3. There will be some amount of overgrowth at the edges of the dots 3.
  • the buffer layer 2 is typically 10 ⁇ m thick .
  • a moderately doped n-type silicon liftoff layer 5 typically 50 ⁇ m thick is then grown over the buffer layer 2 as shown in Figures 29 and 30.
  • the structure is etched in hydrofluoric acid to remove the oxide dots 3 and form etchant access regions to the p-type silicon buffer 2.
  • An electro-chemical etch is then used to selectively etch the p-type silicon buffer 2 and liftoff the liftoff layer 5.
  • a typically 10 ⁇ m thick p-type silicon buffer layer 2 followed by a typically 50 ⁇ m thick n-type liftoff layer 5 is grown on an n-type substrate 1.
  • a laser or other suitable cutting device (not shown) is used to form an array of holes 6 through the n-type layer 5 and provide etchant access regions to the buffer layer 2, as shown in Figures 31 and 32.
  • the holes 6 are approximately 50 ⁇ m in diameter and are spaced approximately 200 ⁇ m apart.
  • a selective electro-chemical etch is used to etch the p-type buffer layer 2 and lift off the n-type liftoff layer 5.
  • Example 14 As in example 12, oxide dots 3 having a thickness of about 1 ⁇ m are deposited on the surface of an n-type silicon substrate 1, to act as a masking layer. The dots are typically 30 ⁇ m in diameter and are spaced typically 200 ⁇ m apart. Silicon deposition is carried out by chemical vapour deposition (CVD) single crystal, p-type epitaxial silicon buffer layer 2 is grown on the exposed regions of the substrate at the same time, polycrystalline silicon 16 is deposited on top of the oxide dots 3. The buffer layer 2 is typically 10 ⁇ m thick . A moderately doped n-type silicon liftoff layer 5 typically 50 ⁇ m thick is then grown over the buffer layer 2. The resulting structure is shown in Figure 33.
  • CVD chemical vapour deposition
  • the structure is first etched in an etchant which etches polycrystalline silicon 16 at a much faster rate than single crystalline silicon to form etchant access regions to the buffer layer.
  • etchant is potassium hydroxide (KOH) in the case where the silicon substrate 1 and epitaxial layer 5 are of (111) orientation.
  • KOH potassium hydroxide
  • an electro-chemical etch is used to selectively etch the p-type silicon buffer 2 to liftoff the liftoff layer 5.
  • a masking layer 3 is deposited and patterned on a (100) oriented p type silicon substrate 1 to produce a structure as shown in Figure 4.
  • a p type epitaxial layer 5 is then grown on the substrate to produce a structure as shown in Figure 8.
  • a phosphorus diffusion is made over the entire surface. The diffusion temperature and time, and the thickness of the masking layer 3, are chosen to ensure that no significant amount of phosphorus diffuses through the masking layer 3 and into the underlying silicon of the substrate 1. The phosphorus diffusion results in an n-type layer 17 surrounding the liftoff layer 5.
  • the masking layer 3 is removed in an etchant which does not significantly attack any of the silicon layers to form etchant access regions. The phosphorus can now be driven in deeper into the silicon if required.
  • FIG. 34 The resulting structure is shown in Figure 34.
  • An electro-chemical etch which etches p-type silicon but does not significantly attack n-type silicon is now used to selectively etch the exposed regions of p-type silicon of the substrate until the epitaxial layer has been lifted off.
  • the n-type silicon layer 17 resulting from the phosphorus diffusion acts as an etch stop layer which protects the epitaxial layer during the etching process.
  • a thin silicon film 5, produced in a manner as described in example 1, has been used for the fabrication of a solar cell 18 using standard semiconductor processing techniques.
  • a phosphorus diffusion has been made over the entire top or sunward surface of the film 5, as well as over most of the bottom surface to produce an n-type layer 19.
  • Some regions 20 on the bottom surface have been left undiffused.
  • Electrical contacts 21 are provided to both p-type and n-type silicon regions, these contacts serving to collect photo generated holes and electrons, respectively. Because the n-type regions 19 extend continuously from the front to the rear of the film, electrons which are generated near the top of the n region 19 can readily flow to a contact 21 on the rear of the cell 18. Due to the short distances that carriers have to travel before reaching the metal contacts, series resistance losses can be kept small.

Abstract

Ce procédé de production de films pelliculaires (5) de silicium monocristallin comprend les étapes consistant à former un substrat monocristallin (1), à déposer ou à former un film pelliculaire de silicium monocristallin (5) présentant la même orientation cristalline que celle du substrat, ce dépôt ou cette formation s'effectuant dans le substrat (1), sur celui-ci ou de façon adjacente à celui-ci, puis à préparer une pluralité de régions d'accès pour un agent de gravure, séparées les unes des autres (6), à travers le film (5) ou le substrat (1). L'enlèvement du film (5) s'effectue par gravure simultanée via lesdites régions d'accès (6). La quantité de gravure requise et le degré d'accès de l'agent de gravure permettent d'obtenir un détachement du film (5) sans dégradation importante de celui-ci.
PCT/AU1998/000027 1997-01-21 1998-01-21 Procede de production de films pelliculaires de silicium WO1998032164A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CA 2278174 CA2278174A1 (fr) 1997-01-21 1998-01-21 Procede de production de films pelliculaires de silicium
AU55440/98A AU743826B2 (en) 1997-01-21 1998-01-21 A method of producing thin silicon films
JP53341198A JP2001508947A (ja) 1997-01-21 1998-01-21 シリコン薄膜の製造方法
EP98900480A EP0970514A4 (fr) 1997-01-21 1998-01-21 Procede de production de films pelliculaires de silicium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AUPO4686A AUPO468697A0 (en) 1997-01-21 1997-01-21 A method of producing thin silicon epitaxial films
AUPO4686 1997-01-21

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WO1998032164A1 true WO1998032164A1 (fr) 1998-07-23

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KR (1) KR20000070285A (fr)
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CA (1) CA2278174A1 (fr)
WO (1) WO1998032164A1 (fr)

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WO2003049201A1 (fr) * 2001-12-04 2003-06-12 Origin Energy Solar Pty Ltd Procede permettant de fabriquer de minces feuilles de silicium pour cellules solaires
EP1708254A1 (fr) * 2004-01-15 2006-10-04 Japan Science and Technology Agency Procede de production d'un film mince monocristallin et dispositif a film mince monocristallin
AU2002349175B2 (en) * 2001-12-04 2008-11-06 The Australian National University Method of making thin silicon sheets for solar cells
AU2002342438B2 (en) * 2001-11-29 2009-02-19 The Australian National University Semiconductor texturing process
WO2009104561A1 (fr) * 2008-02-21 2009-08-27 シャープ株式会社 Pile solaire et son procédé de fabrication
US7828983B2 (en) 2001-11-29 2010-11-09 Transform Solar Pty Ltd Semiconductor texturing process
US7910822B1 (en) 2005-10-17 2011-03-22 Solaria Corporation Fabrication process for photovoltaic cell
US7910035B2 (en) 2007-12-12 2011-03-22 Solaria Corporation Method and system for manufacturing integrated molded concentrator photovoltaic device
US7910392B2 (en) 2007-04-02 2011-03-22 Solaria Corporation Method and system for assembling a solar cell package
US8049098B2 (en) 2007-09-05 2011-11-01 Solaria Corporation Notch structure for concentrating module and method of manufacture using photovoltaic strips
US8227688B1 (en) 2005-10-17 2012-07-24 Solaria Corporation Method and resulting structure for assembling photovoltaic regions onto lead frame members for integration on concentrating elements for solar cells
US9583668B2 (en) 2000-11-29 2017-02-28 The Australian National University Semiconductor device

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US8035028B2 (en) * 2006-10-09 2011-10-11 Solexel, Inc. Pyramidal three-dimensional thin-film solar cells
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CN101976657B (zh) * 2009-04-15 2013-10-30 朱慧珑 用于半导体器件制造的基板结构及其制造方法
NL2003390C2 (en) * 2009-08-25 2011-02-28 Stichting Energie Solar cell and method for manufacturing such a solar cell.
USD699176S1 (en) 2011-06-02 2014-02-11 Solaria Corporation Fastener for solar modules
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CN110676205B (zh) * 2019-09-17 2023-01-06 中国电子科技集团公司第十一研究所 芯片的衬底的多次使用方法及红外探测器

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US9583668B2 (en) 2000-11-29 2017-02-28 The Australian National University Semiconductor device
US7828983B2 (en) 2001-11-29 2010-11-09 Transform Solar Pty Ltd Semiconductor texturing process
AU2002342438B2 (en) * 2001-11-29 2009-02-19 The Australian National University Semiconductor texturing process
AU2002342438C1 (en) * 2001-11-29 2009-09-17 The Australian National University Semiconductor texturing process
US7169669B2 (en) 2001-12-04 2007-01-30 Origin Energy Solar Pty. Ltd. Method of making thin silicon sheets for solar cells
AU2002349175B2 (en) * 2001-12-04 2008-11-06 The Australian National University Method of making thin silicon sheets for solar cells
WO2003049201A1 (fr) * 2001-12-04 2003-06-12 Origin Energy Solar Pty Ltd Procede permettant de fabriquer de minces feuilles de silicium pour cellules solaires
EP1708254A4 (fr) * 2004-01-15 2010-11-24 Japan Science & Tech Agency Procede de production d'un film mince monocristallin et dispositif a film mince monocristallin
EP2256786A1 (fr) * 2004-01-15 2010-12-01 Japan Science and Technology Agency Procédé de production d'un film mince monocristallin et dispositif à film mince monocristallin
EP1708254A1 (fr) * 2004-01-15 2006-10-04 Japan Science and Technology Agency Procede de production d'un film mince monocristallin et dispositif a film mince monocristallin
US7910822B1 (en) 2005-10-17 2011-03-22 Solaria Corporation Fabrication process for photovoltaic cell
US8227688B1 (en) 2005-10-17 2012-07-24 Solaria Corporation Method and resulting structure for assembling photovoltaic regions onto lead frame members for integration on concentrating elements for solar cells
US7910392B2 (en) 2007-04-02 2011-03-22 Solaria Corporation Method and system for assembling a solar cell package
US8049098B2 (en) 2007-09-05 2011-11-01 Solaria Corporation Notch structure for concentrating module and method of manufacture using photovoltaic strips
US7910035B2 (en) 2007-12-12 2011-03-22 Solaria Corporation Method and system for manufacturing integrated molded concentrator photovoltaic device
WO2009104561A1 (fr) * 2008-02-21 2009-08-27 シャープ株式会社 Pile solaire et son procédé de fabrication
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EP0970514A1 (fr) 2000-01-12
AUPO468697A0 (en) 1997-02-13
CN1243602A (zh) 2000-02-02
EP0970514A4 (fr) 2000-11-02
KR20000070285A (ko) 2000-11-25
CA2278174A1 (fr) 1998-07-23
AU5544098A (en) 1998-08-07
JP2001508947A (ja) 2001-07-03
AU743826B2 (en) 2002-02-07

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