WO1998027597A1 - Dispositif mos presentant une caracteristique de contact corps/source, destine a etre utilise sur des substrats soi - Google Patents

Dispositif mos presentant une caracteristique de contact corps/source, destine a etre utilise sur des substrats soi Download PDF

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Publication number
WO1998027597A1
WO1998027597A1 PCT/US1997/019259 US9719259W WO9827597A1 WO 1998027597 A1 WO1998027597 A1 WO 1998027597A1 US 9719259 W US9719259 W US 9719259W WO 9827597 A1 WO9827597 A1 WO 9827597A1
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WO
WIPO (PCT)
Prior art keywords
transistor
source
voltage
silicon
gate
Prior art date
Application number
PCT/US1997/019259
Other languages
English (en)
Inventor
Paul S. Fechner
Original Assignee
Honeywell Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc. filed Critical Honeywell Inc.
Publication of WO1998027597A1 publication Critical patent/WO1998027597A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Definitions

  • the present invention relates generally to semiconductors and specifically to metal oxide semiconductors (MOS) formed in silicon on insulator (SOI) substrates.
  • MOS metal oxide semiconductors
  • Integrated circuits formed in SOI wafers are increasingly used for low power and low voltage circuits. Many applications of integrated circuits are requiring lower power supply voltages. While historically it was common to utilize 5 volt supplies, presently there are requirements for 3.3 volt, 2.5 volt and even lower voltage supplies for portions of systems. Future systems are predicted to operate with power supply voltages of less than 1.0 volt. The reasons for this requirement include significantly lower power consumption with the power scaling with the square of the voltage, and the fact that improved performance is obtained when the voltage swing is limited to a lower value. The lower power supply voltages may be required for only a portion of a system.
  • the body tie In partially depleted SOI transistors the body tie needs to be grounded in order to prevent avalanche injection current from creating floating body effects.
  • the most familiar sign of the floating body is a kink in the saturation region of the drain current versus drain voltage characteristic. This kink increase in drain current is due to the reduction of threshold voltage which occurs when the majority carriers, generated at the drain by impact ionization forward bias the body-to-source junction. If a sufficiently high body-to-source forward bias develops, the drain current increases rapidly due to bipolar action and results in premature drain-to-source breakdown or snapback. However if the body can be allowed to float, the threshold voltage reduces, producing more drive from the transistor.
  • Standard MOS transistor theory predicts that a positive bias applied to the body of an NMOS transistor reduces the threshold voltage thus increasing the drive of the transistor for a given gate voltage applied. Fabrication of NMOS devices on SOI makes it practical to do this at the individual transistor level. However, generation and routing of an additional power supply voltage to accomplish this is not practical, and a constant voltage applied to this terminal increases the nominal drain-to-source subthreshold current. Thus a need exists for a transistor device that provides the advantages of reduced threshold voltage while limiting the floating body effects.
  • the present invention solves these and other needs by providing a new device structure which under dynamic conditions reduces the threshold voltage during device turn-on, producing increased drive while controlling the avalanche injection current so as to achieve only a minor loss in snapback voltage.
  • Fig. 1 is a schematic drawing of an n-channel transistor in accordance with the principles of the present invention.
  • Fig. 2 is a top plan view of one layout of the transistor of Fig. 1.
  • Fig. 3 and Fig. 4 are cross-sectional views of the transistor of Fig. 2 along section line 3-3 and 4-4 respectively.
  • Fig. 5 is a schematic of a gate-type circuit utilizing the principles of the present invention.
  • An n-channel transistor 20 having gate 22, source 24. drain 26 and body 28 is shown schematically in Fig. 1.
  • a Schottky diode contact 30 is connected between body 28 and the most negative circuit voltage 32 or Vss. Schottky diode contact 30 includes parasitic schottky resistance 34, diode forward resistance 36 and diode 38.
  • Schottky contact 30 is connected so that it is turned on when a voltage at body 28 exceeds Vss by a few tenths of a volt.
  • FIG. 2 A layout drawing of an n-channel transistor 40 including active area 39 and having gate 42, source 44, source contact 35, drain 46, drain contact 37 and body 48 is shown in Fig. 2.
  • Fig. 3 shows gate oxide 43, channel 50 and body 48.
  • Transistor 40 is formed in a thin silicon layer 41 which is formed on an insulative layer 45 of, for example, buried oxide. Insulative layer 45 is located, for example, on a silicon substrate 47.
  • Various methods of forming silicon on insulator structures are well known and the particular method used is not important to the present invention.
  • Fig. 4 shows silicide 52 connection 54 to underlying P- silicon 56 which is connected to body 48.
  • a schottky contact is formed at 54 by the silicide 52 to low doped P- silicon 56 connection.
  • Source blank feature 33 blocks the normal N+ and NL DD implants from part of the device on the source.
  • Typical P-well concentrations in the low 10 /cm3 provide a reasonable leaky schottky characteristic with the reverse bias leakage resistance 34 being adjustable via an increase in surface dopant level via implantation if desired.
  • the use of the present invention can be illustrated with reference to a gate type circuit 58 including n-channel transistor 20, schottky contact 30 and p-channel transistor 60 having input 57 and output 59 as shown in Fig. 5.
  • P-channel transistor 60 includes gate 62, source 64, drain 66 and body 68.
  • a schottky diode 70 is connected between body 68 and the most positive circuit voltage 72 which is typically Vdd.
  • Diode 70 includes parasitic schottky resistance 74, diode forward resistance 76 and diode 78. Diode 70 is connected so that it is turned on when voltage at 72 exceeds voltage at 68 by a few tenths of a volt.
  • n-channel transistor 60 when input 57 is low, p-channel transistor 60 is on and n- channel transistor 20 is off so that output 59 is high.
  • the gate 22 of n-channel transistor 20 changes from 0V to Vdd the gate potential (Vg) is capacitively coupled to the body of the transistor through the gate to body capacitance Cgb.
  • the body potential, Vb will float high along with the gate potential, effectively reducing the threshold voltage of transistor 20.
  • Vts the turn-on voltage
  • diode 30 When Vb becomes larger than the turn-on voltage, Vts, of the Schottky diode 30, diode 30 will conduct the current to 32 or Vss, thus fixing Vb at Vts.
  • transistor 20 turns on and functions normally with diode 30 conducting all transient and avalanche injection current to Vss.
  • the drain induced avalanche injection current will become 0 as transistor 20 is turned on and Vb will begin to discharge through the non-ideal resistance 34 in diode 30 and will ultimately discharge back to Vss.
  • the drive current is increased relative to what it would be if body 28 was grounded to Vss and thereby improves the gate switching speed of gate 58.
  • While transistor 20 is turning on the gate to body capacitance is negligible until Vb becomes equal to Vts or Vg is greater than Vt (Vb Vts), thus reducing the parasitic charge required to be supplied by the preceding gate which is driving input 57.
  • Schottky diode 30 reduces the gate to body parasitic capacitance during the critical on- off switching times of the transistor. This reduces the dynamic power consumption during switching and requires less overall charge to turn the transistor on and off.
  • Vg input 57 transitions from Vdd to Vss (0.0V), i.e., when transistor 20 is being turned off and transistor 60 is being turned on, two possible conditions exist:
  • this schottky device in series with the Vss connection to the transistor body is to provide a dynamic body bias to reduce the dynamic threshold voltage, Vt, as well as reducing the gate to body dynamic capacitance to a minimal level improving both speed and reducing power consumption.
  • Using the schottky to clamp the body potential to no more than Vts above Vss prevents turn on of the lateral bipolar device controlling snapback problems to a level so that there is only a minor loss only in snapback voltage compared to the arrangement with Vb tied directly to Vss.
  • the present invention provides increased performance and reduction in dynamic power consumption without sacrificing static power capability.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un transistor MOS formé dans une structure de silicium sur isolant et comprenant une connexion de rectification entre une partie corps et la source. La connexion permet de réduire la tension de seuil du transistor et de limiter une différence de tension entre le corps et la source.
PCT/US1997/019259 1996-12-19 1997-10-27 Dispositif mos presentant une caracteristique de contact corps/source, destine a etre utilise sur des substrats soi WO1998027597A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US77075296A 1996-12-19 1996-12-19
US08/770,752 1996-12-19

Publications (1)

Publication Number Publication Date
WO1998027597A1 true WO1998027597A1 (fr) 1998-06-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/019259 WO1998027597A1 (fr) 1996-12-19 1997-10-27 Dispositif mos presentant une caracteristique de contact corps/source, destine a etre utilise sur des substrats soi

Country Status (1)

Country Link
WO (1) WO1998027597A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6271274A (ja) * 1985-09-25 1987-04-01 Nippon Telegr & Teleph Corp <Ntt> Ｍｏｓ形半導体装置
EP0465961A1 (fr) * 1990-07-09 1992-01-15 Sony Corporation Dispositif semi-conducteur sur un substrat isolant diélectrique
EP0469611A1 (fr) * 1990-08-03 1992-02-05 Hitachi, Ltd. Dispositif à semi-conducteur à injection tunnel et son procédé de fabrication

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6271274A (ja) * 1985-09-25 1987-04-01 Nippon Telegr & Teleph Corp <Ntt> Ｍｏｓ形半導体装置
EP0465961A1 (fr) * 1990-07-09 1992-01-15 Sony Corporation Dispositif semi-conducteur sur un substrat isolant diélectrique
EP0469611A1 (fr) * 1990-08-03 1992-02-05 Hitachi, Ltd. Dispositif à semi-conducteur à injection tunnel et son procédé de fabrication

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ASSADERAGHI F ET AL: "A DYNAMIC THRESHOLD VOLTAGE MOSFET (DTMOS) FOR ULTRA-LOW VOLTAGE OPERATION", 22 October 1995, 1995 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN AND CYBERNETICS, VANCOUVER, OCT. 22 - 25, 1995, VOL. 1, PAGE(S) 809 - 812, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, XP000585609 *
MCDAID L J ET AL: "SUPPRESSION OF LATCH IN SOI MOSFETS BY SILICIDATION OF SOURCE", 23 May 1991, ELECTRONICS LETTERS, VOL. 27, NR. 11, PAGE(S) 1003 - 1005, XP000232464 *
PATENT ABSTRACTS OF JAPAN vol. 011, no. 271 (E - 536) 3 September 1987 (1987-09-03) *

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