WO1998006065A1 - Processeur d'images tridimensionnelles - Google Patents

Processeur d'images tridimensionnelles Download PDF

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Publication number
WO1998006065A1
WO1998006065A1 PCT/JP1996/002199 JP9602199W WO9806065A1 WO 1998006065 A1 WO1998006065 A1 WO 1998006065A1 JP 9602199 W JP9602199 W JP 9602199W WO 9806065 A1 WO9806065 A1 WO 9806065A1
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WO
WIPO (PCT)
Prior art keywords
pixel
luminance
pattern
storage device
depth
Prior art date
Application number
PCT/JP1996/002199
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English (en)
Japanese (ja)
Inventor
Masahiro Shiraishi
Takatoshi Ueno
Kazunori Oniki
Original Assignee
Hitachi, Ltd.
Hitachi Process Computer Engineering, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd., Hitachi Process Computer Engineering, Inc. filed Critical Hitachi, Ltd.
Priority to PCT/JP1996/002199 priority Critical patent/WO1998006065A1/fr
Publication of WO1998006065A1 publication Critical patent/WO1998006065A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/10—Geometric effects

Definitions

  • the present invention relates to a three-dimensional image processing apparatus that performs high-quality ghost display by anti-aliasing processing.
  • the anti-aliasing process is performed by shifting the coordinates of the same figure a plurality of times and setting the brightness as the brightness when displaying the average of all the brightnesses.
  • This method requires processing time for the number of times of drawing.
  • a method that draws a figure in units of sub-pixels and uses the luminance to display the average of the luminance of the sub-pixels included in one pixel requires a device to store luminance and depth information for each sub-pixel. There is. For example, dividing one pixel into 4x4 sub-pixels to perform this method would require 16 times as much storage.
  • An object of the present invention is to realize processing equivalent to the above-described antialiasing processing with a short processing time and a small number of storage devices. Disclosure of the invention
  • information such as luminance and depth is stored in units of one pixel. Then, in the unit of sub-pixel, only whether or not it is included in the graphic area to be drawn is stored as an occupation pattern. Then, based on the occupation pattern, the ratio of the region of the foreground figure and the background is calculated, and the luminance of the figure of the foreground and the luminance of the background are blended according to the ratio, so that one drawing is performed. To achieve anti-aliasing.
  • the luminance of a drawing pixel constituting the figure, the depth of the drawing pixel, and the occupation pattern of the drawing pixel are calculated.
  • the depth of the drawing pixel is compared with the depth of the drawing pixel in the total occupied depth storage device, and if the depth of the drawing pixel is deeper, the drawing of the view is drawn. Abort. If the depth of the drawing pixel is nearer or equal, the occupancy pattern of the same coordinates as the drawing pixel in the occupation pattern storage device is compared with the occupancy pattern of the drawing pixel. However, if even some of the graphic areas overlap, it is determined that the foreground pixel that has already been rendered on the pixel of the same coordinates and the pixel of the rendered pixel are not continuous.
  • the luminance of the luminance storage device at the same coordinates as the drawing pixel is compared with the luminance of the drawing pixel. If the occupied patterns are approximate values, the drawing is already performed at the same coordinates. It is determined that the foreground pixel and the drawing pixel are continuous. As a result of the comparison, if the values are not approximate values, the most recently drawn at the same coordinates It is determined that the previous pixel and the pixel of the drawing pixel are not continuous. After determining whether or not the pixel is a continuous pixel as described above, the ratio of the figure area of the occupation pattern of the drawing pixel and the occupation pattern of the occupation pattern storage device having the same coordinates as the drawing pixel is determined. The luminance and the luminance of the luminance storage device having the same coordinates as the drawing pixel are rendered and stored in the frame buffer.
  • the occupation pattern of the occupation pattern storage device and the graphic area of the occupation pattern of the drawing pixel are combined and stored in the occupation pattern storage device. If it is determined that the drawing pixel is not continuous, the drawing force is stored in the occupation pattern storage device if the drawing force is closer to the depth force of the drawing pixel. Pixel Depth Force If the depth of the z-buffer at the same coordinate is farther than the depth, the occupation pattern of the occupation pattern storage device is stored as it is.
  • the occupation pattern of the occupation pattern storage device is used as a blend ratio when drawing a figure with respect to the pixel having the same coordinates later, the occupation pattern to the occupation pattern storage device described above is used. Remembering is a necessary process.
  • an object with a complicated shape is displayed by continuously combining small polygons.
  • a series of multiple polygons Combine, treat as one polygon, and blend in brightness.
  • FIG. 1 is a diagram showing an overall block diagram of hardware of the present embodiment
  • FIG. 2 is a diagram showing an overall flow of hardware of the present embodiment
  • FIG. Fig. 4 shows each image memory.
  • FIG. 5 is a diagram showing a process of a pixel comparison operation unit
  • FIG. 6 is a diagram showing a block diagram of a luminance approximate value determination
  • FIG. 8 is a diagram showing a selection of a process of the ghost information calculation unit.
  • FIG. 8 is a diagram showing a detailed flow of the pixel comparison calculation unit.
  • FIG. 9 is a calculation procedure of an occupation pattern in the pixel information calculation unit.
  • FIG. 10 is a diagram illustrating the role of the total occupied depth storage device, FIG.
  • FIG. 11 is a diagram illustrating determination of continuous pixels based on the occupation pattern
  • FIG. 12 is a diagram illustrating FIG. 13 is a diagram illustrating an example of a luminance calculation process.
  • FIG. 13 is a diagram illustrating another example of a luminance calculation process.
  • FIG. 14 is a diagram illustrating an example of obtaining an occupation pattern.
  • FIG. 15 is a diagram showing an example of erroneously determining a continuous pixel.
  • FIG. 1 is an overall block diagram of the hardware according to the present invention
  • FIG. 2 is a flowchart showing an outline of the processing in the hardware.
  • This hardware consists of a central processing unit (100) connected to the system bus (100), a rendering processor (200), and a display for displaying the processing results of the rendering processor (200). It consists of control means (400) and CRT (500).
  • the rendering processor (200) is connected to an image memory (300) for storing the processing results and intermediate processing results, and the display control means is stored in this image memory. The processing result is displayed on the CRT (500).
  • the vertex coordinates, vertex luminance, and vertex depth of the three-dimensional figure to be rendered are calculated by a central processing unit (100) having a CPU and a memory, and issued to a rendering processor via a system bus ( 1) and the rendering processor
  • a central processing unit (100) having a CPU and a memory
  • the rendering processor issues the pixel information calculation unit (2100) of (200)
  • the pixel comparison operation unit (220) of the rendering processor (200) the luminance to be displayed is calculated from the calculated pixel information.
  • a ghost image memory (300) is used, and the calculated brightness is stored in the image memory (300).
  • the luminance information stored in the frame buffer (310) in the image memory (300) is displayed on the CRT (500) by the display control means (400) (4).
  • FIG. 3 shows the configuration of the image memory (300), and FIG. 4 shows the role of each memory.
  • the image memory (300) stores a frame buffer (311) in which the averaged luminance (311) of the pixel (31) viewed from the viewpoint direction (30) is displayed for display on the CRT. 3 10 0), Z buffer (3 2 0) that records the depth of the nearest pixel (3 2 1), and the occupancy pattern of the nearest pixel
  • An occupancy pattern storage device (340) that stores (331), a brightness storage device (340) that stores the brightness (334) of the foremost pixel, and a figure of the occupation pattern It consists of an occupied depth storage device ('350) which stores the depth (351) of the foremost pixel such that the area is 100%.
  • each memory corresponding to one pixel is as follows: the frame buffer (310) has 24 bits, the Z buffer (320) has 24 bits, and the occupied pattern storage device (330) has 1 bit.
  • the 6-bit luminance storage device (340) has 24 bits, and the total occupied depth storage device (350) has 24 bits.
  • the occupation pattern storage device (330) stores information of 16 sub-pixels included in one pixel as an occupation pattern of 16 bits.
  • the memory configuration is about 2.3 times as large as that of the frame buffer (310) and the Z buffer (320) only when the anti-aliasing process is performed. To achieve.
  • the detailed block diagrams of the rendering processor (200) are shown in Figs. 5, 6, and 7, and the detailed flow is shown in Fig. 8.
  • the occupancy pattern of the image information calculation unit (210) is shown in Figs. Fig. 9 shows the processing in the calculation unit.
  • the CPU (100) issues the vertex coordinates, vertex depth, and IS point luminance of the figure (triangle in this embodiment) from the CPU (100), and the hardware of the rendering processor (200) executes the operation.
  • the screen information calculation unit (210) receives these vertex information.
  • the rendering processor (200) calculates the coordinates of the pixels constituting the figure, the luminance of the drawing pixels, A pixel information calculation unit for calculating the depth of the drawing pixel and the occupation pattern of the drawing pixel in the sub-pixel
  • a pixel comparison operation unit (220) for calculating information to be stored in the image memory (300) from the pixel information.
  • the pixel information calculation unit (210) supplements the X value between vertices in the Y coordinate direction in quarter pixel units based on the received vertex information. Calculate the frame of the area (41). Next, the subpixel whose center point is equal to or greater than the left frame and less than the right frame is set to “0”, and if not included, is set to “1” (42). After calculating the values of all the sub-pixels in one pixel constituting the figure, the value is transferred to the pixel comparison operation unit (220) as a 16-bit occupation pattern (43). At the same time, the luminance of the pixel at the same coordinate and the depth of the pixel at the same coordinate are transferred to the pixel comparison operation unit (2220). In the following, unless otherwise specified, the information of each memory in the image memory (300) is the information of the memory having the same coordinates as the drawing pixel.
  • the pixel comparison operation unit (220) first stores the depth Z (33) of the picture pixel (35) and the total occupied depth storage device (350). ) Is compared with the depth AB (3 5 2) (2 2 1).
  • the drawing pixel (35) is deeper (when CO becomes 0)
  • the state of the pixel (36) viewed from the viewpoint direction (32) is changed to the pixel (34) in front.
  • the drawing pixel (35) is hidden and invisible. Therefore, the information of the frame buffer (310) needs to be updated, and the drawing of the pixel is stopped (17). If the drawing pixel (35) is closer or equal in depth (when CO becomes 1), then the occupation pattern P of the drawing pixel and the occupation pattern storage device (330) are stored. A logical sum (P
  • the result (56) of the bit-wise OR of the occupation pattern (54) of (53) and the occupation pattern (55) of the pixel (53) in the figure (52) is (56) in which all bits are '1'.
  • the pixel (59) overlapping the figure (57) and the figure (58) is the occupied pattern (60) of the pixel (59) in the figure (57) and the figure (58).
  • the result (62) of the bit-wise OR of the pixel (59) with the occupation pattern (61) of the pixel (59) at the point becomes the bit power '' 0 'of the overlapped portion.
  • the occupation pattern of the drawing pixel by calculating the bit-wise logical OR, the occupation pattern of the drawing pixel and the It is possible to determine whether or not the graphic area portion overlaps with the occupation pattern stored in the occupation pattern storage device (330).
  • the brightness I of the drawing pixel is compared with the brightness IB of the brightness storage device (340) (223), and it is determined whether or not these values are approximate values. Is determined.
  • IT is performed using a threshold value preset in a threshold value register (230) as shown in FIG.
  • the R, G, and B components of the luminance of the picture pixel are Rl, GI, and BI, respectively, and the R, G, and B components of the luminance of the luminance storage device (340) are RIB, GIB, BIB.
  • the absolute value of the difference from the luminance of (340) is calculated as R S, G S, and B S for each RGB component (227). Then, the threshold value R preset in the threshold value register (230) is compared with the absolute value of the difference for each of the RGB components (228). If all of R S, G S, and B S are smaller than the threshold value R, it is determined to be an approximate value. If at least one of R S, G S, and B S is larger than the threshold value R, it is determined that the value is not an approximate value.
  • the value set in the threshold register (230) sets the upper limit of the absolute value of the difference in luminance considered as an approximate value.
  • about 30% of the maximum luminance value of the frame buffer (310) is set as the upper limit of the luminance difference that is regarded as an approximate value. That is, since each component of the luminance of the frame buffer (310) is 8 bits and the maximum luminance is 255, the threshold value is set to 76.
  • the bit unit is If the result of the logical product (P & SB) (2 25) is all '0' for all 16 bits (C 4 is 1), the pixel information calculation unit (2 26) The processing corresponding to (10) in Fig. 7 and Fig. 8 (the following processing (8) (() (0) () ( ⁇ )) is performed, and the result of bitwise logical AND (225) If all of the 16 bits are not '0', the pixel information calculation unit (226) performs the processing corresponding to (11) in FIGS. 7 and 8 (the following processing (A)). (C) (D) (F)).
  • the result of the depth comparison (2 2 4) indicates that the drawing pixel is at the depth (when C3 is 0)
  • the result of the bit-wise logical AND (2 25) will be all 16 bits If '0' (C4 becomes 1), the pixel information calculation unit
  • drawing has already been performed It is determined that the foreground pixel and the pixel to be rendered are not continuous.
  • the depth of the drawing pixel is compared with the Z buffer (320) (224), followed by the occupation pattern P of the drawing pixel and the occupancy of the occupation pattern storage device (330). Performs a bit-wise AND operation with the pattern (SB) (225).
  • the pixel information calculation unit (2 26) performs processing corresponding to (14) in FIGS. 7 and 8 (the following processing (A) (C) (E) (F) (G) ), And if the result of the bit-wise logical AND (2 25) is not all “0” for both 16 bits, the pixel information calculation unit (2 26) performs the operations shown in FIGS. The processing corresponding to (15) in the figure (the following processing (A) (C) (E) (F)) is performed.
  • the depth comparison (2 24) if the drawing pixel is located at the depth, the pixel information calculation unit (2 26) performs processing corresponding to (15) in FIG. 7 and FIG. The following processing (B)) is performed.
  • each memory in the image memory (300) that has not been updated stores the information before drawing the drawing pixel as it is.
  • the occupation pattern of the drawing pixel is “P”
  • the occupation pattern stored in the occupation pattern storage device (330) is “P”. Expressed as 'SB'.
  • Ra2 Percentage of '0' in (SBI 1 ⁇ ⁇ ⁇ (?))
  • Ra3 1.0-Ral ⁇ Ra2
  • the outline of the process (A) will be described with reference to the example of FIG.
  • the processing (A) is performed when the depth (75) of the drawing pixel is closer to or equal to the depth (32) read out from the Z buffer (320). ) Is a process of calculating the luminance to be stored.
  • the regions (71), (72), and (73) in a subpixel of a certain pixel viewed from the viewpoint direction (70) are weighted by the ratio of occupying the subpixel by each luminance and averaged.
  • the area (71) viewed from the line-of-sight direction (70) occupies 9Z16, which is the ratio of '0' in the pattern (76) occupied by the drawing pixel, due to the luminance (74) of the drawing pixel. ing.
  • the area (72) viewed from the line-of-sight direction (70) is read from the occupancy pattern storage device (330) by the brightness (333) read from the brightness storage device (340).
  • Occupancy pattern (3 4 3) Occupies 3 16 which is the proportion of '0' in INOT (occupation pattern (76) of drawing pixels) 76.
  • the brightness of the frame buffer (310) is calculated by averaging the brightness of the area (73) when the pixel was previously drawn, using the brightness of the area (73).
  • the brightness of the original region (73) can be reflected to some extent.
  • the area (81) viewed from the line-of-sight direction (80) is determined by the drawing pixel luminance (84) (drawing pixel occupation pattern (86) [NOT (read from occupation pattern storage device (330)).
  • the occupation pattern (3 4 4)) occupies 5 to 16 which is the ratio of '0'.
  • the area (8 2) viewed from the line of sight (80) is the luminance storage device (3 4 0).
  • the luminance of the frame buffer (310) is averaged using the luminance of the area (83) when the pixel was previously drawn, the luminance of the frame buffer (310) is calculated as follows. By setting the brightness of the area (83), the brightness of the original area (83) can be reflected to some extent. Processing (C)
  • the processing (C) stores and updates the depth of the drawing pixel in the Z buffer (320) when the depth of the drawing pixel is closer or equal to the depth read from the Z buffer (320). It is processing.
  • Occupancy pattern storage device (330) P & S B
  • the process (D) is a process of synthesizing an occupation pattern and storing the occupation pattern in the occupation pattern storage device (330) when it is determined that the drawing pixel and the foremost pixel that has been previously drawn are continuous. is there.
  • the occupation pattern (91) of the drawing pixel and the occupation pattern (92) read from the occupation pattern storage device (330) are bit-wise ANDed with each other to perform the logical AND operation.
  • This is a process of synthesizing the graphic area (area of '0') (93) and storing it as a graphic area of one pixel in the occupation pattern storage device (330).
  • the drawing pixel is connected to the foremost pixel that has been previously drawn. Occupied pattern storage device (330) when it is determined that the connection is not continuous and the depth of the drawing pixel is closer to or equal to the depth of the Z buffer (320). This is a process of storing a pattern. Processing (F)
  • the processing (F) stores the brightness of the drawing m in the luminance storage device (340) when the depth of the drawing pixel is closer or equal to the depth of the Z buffer (320). This is the process to do.
  • the occupation pattern storage device (330) is updated by the process (D) or the process (E), and the occupation pattern (P) of the drawing pixel and the occupation pattern storage device (330) are updated.
  • the bit-wise AND with the occupation pattern (SB) read from) is 16 bits, the total occupied depth storage device (35%) becomes “0” (100% of the pixel graphic area). 0) is a process of storing the depth of the drawing element.
  • Fig. 13 if the depth of the pixel (85) to be drawn is the second closest to the front of the depth of the previously drawn pixel, the ideal brightness is If it is the third or later from the front, that is, the pixel to be drawn (85) and the foremost pixel that has been previously drawn If there is another pixel that has been previously drawn between the depths of (3 2 4), the result will be different from the ideal luminance.
  • the occupation pattern (64) of the drawing pixel and the occupation pattern storage device Since the result (66) of the bitwise OR of the occupation pattern (65) of (330) is all '1', the pixel is erroneously determined to be continuous. Also, if the luminance is not an approximate value while two M elements are adjacent, it is erroneously determined that the pixels are not continuous. As described above, if the determination as to whether or not they are continuous is incorrect, the determination as to whether or not to combine the graphic area of the occupied pattern is also erroneously made, resulting in the occupation of the wrong occupied pattern.
  • the pattern storage device (330) It is stored in the pattern storage device (330). Therefore, when the pixel is drawn later at the same coordinates, the luminance is calculated from the ratio of '0' of the wrong occupation pattern, so that the luminance power of the frame buffer (310) does not become the ideal luminance. There are cases. In particular, when the depth of the drawing pixel is deeper than the depth of the Z buffer (320), the occupied pattern of the occupied pattern storage device (330) is located at the foreground. Since the ratio of the occupation pattern of the occupation pattern storage device to be seen is likely to be large, the ratio of the occupation pattern is greatly involved in calculating the luminance.
  • the anti-aliasing process is performed by one drawing by performing the brightness calculation using the foreground occupation pattern held in one element unit, so that the conventional method is used. It is faster to draw and is suitable for performing anti-aliasing with less memory.

Abstract

Processeur d'images tridimensionnelles effectuant une opération d'anticrénelage avec une capacité limitée de mémoire en une courte durée. Ce processeur d'images comporte une mémoire d'images (300) comprenant une zone de mémorisation (330) dans laquelle sont mémorisées des configurations d'occupation, une zone de mémorisation de luminance (340) dans laquelle est mémorisée la luminance du premier élément d'image, une zone de mémorisation (350) de profondeur d'occupation totale dans laquelle est mémorisée la profondeur du premier élément d'image dont la configuration d'occupation est de 100 %, un tampon d'images dans lequel est mémorisé l'information concernant ces éléments d'image individuels, ainsi qu'un tampon Z (320), une section de calcul (210) d'information d'élément d'image, qui calcule les configurations d'occupation dans des unités d'un élément d'image, et une section (220) de calcul et de comparaison d'éléments d'image, qui calcule l'information à mémoriser dans la mémoire (300). Etant donné que ce processeur d'images effectue l'anticrénelage à vitesse élevée pour une image, ceci permet de supprimer une augmentation de la capacité de la mémoire et, par conséquent, de limiter les coûts de ce processeur.
PCT/JP1996/002199 1996-08-05 1996-08-05 Processeur d'images tridimensionnelles WO1998006065A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11345218A (ja) * 1998-04-03 1999-12-14 Sony Corp 画像処理装置およびその方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63113785A (ja) * 1986-10-31 1988-05-18 Hitachi Ltd 図形表示方法
JPH04343185A (ja) * 1990-10-30 1992-11-30 Sun Microsyst Inc 図形画像を生成する装置及び方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63113785A (ja) * 1986-10-31 1988-05-18 Hitachi Ltd 図形表示方法
JPH04343185A (ja) * 1990-10-30 1992-11-30 Sun Microsyst Inc 図形画像を生成する装置及び方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NIKKEI CG, January 1988, TOSHIAKI KATO, "Method for Eliminating Aliasing Used for High-Quality Image Generation", p. 138-142. *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11345218A (ja) * 1998-04-03 1999-12-14 Sony Corp 画像処理装置およびその方法
JP4505866B2 (ja) * 1998-04-03 2010-07-21 ソニー株式会社 画像処理装置および映像信号処理方法

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