Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/69—Spread spectrum techniques
  • H04B1/707—Spread spectrum techniques using direct sequence modulation
  • H04B1/7097—Interference-related aspects
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
  • H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
  • H04L25/03834—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using pulse shaping
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
  • H04L27/20—Modulator circuits; Transmitter circuits
  • H04L27/2003—Modulator circuits; Transmitter circuits for continuous phase modulation
  • H04L27/2007—Modulator circuits; Transmitter circuits for continuous phase modulation in which the phase change within each symbol period is constrained
  • H04L27/2017—Modulator circuits; Transmitter circuits for continuous phase modulation in which the phase change within each symbol period is constrained in which the phase changes are non-linear, e.g. generalized and Gaussian minimum shift keying, tamed frequency modulation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
  • H04L27/20—Modulator circuits; Transmitter circuits
  • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
  • H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
  • H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers
  • H04L27/2064—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers using microwave technology
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D30/00—Reducing energy consumption in communication networks
  • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

• the invention relates to methods and apparatuses for the realization of spectral containment of radio transmissions so that they do not cause adjacent channel interference and, in particular, for the realization of spectral containment of high bitrate digital transmissions such as TDMA or CDMA cellular telephone signals.
• the GSM TDMA system codes speech using convoiutional coding and transmits the coded speech using one or two out of 16 timeslots depending on whether a half-rate or a full-rate channel is allocated.
• An IS-54 system also convolutionally codes speech and then transmits it using one or two out of six timeslots.
• An IS-95 system uses convoiutional coding plus bit repetition and transmits the speech using 2, 4, 8 or 16 out of 16 timeslots depending on whether the speech sound is a voiced sound, non-voiced sound or silence/background noise. In all cases therefore, the bitrate of speech is first compressed to remove natural redundance and then the bitrate is increased by using intelligent coding to obtain a higher bitrate stream for transmission that is more tolerant of interference.
• a transmitter for such digitally coded signals preferably comprises a balanced quadrature modulator.
• Figure 1 illustrates a prior art arrangement of a quadrature modulator for synthesizing an arbitrarily modulated signal.
• a digital signal processor (DSP) 30 calculates time-spaced samples of the real and imaginary parts of a desired complex modulation. The real part is given by the desired amplitude times the cosine of the desired phase angle, while the imaginary part is given by the amplitude times the sine of the phase angle. In this way both Amplitude Modulated (AM) signals or Phase Modulated (PM) signals can be generated, or signals comprising both, the result of which is generally known as complex modulated signals.
• AM Amplitude Modulated
• PM Phase Modulated
• the numerical samples calculated by the DSP 30 are transferred to a pair of Digital-to-Analog (D-to-A) convertors 31 that convert each numerical sample pair into a pair of analog voltages known as I (In-phase) and Q (Quadrature) signals.
• D-to-A Digital-to-Analog
• a sequence of such numerical samples generates I and Q waveforms but in a stepwise fashion.
• I and Q smoothing filters 32 are necessary. These are low-pass filters that pass all modulation spectral components of interest but suppress the higher frequency components of the spectrum associated with the stepwise or piecewise linear I,Q waveforms from the D-to-A converters 31.
• the smoothed I,Q waveforms are applied to a pair of balanced modulators 33 together with cosine and sine carrier frequency signals, this arrangement being known as a quadrature modulator.
• This arrangement being known as a quadrature modulator.
• the arrangement described so far and illustrated in Figure 1 belongs to the well-known prior art.
• the DSP 30 produces numerical I and Q waveforms representative of the desired digital or analog modulation and then D-to-A convertors 31 convert the numerical I,Q representations to analog I,Q modulating waveforms.
• Filters 32 remove discontinuities due to the finite time sampling and quantization of the numerical I,Q signals to produce continuous I,Q waveforms, thus avoiding spectral splatter into adjacent radio channels.
• the smoothed I,Q waveforms are applied to sine and cosine radio frequency-carriers using quadrature modulator 33.
• the levels of the I and Q signals are accurately controlled relative to each other, and (3) the balanced modulators have low carrier leakage or offset, that is, the output signal of a balanced modulator should be zero when its respective I or Q modulating signal is zero.
• the zero point of an I or Q waveform cannot be defined to be zero voltage, but must be defined to be some positive reference voltage such as half the supply voltage. Then when an I or Q waveform swings below this reference voltage it will be interpreted as negative, and positive when it swings above.
• the balanced mixers 43 are therefor provided with balanced, two-wire inputs rather than single-ended inputs, that are responsive to the difference in the signals on the two wires and unresponsive to the absolute or common-mode voltage (sum of the voltages) on the two wires.
• High bitrate delta-sigma modulation bitstreams are simply converted to the analog voltage they represent by forming the moving average voltage over a large number of bits. This may be done using a continuous-time, low-pass filter having a bandwidth which is a small fraction of the bitrate, but still sufficient to pass all desired modulation components.
• balanced filters 44 are interposed between the delta-sigma convertor outputs and the I,Q balanced modulators 43.
• delta-sigma convertors 41 convert the numerical sample values from DSP 30 to high bitrate streams wherein instantaneous waveform values are represented by the proportion of ones to zeros in the bitstrea , i.e., by the average mark/space ratio.
• the inverters 42 form complementary bitstreams such that the difference in mark space ratio forms a balanced signal that can more easily represent both positive and negative instantaneous waveform values.
• the ' high bitrate fluctuations are removed by balanced filters 44 to obtain continuous, smoothed I,Q waveforms which are applied to balanced inputs of quadrature modulator 43, as disclosed in U.S. Patent Application No. 08/305,702, which is a continuation-in-part of U.S. Patent Application No. 07/967,027 which is also incorporated herein by reference.
• the parent applications disclose the advantages of using balanced I,Q signals representing a complex modulating signal waveform by means of high bitrate sigma-delta modulation streams and their complements.
• a signal to be transmitted is formed initially as a pair of complex baseband signals comprising an I-signal and a Q-signal.
• the I and Q signals can be represented by high bitrate sigma-delta modulation in which each bit is either a zero or a one.
• An I stream, a Q stream and their complements are preferably used to form a balanced I signal and a balanced Q signal each on a pair of wires.
• a CDMA signal can likewise be represented by a stream of high bitrate I-chips and a stream of high bitrate Q-chips, and their complements.
• the CDMA I and Q signals may furthermore be sampled at a multiple of, e.g., four times, the chiprate giving four bits per chip of balanced I and balanced Q signals.
• the balanced I and Q signals are delayed in a chain of shift register stages clocked at at least the bitrate to produce delayed balanced I,Q signals at respective q and q outputs of each of the shift register stages.
• a first resistor network comprising resistors of different values representing transversal filter weights is connected to the I outputs of the shift register, the q outputs being used for a positive weight and the q outputs for a negative weight.
• Each shift register output connects to one end of a respective weighting resistor while the other resistor ends are summed to provide a first filtered output.
• a second identical resistor network connects to the q and q outputs not used by the first network to provide a complementary output.
• Identical first and second resistor networks are likewise connected to the q and q outputs of the Q shift register to provide complementary filtered Q outputs.
• the balanced I and Q filtered outputs can be further connected to a balanced resistor-capacitor filter to remove unwanted high-frequency components.
• the RC- filtered balanced signals are then connected to an I,Q modulator (quadrature modulator) to modulate a radio frequency signal such that unwanted emissions in adjacent channels are reduced.
• the inventive balanced I,Q transversal filter may be constructed entirely on a semiconductor substrate as an integrated circuit.
• the desired filtering function is determined by resistor ratios and not absolute values making it suitable for production in processes where absolute resistor values are not able to be tightly controlled but resistor ratios are determined by geometry and thus are more tightly controlled.
• Figure 1 is a schematic diagram of a conventional art I,Q modulator circuit
• Figure 2 is a schematic diagram of an inventive I,Q modulator circuit as disclosed herein and in parent application Serial Number 08/305,702;
• Figure 3 is a schematic diagram of an I,Q filtering circuit in accordance with the present invention
• Figure 4 is a schematic diagram of an I,Q filtering circuit in accordance with the present invention as applied to CDMA transmission.
• Figure 3 shows an inventive alternative to the combination of the inverters 42 and the balanced filters 44 of Figure 2 for realizing a balanced filter.
• An I bitstream or a Q bitstream from delta-sigma convertors 41 is applied to a filter 30 constructed broadly according to Figure 3, i.e., there is one filter 30 for each of the I and Q bitstreams.
• the I or Q bitstream enters a shift register 50 which is in the form of a chain of shift register stages (50,, 50 2 , ... 50 N ) each comprising a flip-flop (51,, 51 3 , ... 51 N ) having q and q complementary outputs.
• a resistor network 60 consisting of a group of resistors (60,, 60 3 ...
• An identical set of resistors 80 connects to the flip flop q- outputs where the first network connects to the q outputs and vice-versa, such that the waveform produced at the summer 90 or summing junction 91 of the second resistor network 80 is complementary to the first waveform at the summer 70 or summing junction 71 of the first resistor network 60.
• a 13MHz reference clock is used as the reference for all bitrates and frequencies.
• the transmitted bitrate is 13MHz/48.
• 13MHz as the delta-sigma bitrate output from delta-sigma convertors 41 means that 48 delta-sigma bit outputs will occur per transmitted bit period.
• Shift register 50 can thus conveniently be 48 bits long and the resistors 60,-60 4S ("N" in this instance being equal to 48) chosen to obtain a desired impulse response with a duration of one bit period. This impulse response corresponds to a frequency response bandwidth of the order of the bitrate or a few times the bitrate.
• the delta-sigma convertor 31 can comprise a Read Only Memory (ROM) containing 8 precomputed 48-bit patterns of I and Q waveforms corresponding to all possible patterns of three consecutive information bits.
• ROM Read Only Memory
• I,Q waveforms can be created for digital transmitters by means of such a ROM modulator, which relies on being able to truncate the impulse response of the premodulation filter to a reasonable number of bit periods M, where 2 M gives a ROM of a reasonable size.
• the filter can produce, over each bit interval, one of a finite number, 2 M , of possible waveforms.
• the modulation and filtering is achieved simply by feeding the data stream through an M-bit shift register (not shown) which addresses the ROM to output waveforms for that bit interval.
• Each waveform then has an impulse response length which can be up to three information bit periods long, as compared to the one bit period of the filter of Figure 3 with 48 stages.
• the sharpness of cut-off of a filter response in the frequency domain increases in proportion to the lengths of its impulse response in the time domain. Thus, a long impulse response is desirable to obtain a sharp filtering effect in the frequency domain. Desirable impulse responses are generally several information symbols in length, e.g., 3 symbol periods.
• the sharpness of cut-off is determined by the number of symbols of each waveform stored in the ROM modulator depends on, while attenuation of components further away from the cut-off point depends on the filtering applied to these delta- sigma waveforms after they emerge from the ROM modulator.
• the filter of Figure 3 may also be used for generating a filtered, CDMA coded signal, as shown in Figure 4.
• the DSP 30 supplies convolutionally-coded and interleaved information bits to convertors 41, which are now CDMA code-spreaders 95 instead of the delta-sigma convertors. For example, if the CDMA spreading spreads each coded bit from DSP 30 by a factor of 64, the output chip rate from spreaders 95 will be 64 times the coded information rate, giving in the case of CDMA standard IS- 95 a chiprate of 1.2288 Megabits/sec. This chip stream can be used as an input for the filter of Figure 3.
• the chip stream may be further sampled at four samples per chip to obtain a rate of 4.9152 Megabits/sec which is clocked into a shift register 50 of, for example, 48 stages.
• the total impulse response length of 48 1/4-chips or 12 chips is adequate to allow, by proper choice of weighting resistors 60,-60 N , good spectral containment of transmissions.
• Figure 4 illustrates the application of the present invention to a CDMA system in which the DSP 30 codes analog speech into digital form or accepts digital data signals already in digital form and applies error correction coding.
• the coded speech and data are then converted to I,Q signals representing the vector components of a modulated signal which are further spread-spectrum coded by the code spreading unit 95 to obtain high bitrate I and Q chipstreams.
• the I,Q chipstreams are clocked through shift register stages 50a, 50b at a multiple of (for example, four times) the chiprate and the inverted q or non-inverted q outputs of the shift registers are applied to resistor networks 60a, 60b with the inverse being applied to other resistor networks 80a, 80b.
• the first resistor networks 60a, 80a generate antiphase I-signals forming a balanced signal input to a first balanced RC filter 32a and second resistor networks 60b, 80b form balanced Q- signal outputs to a second balanced RC filter 32b.
• Filters 32a, 32b have only to remove unwanted spectral components above the sampling frequency (of four times the chiprate) and can be integrated RC filters, the main filter frequency response in the vicinity of the chiprate having been accurately determined by the resistor ratios within weighting networks 60a, 60b, 80a, 80b.
• the filtered, balanced I,Q drive signals from filters 32a, 32b are then applied to the balanced inputs of quadrature modulator 43.
• the inventive balanced quadrature modulator may be used advantageously to generate CDMA signals for transmission that have been accurately filtered by balanced transversal filters using resistive weights.
• the weighting values of a transversal filter should follow the coefficients of an inverse Fourier Transform of the desired frequency response. Accordingly, the resistor values 60,, 60 2 ...60 N should be inversely proportional to the Fourier transform of the desired frequency response. This is also equivalent to choosing the weighting resistor values to be inversely proportional to samples on the desired filter impulse response.
• the invention of Figures 3 and 4 is amenable to integration in the form of a semiconductor (e.g. , silicon) chip.
• Semiconductor chip processes have various means for forming resistors.
• the resistors should be of high value; high value resistors may be fabricated in a CMOS process for example as long, N-type FETs that are biassed to the ON condition by connecting their gates to the positive supply. The resistor values are proportional then to the total gate length.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Physics & Mathematics (AREA)
• Power Engineering (AREA)
• Nonlinear Science (AREA)
• Spectroscopy & Molecular Physics (AREA)
• Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
• Compression, Expansion, Code Conversion, And Decoders (AREA)

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• 1997
  • 1997-03-13 CA CA002250330A patent/CA2250330C/en not_active Expired - Fee Related
  • 1997-03-13 EP EP97914988A patent/EP0888681B1/en not_active Expired - Lifetime
  • 1997-03-13 KR KR10-1998-0707474A patent/KR100462139B1/ko not_active IP Right Cessation
  • 1997-03-13 JP JP53352997A patent/JP3758681B2/ja not_active Expired - Fee Related
  • 1997-03-13 AU AU22046/97A patent/AU712678B2/en not_active Ceased
  • 1997-03-13 DE DE69722390T patent/DE69722390T2/de not_active Expired - Lifetime
  • 1997-03-13 CN CNB971948011A patent/CN1147098C/zh not_active Expired - Fee Related
  • 1997-03-13 WO PCT/US1997/003803 patent/WO1997035411A1/en active IP Right Grant
  • 1997-03-14 TW TW086103205A patent/TW317680B/zh not_active IP Right Cessation
  • 1997-03-20 CO CO97015007A patent/CO4600652A1/es unknown
  • 1997-03-20 AR ARP970101109A patent/AR006980A1/es unknown
  • 1997-03-20 ID IDP970911A patent/ID16560A/id unknown

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