WO1997027621A1 - Procede de rognage a attaque selective pour la fabrication de plaquettes du type semi-conducteur-sur-isolant - Google Patents

Procede de rognage a attaque selective pour la fabrication de plaquettes du type semi-conducteur-sur-isolant Download PDF

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Publication number
WO1997027621A1
WO1997027621A1 PCT/US1997/000991 US9700991W WO9727621A1 WO 1997027621 A1 WO1997027621 A1 WO 1997027621A1 US 9700991 W US9700991 W US 9700991W WO 9727621 A1 WO9727621 A1 WO 9727621A1
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Prior art keywords
layer
semiconductor layer
semiconductor
masking
masking layer
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PCT/US1997/000991
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English (en)
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WO1997027621A9 (fr
Inventor
Robert A. Craven
David Dimilia
Subramanian S. Iyer
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Sibond, L.L.C.
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Publication of WO1997027621A1 publication Critical patent/WO1997027621A1/fr
Publication of WO1997027621A9 publication Critical patent/WO1997027621A9/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Definitions

  • the present invention generally relates to the manufacture of semiconductor-on-insulator wafers, and specifically, to a process for trimming the peripheral edge of such wafers.
  • the invention also relates to semiconductor-on-insulator wafers having an edge-trimmed semiconductor layer.
  • SOI wafers typically comprise, in succession, a handle or substrate layer, an insulating layer, and a semiconductor layer. Such wafers are manufactured by several techniques known in the art, including primarily implanted oxygen (SIMOX) methods and direct bonding methods.
  • SIMOX implanted oxygen
  • Japanese Kokoku Patent No. 62- 34716 discloses another method involving localized growth of the semiconductor layer from a single crystal projection extended through the oxide layer.
  • the peripheral edges of semiconductor-on-insulator wafers are trimmed to make them cosmetically acceptable and functionally compatible with subsequent integrated circuit fabrication steps. Edge trimming is particularly important for bonded semiconductor-on-insulator wafers that have lamination defects near their peripheral edge, as such defects can cause the edge to flake and become jagged.
  • Particles from flaking edges can break off during subsequent fabrication steps and cause deleterious consequences such as abrading or gouging the surface during polishing steps, adhering to and masking portions of the semiconductor surface during etching steps, contaminating cleaning baths and other wafers therein, and creating reference inaccuracies in lithographic patterning and handling steps.
  • the peripheral edge of the semiconductor layer is typically removed, before the semiconductor layer is finished in terms of thickness, thickness variation and surface roughness, by abrading, grinding, and/or etching and is usually left at an angle or contour which minimizes the trapping of particles during subsequent exposure to a polishing slurry.
  • 07-045485 discloses edge trimming a bonded wafer by abrading with a diamond grinding tool and/or by etching.
  • U.S. Patent No. 5,340,435 to lto et al discloses rough grinding the surface of the semiconductor layer and etching the periphery of the ground surface.
  • Such edge trimming processes which employ only grinding methods, however, typically do not fully preserve the integrity of the insulating layer immediately adjacent the peripheral edge of the trimmed semiconductor layer.
  • the insulating layer which underlies the peripheral edge of the semiconductor layer is generally at least partially removed therewith to ensure complete removal of the semiconductor layer about its edge. As a result, at least part of the peripheral edge of the insulating layer is flush with the peripheral edge of the trimmed semiconductor layer. This becomes problematic during device fabrication steps where the wafers are subjected to conditions which would etch the exposed peripheral edge of the insulating layer, and thereby undercut the semiconductor layer.
  • Prior art edge-trimming processes which employ grinding and etching also suffer from certain disadvantages.
  • the grinding step leaves a coarse, rough surface on the semiconductor.
  • the etchant may nonuniformly break through the semiconductor layer, thereby exposing the underlying oxide layer to the etchant for varying periods of time and causing irregularities in the exposed surface of the underlying oxide.
  • the risk of localized break-through to the underlying substrate layer is heightened.
  • subsequent fabrication steps may stain the exposed portion and produce a wafer which is at least cosmetically less desirable.
  • the semiconductor surface has a periphery which is excessively rounded, tapered or beveled, as shown in Figures 11(a) through 11(c) .
  • Such a tapered-edge leads to reference inaccuracies in lithographic patterning and handling steps. Additionally, the area of the semiconductor surface suitable for device fabrication is decreased. Moreover, the edge profile must typically be angled or contoured to reduce the accumulation of particulate buildup during polishing. Further, edge trimming processes known in the art are not suited to a semiconductor-on-insulator wafer having a polished semiconductor surface.
  • Abrasive edge trimming methods employ organic masks such as teflon, polyethylene, waxes or high-molecular weight organic films to protect the exposed semiconductor surface while the edge is abraded, and etching methods employ such masks to block the area of the semiconductor surface not being etched. These conventional masks may contaminate the surface of the semiconductor layer with organic residues.
  • a further object of the invention is to provide a semiconductor-on- insulator wafer having an underlying insulating layer adjacent to the peripheral edge of the semiconductor layer, having a polished surface free of contaminants, having a surface which is not tapered, beveled or rounded at its peripheral edge and being free from polishing slurry without additional process steps to contour the edge profile.
  • the present invention is directed to a process for trimming the peripheral edge of a semiconductor-on-insulator wafer having, in succession, a substrate layer, an insulating layer and a semiconductor layer which has a first surface adjacent the insulating layer and a second surface parallel to and opposing the first surface.
  • the process comprises forming a masking layer on the second surface of the semiconductor layer wherein the second surface has a RMS surface roughness of less than about 1 ⁇ m over an area of about or less than 625 ⁇ m 2 .
  • the masking layer covers all of the second surface except for an edge margin thereof .
  • the uncovered peripheral portion of the semiconductor layer is etched without substantially etching the masking layer.
  • the process comprises forming a masking layer on the second surface of the semiconductor layer, the masking layer covering all of the second surface except for an edge margin thereof and etching the semiconductor layer to remove the uncovered portion of the semiconductor layer without substantially etching the masking layer. After etching, the masking layer is removed from the second surface of the semiconductor layer and the thickness of the semiconductor layer is reduced by about or less than about 1 ⁇ m.
  • a masking layer is formed over the entire second surface of the semiconductor layer and a protective film is deposited over the masking layer.
  • a peripheral portion of the film is removed to expose a peripheral portion of the underlying masking layer, which, in turn, overlies the edge margin of the semiconductor layer.
  • the exposed peripheral portion of the masking layer is then etched with an etchant that preferentially etches the masking layer over the semiconductor layer to remove the peripheral portion of the masking layer and thereby expose the edge margin of the semiconductor layer.
  • the uncovered portion of the semiconductor layer is then etched without substantially etching the masking layer and without substantially etching the insulating layer.
  • the semiconductor layer has a thickness of less than about 50 ⁇ m and the second surface of the semiconductor layer has a RMS surface roughness of less than about 1 ⁇ m per an area of about 625 ⁇ m 2 .
  • a masking layer is formed over the entire second surface of the semiconductor layer and a protective film is deposited over the masking layer.
  • a peripheral portion of the protective film is then removed to expose a peripheral portion of the underlying masking layer, the exposed peripheral portion including the area of the masking layer which overlies the edge margin of the semiconductor layer.
  • the exposed peripheral portion of the masking layer is etched with an etchant which preferentially etches the masking layer over the semiconductor layer to remove the peripheral portion of the masking layer and to thereby expose the edge margin of the semiconductor layer.
  • the semiconductor layer is then etched to remove the uncovered portion of the semiconductor layer without substantially etching the masking layer. After etching the semiconductor layer, the masking layer is removed from the second surface of the semiconductor layer and thereafter, the thickness of the semiconductor layer is reduced by less than about 1 ⁇ m.
  • the invention is further directed to a semiconductor-on-insulator wafer comprising a substrate layer having a first surface and a second surface parallel to and opposing the first surface, an insulating layer having a first surface adjacent the second surface of the substrate layer and a second surface parallel to and opposing the first surface, and a semiconductor layer having a first surface adjacent the second surface of the insulating layer, a second surface parallel to and opposing the first surface and a mean thickness.
  • the second surface of the semiconductor layer has a radius, r 2 , overlying a corresponding radius on the first surface of the semiconductor layer, r 17 and the difference in radii, r x - r 2 , is less than about ten times the mean thickness of the semiconductor layer.
  • the invention is also directed to a bonded semiconductor-on-insulator wafer comprising a substrate layer having a first surface and a second surface parallel to and opposing the first surface, an insulating layer having a first surface adjacent to the second surface of the substrate layer and a second surface parallel to and opposing the first surface, and a semiconductor layer having a first surface adjacent the second surface of the insulating layer, a second surface parallel to and opposing the first surface and a mean thickness.
  • the first surface of the semiconductor layer has a radius, r 1 and a characterizing radius, r c , which is equal to ⁇ less a distance of about ten times the mean thickness of the semiconductor layer.
  • the thickness of the semiconductor layer measured at its characterizing radius, r c is about equal to the mean thickness of the semiconductor layer.
  • the invention is directed, moreover, to a semiconductor on insulator wafer comprising a substrate layer having a first surface and a second surface parallel to and opposing the first surface, an insulating layer having a first surface adjacent the second surface of the substrate layer and a second surface parallel to and opposing the first surface, and a semiconductor layer having a first surface adjacent the second surface of the insulating layer, a second surface parallel to and opposing the first surface and a mean thickness ranging from about 100 A to about 50 ⁇ m with a maximum total thickness variation of less than about 15% of the mean thickness of the semiconductor layer.
  • the second surface of the semiconductor layer has a radius, r 2 , overlying a corresponding radius on the first surface of the semiconductor layer, ⁇ l t which also has a characterizing radius, r c , defined as x less a distance of about ten times the mean thickness of the semiconductor layer.
  • the difference in radii, r x - r 2 is less than about ten times the mean thickness of the semiconductor layer, and the thickness of the semiconductor layer measured at its characterizing radius, r c , is about equal to the mean thickness of the semiconductor layer.
  • the entire first surface of the semiconductor layer is generally uniformly bonded to the second surface of the insulating layer, and the bond formed between the semiconductor layer and the insulating layer is characterized by a lack of peripheral lamination defects.
  • FIGs. 1(a) and 1(b) are perspective and schematic cross-sectional views, respectively, of an untrimmed semiconductor-on-insulator wafer.
  • Fig. 2 is a schematic cross-sectional view of an untrimmed semiconductor-on-insulator wafer having intermediate layers.
  • Figs. 3(a) through 3(e) are views of a semiconductor-on-insulator wafer at various stages of the edge-trimming process of the present invention.
  • Figs. 3(a) , 3(c) and 3(d) are schematic cross-sectional views.
  • Fig. 3(b) is a top plan view.
  • Fig. 3(e) is a perspective view of a trimmed semiconductor-on-insulator wafer.
  • Figs. 4(a) through 4(d) are schematic cross- sectional views of a semiconductor-on-insulator wafer at various stages of a method for forming a masking layer over all but the edge margin of the surface of the semiconductor layer.
  • Figs. 5(a) and 5(b) are schematic cross-sectional views of a semiconductor-on-insulator wafer at various stages of another method for forming a masking layer over all but the edge margin of the surface of the semiconductor layer.
  • Figs. 6(a) through 6(d) are schematic cross- sectional views of semiconductor-on-insulator wafers differing in the extent to which the insulating layer covers the substrate layer.
  • Fig. 7 is a schematic cross-sectional view of a trimmed semiconductor-on-insulator wafer showing the area enlarged in Fig. 8.
  • Figs. 8(a) through 8(c) are enlarged schematic cross-sectional views of the peripheral edge of the trimmed semiconductor layer shown in Fig. 7.
  • Figs. 9(a) and 9(b) are cut-away schematic cross- sectional views of the right half of the trimmed semiconductor-on-insulator wafer shown in Fig. 7.
  • Fig. 10 is a graph showing the edge profile of a trimmed semiconductor-on-insulator wafer.
  • FIGs. 11(a) through 11(c) are enlarged schematic cross-sectional views of the peripheral edge of a semiconductor-on-insulator wafer edge-trimmed according to prior art methods.
  • the peripheral edge of a semiconductor-on-insulator wafer is trimmed by forming a differentially etchable masking layer over all but the edge margin of the surface of the semiconductor layer and selectively etching the peripheral portion of the semiconductor layer without removing the insulating layer.
  • the process may be applied to a bonded semiconductor-on-insulator wafer to remove lamination defects located between the semiconductor layer and the insulating layer.
  • the semiconductor-on-insulator wafer is close to being in its finished state before being edge-trimmed. That is, the thickness, thickness variation, surface roughness and surface defects of the semiconductor layer approximate, before edge-trimming, the same characteristics of a wafer in its final, finished form which is suitable for device fabrication. Specifically, before edge-trimming according to the present invention, the thickness of the semiconductor layer has been reduced to less than about 50 ⁇ m and the total thickness variation of the untrimmed semiconductor layer is less than about 1 ⁇ m. The surface of the untrimmed semiconductor layer has been etched or polished and has a surface roughness which is less than that of a typical ground surface.
  • the semiconductor layer has a root-mean-square (RMS) surface roughness of less than about 1 ⁇ m per an area of about 625 ⁇ m 2 and most preferably less than about 1 ⁇ m over an area of about 400 ⁇ m 2 .
  • RMS root-mean-square
  • the etching of the periphery proceeds uniformly such that the underlying insulating layer, which acts as an etch stop, is not subject to local variation in the extent to which it is exposed to the etchant.
  • a similar advantage results from having a small thickness variation. Together, the result is a more uniform insulating layer outside the periphery of the edge-trimmed semiconductor layer and a marked decrease in the likelihood of breakthrough during etching.
  • a further advantage arising out of the aforementioned characteristics of the semiconductor layer is that only minimal additional polishing is required after edge-trimming to create a finished wafer which is ready for device fabrication.
  • the edge- trimmed semiconductor-on-insulator wafer is characterized by its semiconductor layer being free from tapering, beveling and/or rounding near its periphery.
  • the resulting sharp-edged semiconductor layer improves the accuracy of lithographic patterning and handling by providing a more representative reference edge, and also maximizes the surface area available for device fabrication.
  • Bonded semiconductor-on-insulator wafers are further characterized by a lack of peripheral lamination defects.
  • an untrimmed semiconductor-on-insulator wafer 2 comprises, in succession, a substrate layer 10, an insulating layer 20 and a semiconductor layer 30.
  • the semiconductor-on- insulator wafer 2 may also comprise one or more intermediate layers 40, 42, situated between the insulating layer 20 and the semiconductor layer 30.
  • the substrate layer 10 has first and second parallel and opposing surfaces 11, 12 and a generally circular peripheral side 14.
  • the peripheral side may include an orientation flat, notch or other means for identifying wafer orientation.
  • the substrate layer 10 may be any material suitable for support and handling, including, for example, a semiconductor material such as silicon, a compound semiconductor material, polycrystalline silicon, glass materials such as fused quartz and ceramic materials such as alumina, aluminum oxide or silicon nitride.
  • the conductivity type and resistivity are not critical.
  • the substrate layer 10 may be patterned or unpatterned and may be of any desired thickness. Although thickness control is not critical for practicing the present invention, a uniform thickness is generally desirable for handling during device fabrication steps.
  • the total thickness variation of the substrate layer is preferably less than about 10 ⁇ m.
  • the insulating layer 20 has a first surface 21 adjacent the second surface 12 of the substrate layer 10 and a second surface 22 parallel to and opposing the first surface 21.
  • the insulating layer also has a peripheral side 24.
  • the insulating layer 20 is preferably silicon dioxide, silicon nitride or combinations thereof, and most preferably a thermally grown silicon dioxide.
  • the thickness of the insulating layer 20 is not critical but it preferably ranges from about 5 A (0.5 nm) to about 5 mm. Thickness control of the insulating layer is likewise not critical for practicing the present invention, but total thickness variation is preferably less than about 10 ⁇ m.
  • the semiconductor layer 30 has a first surface 31 adjacent the second surface 22 of the insulating layer 20, a second surface 32 parallel to and opposing the first surface 31, and a peripheral side 34.
  • the second surface 32 has an edge margin 36.
  • the semiconductor layer 30 may be any type of semiconductor material, compound semiconductor material or doped semiconductor material. Silicon is a preferred semiconductor material.
  • the semiconductor layer has a mean thickness which is equal to the mean perpendicular linear distance between the second surface 32 and the first surface 31 of the semiconductor layer.
  • the thickness of the semiconductor layer 30 preferably ranges from about 100 angstroms (10 nm) to about 50 ⁇ m and is preferably within about 1 ⁇ of its final thickness before edge-trimming according to the present invention, such that after edge-trimming, the semiconductor layer 30 preferably requires a reduction in its thickness of less than about 1 ⁇ m.
  • the reduction in thickness after edge-trimming is more preferably less than about 0.5 ⁇ m (5000 A) and most preferably less than about 0.3 ⁇ m (3000 A) .
  • the total thickness variation of the semiconductor layer 30 is preferably less than about 5 ⁇ m, more preferably less than about 2 ⁇ m and most preferably less than about 1 ⁇ m.
  • the second surface 32 may have an etched or polished finish prior to the edge trimming process of the present invention and is preferably polished to a specular gloss finish.
  • the second surface 32 should be free from crystallographic defects such as surface dislocations which typically result from conventional grinding processes.
  • the microroughness of the second surface 32 should have a smaller short-range variation and be less rough than conventionally ground surfaces.
  • the second surface 32 should have, prior to being edge- trimmed, a RMS surface roughness of less than about 1 ⁇ m over an area of about 625 ⁇ m 2 .
  • the surface roughness of the second surface 32 is more preferably less than about 0.5 ⁇ m, even more preferably less than about 1 nm and most preferably less than about 1 A (0.1 nm) over such an area.
  • the semiconductor-on-insulator wafer 2 includes intermediate layers 40, 42, the first surface 31 of the semiconductor layer 30 is adjacent the intermediate layer 42.
  • the intermediate layers 40, 42 may be metallic materials, refractory metal suicides, other semiconductor materials, compound semiconductor materials, polycrystalline silicon, doped silicon or ceramic materials such as sapphire or silicon carbide.
  • the semiconductor-on-insulator wafer 2 is a bonded semiconductor-on-insulator wafer in which a silicon dioxide insulating layer 20 is formed over the second surface 12 of the substrate layer 10, by thermal growth for example, and in which the first surface 31 of the semiconductor layer 30 is bonded to the second surface 22 of the insulating layer.
  • Lamination defects located around the periphery of the bond formed between the insulating layer 20 and the semiconductor layer 30 may occur due to irregularities in the shape of the unbonded layers near their periphery, defects caused by handling the unbonded layers or impurities being swept to the edge during the bonding process.
  • a masking layer 50 is formed on the second surface 32 of the semiconductor layer 30.
  • the masking layer 50 is preferably a material which is capable of being etched at an etch rate which differs from the etch rate of the semiconductor layer 30, preferably by a factor of at least 100.
  • the etch rate of the semiconductor layer 30 is preferably at least 100 times greater than the etch rate of the masking layer.
  • the etch rate of the semiconductor layer 30 is preferably at least about 100 times less than the etch rate of the masking layer.
  • Suitable materials for the masking layer 50 include silicon dioxide, silicon nitride, suicides, molybdenum, aluminum, or etch- resistant organic masking materials. Materials which would leave a residue on the second surface 32 of the semiconductor layer 30 and which would require polishing or further process steps to remove are less preferred. Silicon dioxide is a preferred material for the masking layer 50.
  • Silicon dioxide and silicon nitride masking layers 50 are formed on the second surface 32 of the semiconductor layer 30 by techniques known in the art, including thermal growth, evaporation, chemical vapor deposition and plasma enhanced deposition. Silicon dioxide is preferably formed on the masking layer 50 by thermal growth processes. Suicides are formed on the semiconductor layer 30 by chemical vapor deposition or by thermal treatment of deposited metals. Metals such as molybdenum and aluminum are formed on the semiconductor layer 30 by vapor deposition or evaporation methods.
  • the thickness of the masking layer 50 formed on the semiconductor layer 30 ranges from about 10 angstroms (1 nm) to about 1000 angstroms (100 nm) , depending on the thickness of the semiconductor layer and on the difference in the etch rate of the masking layer versus that of the semiconductor layer.
  • a 50 A (5 nm) thick Si0 2 masking layer is appropriate for use over a 2000 A (0.2 ⁇ m) thick silicon layer, whereas relatively thicker layers, such as a 400 A (40 nm) thick Si0 2 masking layer, may be appropriate over a 4.5 ⁇ m thick silicon layer.
  • the masking layer 50 is preferably free from pinhole defects which would reduce its effectiveness as a mask.
  • the masking layer is also preferably free of other defects such as edge variation, edge crown, delamination or particulates which would limit its use in defining a smooth edge.
  • the masking layer 50 covers all of the second surface 32 of the semiconductor layer 30 except for the edge margin 36 thereof.
  • the width, w, of the uncovered edge margin 36 defines the peripheral portion of the semiconductor layer 30 to be removed and ranges from about 0.5 mm to about 10 mm.
  • the width of the edge margin should be sufficient to ensure that peripheral lamination defects are removed during subsequent steps.
  • the edge margin width, w is preferably less than about 3 mm and most preferably less than about lmm.
  • one method for covering all but the edge margin 36 of the second surface 32 of the semiconductor layer 30 with the masking layer 50 includes first forming a masking layer 50 over the entire second surface 32 of the semiconductor layer 30. (Fig. 4(a)) . A protective film 60 is then deposited on the masking layer 50. (Fig. 4 (b) ) . A peripheral portion 62 of the protective film 60 is removed to expose a peripheral portion 52 of the underlying masking layer 50. (Fig. 4(c)) . The exposed peripheral portion 52 of the masking layer 50 is then removed by etching with an etchant that preferentially etches the masking layer over the semiconductor layer. (Fig. 4(d)) . The protective film 60 may, if desired, be removed. (Fig. 3(a)) .
  • the protective film 60 is an organic or inorganic film patternable by lithographic or mechanical means. Resins and polymers are suitable. Photo-resist or non photo-resist films may be employed, depending on the manner in which the peripheral portion 62 of the protective film 60 is to be removed during subsequent steps.
  • the protective film 60 is deposited by spinning it on to the masking layer 50, preferably to a thickness ranging from about 1 ⁇ m to about 3 ⁇ m.
  • the peripheral portion 62 of the protective film 60 being removed is that portion which overlies the edge margin 36 of the second surface 32 of the semiconductor layer 30.
  • the peripheral portion 62 is removed by lithographic or mechanical methods known in the art. Lithographic methods may be used to accurately and reproducibly remove photo-resist films, but are relatively expensive. Mechanical methods, such as polishing, are less expensive and may be carried out using edge grinders or edge polishing tools known in the art. If the peripheral portion 62 is removed by mechanical means, the underlying masking layer 50 is preferably a hard material relative to the protective film 60, such as silicon dioxide.
  • the exposed underlying peripheral portion 52 of the masking layer 50 is removed by etching.
  • the etchant should preferentially etch the masking layer 50 over the semiconductor layer 30 with an etch rate ratio of about 100:1.
  • the ratio of etch rates of the masking layer 50 to semiconductor layer 30 is more preferably greater than about 1,000:1.
  • a silicon dioxide masking layer 50 may be etched using hydrofluoric acid (HF) , preferably with a buffering agent such as ammonium fluoride.
  • an aqueous solution having a molar concentration of HF ranging from about 5% to about 10% will satisfactorily etch the silicon dioxide masking layer 50 at ambient temperatures within a few minutes, without substantially etching the underlying silicon semiconductor layer 30.
  • a silicon nitride masking layer 50 may be etched using phosphoric acid (H 3 P0 4 ) .
  • H 3 P0 4 phosphoric acid
  • an aqueous solution having an 85% molar concentration of H 3 P0 4 will satisfactorily etch the silicon nitride masking layer 50 at about 150 °C within about 5 minutes, without substantially etching the silicon semiconductor layer 30. Dry etching techniques known in the art could also be used to etch both silicon dioxide and silicon nitride preferentially over silicon.
  • the remainder of the protective film 60 may be removed.
  • Methods known in the art including stripping by oxidizing with sulfuric acid, dissolving in solvent, ashing or grinding can be used to completely remove the protective film 60 from the masking layer 50.
  • An alternative method for covering all but the edge margin 36 of the second surface 32 of the semiconductor layer 30 with the masking layer 50 includes, as shown in Figures 5(a) and 5(b) , covering the edge margin 36 with an annular blocking ring 70, (Fig. 5(a)) , forming a masking layer 50 on the uncovered area of the second surface 32 (Fig. 5(b)) and removing the blocking ring 70. (Fig. 3(a)) .
  • the annular blocking ring 70 may be of any material which is compatible with the subsequent formation of the masking layer 50 on the uncovered areas of the semiconductor layer 30, including, for example, glass, ceramic, quartz, semiconductors such as silicon and metals.
  • the blocking ring 70 is set onto the surface 32 to cover the edge margin 36.
  • the blocking ring 70 is preferably held in place by gravity, but may also be clamped in place.
  • the masking layer 50 may be formed on the uncovered area of the semiconductor layer surface 32 by any of the methods previously discussed, except that thermal growth is a less preferred technique.
  • the blocking ring 70 is removed by lifting it off of the surface 32. Other methods employing a similar approach are also envisioned.
  • the semiconductor layer 30 is then etched to remove the uncovered portion of the semiconductor layer 30 without substantially etching the masking layer 50, as shown in Figure 3(c) .
  • the etchant should preferentially etch the semiconductor layer 30 over the masking layer 50 with an etch rate ratio greater than about 100:1.
  • the ratio of etch rates of the semiconductor layer 30 to the masking layer 50 is more preferably greater than about 1,000:1.
  • the etchant should etch selectively, but without orientation dependency.
  • a suitable etchant is a solution comprising ethylenediamine, pyrocathecol and water.
  • the silicon semiconductor layer 30 is etched in such a ethylenediamine-pyrocathecol-water solution at standard molar concentrations and at a temperature of about 150 °C for a period ranging from about 1/2 minute to a few minutes.
  • Other suitable etchants include potassium hydroxide (KOH) or ammonium hydroxide (NH 4 OH) solutions having a molar concentration of hydroxyl ion of about 0.4 M at a temperature of about 180 °C for a period of about 5 minutes.
  • etchants such as hydrazine, ethanolamine-pyrazinamide-gallic acid-water solution, are also known in the art for preferentially etching silicon over silicon dioxide. Dry etching methods known in the art may be employed as well . These same etchants are suitable when silicon nitride is used as the masking layer 50.
  • the semiconductor layer 30 is preferably etched without substantially etching the insulating layer 20.
  • the etchants discussed above with respect to preferentially etching the semiconductor layer 30 over silicon dioxide or silicon nitride masking layers 50 are equally suitable for etching the semiconductor layer 30 over silicon dioxide or silicon nitride insulating layers 20. If the insulating layer 20 is not the same material as the masking layer 50, then the etchant would have to preferentially etch the semiconductor layer 30 over both the masking layer 50 and the insulating layer 20.
  • the trimmed semiconductor layer 30 After etching the trimmed semiconductor layer 30 has a new peripheral side 37 contained within the peripheral side 14 of the substrate layer 10, and the second surface 32 of the trimmed semiconductor layer 30 remains covered by the masking layer 50, as shown in Fig. 3(c) .
  • the masking layer 50 may be removed, if desired, by mechanical methods or by etching to expose the second surface 32 of the semiconductor layer 30. (Fig. 3(d)) .
  • the masking layer 50 is removed by preferentially etching the masking layer 50 over the semiconductor layer 30.
  • the etchant should not roughen the surface 32 of the semiconductor layer. Appropriate etchants, such as HF, and etching conditions are discussed above.
  • the masking layer 50 is the same material as the insulating layer 20 (e.g. silicon dioxide), exposed portions of the insulating layer 20 should be masked to prevent being etched when the masking layer 50 is etched. If desired, however, exposed portions of the insulating layer could be removed by etching at the same time that the masking layer is etched.
  • the insulating layer 20 e.g. silicon dioxide
  • the semiconductor layer 30 may be etched without substantially removing these intermediate layers.
  • the intermediate layers 40, 42 may also be etched to remove a peripheral portion thereof underlying the portion of the semiconductor layer removed.
  • the substrate layer 10 is preferably unaffected by any of the process steps discussed above.
  • the substrate layer 10 is not abraded, etched or otherwise altered in thickness or in edge profile. Appropriate steps known to those skilled in the art, such as masking any portions of the substrate layer 10 potentially exposed to more than substantial etching, should be employed.
  • the thickness and edge profile of the substrate layer 10 should be maintained to ensure compatibility with handling equipment and lithographic tooling and to preclude damage propagation and particle shedding during subsequent processing steps.
  • the second surface 32 of the semiconductor layer may be touch-polished or otherwise finished to achieve a desired surface finish. Regardless of the finishing means, the thickness of the edge-trimmed semiconductor layer is preferably reduced by less than about 1 ⁇ m.
  • the insulating layer 20 includes a peripheral portion 26 lying outside the peripheral side 37 of the semiconductor layer 30.
  • the peripheral portion 26 of the insulating layer 20 protects the semiconductor layer 30 from being undercut during subsequent device fabrication steps in which the insulating layer 20 could be etched out from under the semiconductor layer 30.
  • the insulating layer 20 need not extend to the peripheral side 14 of the substrate layer 10.
  • Figs. 6(b) -6(d) show further variations in which the semiconductor-on- insulator wafer 2 could also include an insulating layer 20 covering the entire first surface 11 of the substrate layer 10 (Fig.
  • the insulating layer 20 overlying these surfaces is preferably formed before the semiconductor-on-insulator wafer 2 is trimmed according the process of the present invention.
  • the semiconductor-on-insulator wafers trimmed according to the present invention have a sharp-edged semiconductor layer 30.
  • the first and second surfaces 31, 32 of the semiconductor layer 30 have first and second peripheral edges, 38, 39 respectively, which are coplanar with their respective surfaces 31, 32.
  • the edge profile or contour of the peripheral side 37 is not critical.
  • the edge profile may be generally convex, straight or concave and may be irregular or smooth.
  • the sharp-edged semiconductor layer 30 is characterized by the difference in the length of radii on the first and second surfaces 31, 32. As shown in Figure 9 (a) , the distance from the center of the second surface 32 to the second peripheral edge 39 defines a radius, r 2 , which overlies a corresponding radius, r x , on the first surface 31 of the semiconductor layer 30, defined by the distance from the center of the first surface 31 to the first peripheral edge 38.
  • the difference in radii, r x - r 2 referred to in the figures as ⁇ r, is preferably less than about ten times the mean thickness of the semiconductor layer 30, more preferably less than about two times the mean thickness of the semiconductor layer 30, and most preferably about equal to or less than the mean thickness of the semiconductor layer 30.
  • This sharp-edged feature may also be characterized in terms of the thickness of the semiconductor layer at a characterizing radius, r c , relative to the mean thickness of the semiconductor layer.
  • the characterizing radius, r c is defined as the radius r x of the first surface 31 less a distance x, r ⁇ - x, where x is preferably about ten times the mean thickness of the semiconductor layer 30, more preferably about two times the mean thickness of the semiconductor layer 30, and most preferably about equal to or less than the mean thickness of the semiconductor layer 30.
  • the thickness of the semiconductor layer 30 measured at its characterizing radius, r c is about equal to the mean thickness of the semiconductor layer 30.
  • the bond integrity is consistent throughout the bonded area.
  • the entire first surface 31 is generally uniformly bonded to the second surface 22 and the bond formed therebetween is characterized by a lack of peripheral lamination defects.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

Le bord périphérique d'une plaquette du type semi-conducteur-sur-isolant est dressé à l'aide d'un procédé consistant à déposer un masque de préférence attaquable recouvrant l'ensemble à l'exception d'une marge périphérique de la couche de semi-conducteur et à attaquer cette dernière de façon sélective de préférence sans toucher ni le masque ni l'isolant. L'épaisseur, les variations d'épaisseur, la rugosité et les défauts de la surface de la couche de semi-conducteur resteront, avant rognage, sensiblement ceux de la plaquette dans sa forme finale convenant à la fabrication de composants. Appliqué aux plaquettes collées du type semi-conducteur-sur-isolant, le procédé permet d'éliminer les défauts de lamination se trouvant entre la couche de semi-conducteur et la couche isolante. Une fois traitée la plaquette présente des bords périphériques nets et une absence de défauts de lamination périphériques.
PCT/US1997/000991 1996-01-26 1997-01-23 Procede de rognage a attaque selective pour la fabrication de plaquettes du type semi-conducteur-sur-isolant WO1997027621A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59278596A 1996-01-26 1996-01-26
US08/592,785 1996-01-26

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WO1997027621A1 true WO1997027621A1 (fr) 1997-07-31
WO1997027621A9 WO1997027621A9 (fr) 1997-10-09

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WO (1) WO1997027621A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0935280A1 (fr) * 1998-02-04 1999-08-11 Canon Kabushiki Kaisha Substrat SOI et procédé de fabrication du substrat
EP1026729A2 (fr) * 1999-02-02 2000-08-09 Canon Kabushiki Kaisha Elément composite et méthode de separation associée, empilement de substrat soudé et méthode de separation associée, méthode de transfert pour une couche de transfert, et méthode de fabrication d'un substrat SOI
US8192822B2 (en) 2008-03-31 2012-06-05 Memc Electronic Materials, Inc. Edge etched silicon wafers
US8735261B2 (en) 2008-11-19 2014-05-27 Memc Electronic Materials, Inc. Method and system for stripping the edge of a semiconductor wafer
US8853054B2 (en) 2012-03-06 2014-10-07 Sunedison Semiconductor Limited Method of manufacturing silicon-on-insulator wafers

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI553728B (zh) * 2014-07-30 2016-10-11 環球晶圓股份有限公司 邊緣氧化層剝除裝置及晶圓邊緣氧化層的剝除方法

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Publication number Priority date Publication date Assignee Title
US5340435A (en) * 1990-02-28 1994-08-23 Yatsuo Ito Bonded wafer and method of manufacturing it
JPH0745485A (ja) * 1993-06-28 1995-02-14 Sumitomo Sitix Corp 接着半導体基板の製造方法
US5494849A (en) * 1995-03-23 1996-02-27 Si Bond L.L.C. Single-etch stop process for the manufacture of silicon-on-insulator substrates

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5340435A (en) * 1990-02-28 1994-08-23 Yatsuo Ito Bonded wafer and method of manufacturing it
JPH0745485A (ja) * 1993-06-28 1995-02-14 Sumitomo Sitix Corp 接着半導体基板の製造方法
US5494849A (en) * 1995-03-23 1996-02-27 Si Bond L.L.C. Single-etch stop process for the manufacture of silicon-on-insulator substrates

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0935280A1 (fr) * 1998-02-04 1999-08-11 Canon Kabushiki Kaisha Substrat SOI et procédé de fabrication du substrat
US6417108B1 (en) 1998-02-04 2002-07-09 Canon Kabushiki Kaisha Semiconductor substrate and method of manufacturing the same
US7245002B2 (en) 1998-02-04 2007-07-17 Canon Kabushiki Kaisha Semiconductor substrate having a stepped profile
EP1026729A2 (fr) * 1999-02-02 2000-08-09 Canon Kabushiki Kaisha Elément composite et méthode de separation associée, empilement de substrat soudé et méthode de separation associée, méthode de transfert pour une couche de transfert, et méthode de fabrication d'un substrat SOI
EP1026729A3 (fr) * 1999-02-02 2004-04-21 Canon Kabushiki Kaisha Elément composite et méthode de separation associée, empilement de substrat soudé et méthode de separation associée, méthode de transfert pour une couche de transfert, et méthode de fabrication d'un substrat SOI
US8192822B2 (en) 2008-03-31 2012-06-05 Memc Electronic Materials, Inc. Edge etched silicon wafers
US8309464B2 (en) 2008-03-31 2012-11-13 Memc Electronic Materials, Inc. Methods for etching the edge of a silicon wafer
US8735261B2 (en) 2008-11-19 2014-05-27 Memc Electronic Materials, Inc. Method and system for stripping the edge of a semiconductor wafer
US8853054B2 (en) 2012-03-06 2014-10-07 Sunedison Semiconductor Limited Method of manufacturing silicon-on-insulator wafers

Also Published As

Publication number Publication date
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