WO1997012403A1

WO1997012403A1 - Diode

Info

Publication number: WO1997012403A1
Application number: PCT/JP1995/001956
Authority: WO
Inventors: Susumu Murakami; Yasuo Onose; Makoto Morishima; Sigeharu Nonoyama; Toyoichi Nemoto
Original assignee: Hitachi, Ltd.
Priority date: 1995-09-27
Filing date: 1995-09-27
Publication date: 1997-04-03

Abstract

A diode comprising a semiconductor substrate which has a pair of main planes and bevel edges, wherein an n+ type semiconductor region, an n- type semiconductor region and a p+ type semiconductor regions are formed adjacent to one another. Means for preventing carrier injection toward bevel edges is disposed in a region between the bevel edges and the end of a cathode electrode and parallel to the cathode surface of the semiconductor substrate. Accordingly, carriers can hardly be trapped by the insulator for passivation, formed on the bevel edges, and thus the diode has a high withstand voltage and high reliability.

Description

Specification

Diode Technical field

The present invention relates to a diode, and particularly to a junction structure suitable for achieving high withstand voltage and high reliability. 、, technique

A conventional diode withstanding voltage technology is described in “The Influence of IEEE Transaction on Electron Devices, Vol. ED-31, No. 6, 733 (1994)” by P. Brieger and others. In a document entitled “Surface Charge and Bevel Angle on the Blocking Behavior of a High-Voltage p + nn + Device”, the bevel angle at the end face of a semiconductor device was adjusted to reduce the electric field strength at the Pn junction surface. It is shown that a diode with high withstand voltage can be obtained.

According to Japanese Utility Model Publication No. 48-40370, according to this conventional technique, the peripheral side surface of a diode having a pn junction formed between a P-type layer and an n-type layer is formed in a concave curved shape. It has been shown that surface discharge can be prevented by forming the curved apex of the peripheral side on the lower impurity concentration layer side of the p-type layer and the n-type layer.

Further, according to the technology described in Japanese Patent Application Laid-Open No. 61-158171, the bevel surface is processed by processing the bevel surface so that at least the brazing material layer is left and one main surface of the heat buffer plate is not exposed. It shows that the reliability of the breakdown voltage characteristics can be improved and the workability of coating the passivation film can be improved.

In the first prior art mentioned above, the electric field strength on the semiconductor surface is not uniform Therefore, depending on the bevel angle and the polarity and magnitude of the charge in the protective film on the semiconductor surface, the surface of the n-type semiconductor layer having a low impurity concentration close to the p-type semiconductor layer side or the n-type semiconductor layer having a high impurity concentration The electric field is strong and the breakdown is easy. That is, the breakdown phenomenon does not occur uniformly at the Pn junction inside the device, but tends to occur at the end face. For this reason, even if a high withstand voltage diode is initially obtained, breakdown is likely to occur due to local heat generation at the time of breakdown. There is a problem that is reduced. In addition, there is a problem that the withstand voltage is reduced when a high-temperature current test is performed while a current is flowing in the forward direction.

On the other hand, even in the above-mentioned second or last conventional technology, sufficient consideration is not given to the amount of charge existing in the surface stabilizing film, and the blocking performance is reduced by the life test such as the high-temperature bias test and the current test. There's a problem.

The present invention has been made in consideration of the problems of the conventional structure as described above, and provides a highly reliable high breakdown voltage diode. Disclosure of the invention

A diode according to the present invention includes a pair of main surfaces, a first semiconductor region of a first conductivity type, and a second semiconductor of a first conductivity type which is adjacent to the first semiconductor region and has a lower impurity concentration than the first semiconductor region. A semiconductor substrate having a region and a third semiconductor region of a second conductivity type adjacent to the second semiconductor region. In this semiconductor substrate, the end has a bevel structure, a first electrode is provided on the surface of the first semiconductor region on one main surface, and the third electrode is provided on the surface of the third semiconductor region on the other main surface. A second electrode is provided. Further, a bevel region is located between the end of the first electrode and the bevel surface and is parallel to the first electrode forming surface of the semiconductor substrate. There is provided a means for suppressing the injection of the carrier into the vicinity of the surface or a means for suppressing the injection of the carrier into the insulator covering the bevel surface.

Here, the first conductivity type and the second conductivity type are p-type and n-type, respectively, but are opposite to each other.

In the diode of the present invention, when a so-called high-temperature energization test in which a forward current is applied between the first electrode and the second electrode in a high-temperature state is performed, a part of the carrier injected from the first semiconductor region extends in the bevel plane direction. Injected. The injected carriers in the direction of the bevel surface are injected into and accumulated in the interface between the semiconductor substrate near the bevel surface and the insulator usually formed on the bevel surface for passivation. An inversion layer is formed on the surface of the semiconductor substrate, which causes a decrease in breakdown voltage. In the present invention, the occurrence of such factors is prevented by means for suppressing the injection of the carrier near the bevel surface or means for suppressing the injection of the carrier into the insulator covering the bevel surface. . Here, the means for suppressing the injection of carriers is provided between the end of the first electrode and the bevel surface in a region parallel to the first electrode forming surface of the semiconductor substrate. The distance between the end of the first electrode and the beveled surface increases, and a means for suppressing the carrier injection is located between the end of the first electrode and the beveled surface. Carriers to reach can be extremely reduced. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a sectional view of a first embodiment of a high breakdown voltage diode according to the present invention. FIG. 2 is a plan view of a first embodiment of the high breakdown voltage diode according to the present invention. FIG. 3 is a view showing an impurity concentration distribution in a portion AA ′ of the high breakdown voltage diode of FIG. 1 according to the present invention. FIG. 4 is a view showing an impurity concentration distribution in a BB ′ portion of the high breakdown voltage diode of FIG. 1 according to the present invention.

FIG. 5 is a view showing a manufacturing process of the first embodiment of the high breakdown voltage diode according to the present invention.

FIG. 6 is a sectional view of a second embodiment of the high breakdown voltage diode according to the present invention. FIG. 7 is a view showing an impurity concentration distribution in a C-C ′ portion of the high breakdown voltage diode of FIG. 5 according to the present invention.

FIG. 8 is a view showing an impurity concentration distribution in a DD ′ portion of the high breakdown voltage diode of FIG. 1 according to the present invention.

FIG. 9 is a sectional view of a third embodiment of the high breakdown voltage diode according to the present invention. FIG. 10 is a sectional view of a fourth embodiment of the high breakdown voltage diode according to the present invention. _C FIG. 11 is a sectional view of a fifth embodiment of the high breakdown voltage diode according to the present invention. FIG. 12 is a sectional view of a sixth embodiment of the high breakdown voltage diode according to the present invention. FIG. 13 is a cross-sectional view of a modified example of the sixth embodiment of the high breakdown voltage diode according to the present invention.

FIG. 14 is a sectional view of another modification of the sixth embodiment of the high breakdown voltage diode according to the present invention.

The first 5 figures sectional view _c first 6 views of a seventh embodiment of the high voltage diodes according to the present invention, an eighth cross-sectional view of an embodiment of the high withstand voltage diode according to the present invention. FIG. 17 is a sectional view of a ninth embodiment of a high breakdown voltage diode according to the present invention. FIG. 18 is a view showing a manufacturing process of a ninth embodiment of the high breakdown voltage diode according to the present invention.

FIG. 19 is a sectional view of a modification of the first embodiment of the high breakdown voltage diode according to the present invention.

FIG. 20 shows a modification of the ninth embodiment of the high breakdown voltage diode according to the present invention. FIG.

FIG. 21 is a cross-sectional view of another modified example of the first embodiment of the high breakdown voltage diode according to the present invention.

FIG. 22 is a sectional view of another modified example of the ninth embodiment of the high breakdown voltage diode according to the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each embodiment, the same reference numerals are given to the equivalents. The symbols n +, η, and n − indicating the conductivity type of the semiconductor layer indicate relative differences in impurity concentration, and the impurity concentration decreases in this order. This is the same for P +, p, and P-.

(Example 1)

FIG. 1 is a sectional view showing a first embodiment of a high breakdown voltage diode according to the present invention. A p + type semiconductor region 20, an n − type semiconductor region 10, an n type semiconductor region 40, and a high impurity concentration n + type semiconductor region 30 are formed adjacent to each other. An anode electrode 120 and a force source electrode 130 are formed in the P-type semiconductor region 20 and the n + -type semiconductor region 30 having a high impurity concentration, respectively. Further, a first insulating film 5 having an elastic modulus of 10 ′ ° dyn / cm ² or more is formed on the exposed surface of the semiconductor region for stabilizing the surface of the diode. The first insulating film 5 overhangs a part of the anode electrode 120 and the cathode electrode 130 so as to cover the entire exposed surface of the semiconductor region. Further, a second insulating film 6 having an elastic modulus of 1 (T〜10 ′ ° dyn cm ² ) is formed by being laminated on the first insulating film 5.

FIG. 2 is a plan view of the high breakdown voltage diode of FIG. 1 as viewed from the cathode electrode 130 side. Each part of this high voltage diode is concentric to increase the voltage resistance Is formed.

FIG. 3 and FIG. 4 are diagrams showing the impurity concentration distribution in the AA ′ and BB ′ portions of the high breakdown voltage diode of FIG. 1 according to the present invention.

As shown in FIG. 3, the ρ + type semiconductor region 20 has a surface impurity concentration of 1 × 1 from the anode side of the η− type semiconductor region 10 which is a high resistance semiconductor substrate of 100 to 500. 0 ¹⁵ to 1 X 10 ' ⁸ Zcm ³ is formed by diffusion. Further, from the force source side, n + type semiconductor region 30 is formed by diffusion so that the surface impurity concentration becomes 1 × 10 ′ ³ to 1 × 10 ″ / cm ³ , and n + type semiconductor region 30 and n− An η-type semiconductor region 40 having an impurity concentration between the n + -type semiconductor region 30 and the η--type semiconductor region 10 is formed between the n-type semiconductor regions 10.

As shown in FIG. 4, in the η-type semiconductor region 40 diffused from the cathode side, the surface impurity concentration of the η + -type semiconductor region 30 is 1 Xi 0 ' ^s to 1 Xi 0 ²⁰ / cm ³ On the other hand, it is formed by deep diffusion so that the surface impurity concentration is at most 1 X 1 O ^ / cm ³ .

Next, the operation of the present embodiment will be described. When a forward bias voltage is applied to the pn junction so that the anode electrode 120 is positive and the cathode electrode 130 is negative, electrons from the n + type semiconductor region 30 with a high impurity concentration become p + type half. Holes are injected from the conductor region 20, and a forward current flows through this diode. The current caused by the electrons mainly flows directly below the n + -type semiconductor region 30, but also partially flows in the first insulating film 5 or at the interface between the first insulating film 5 and the semiconductor region. For example, this electron current flows at the interface between the n-type semiconductor region 40 near the n + -type semiconductor region 30 and the first insulating film 5. Therefore, electrons are accumulated as negative space charges in the first insulating film 5 near the n + type semiconductor region 30. The accumulated electrons induce holes of opposite polarity on the semiconductor surface, that is, holes, and the n + type semiconductor region A p-type inversion layer is formed on the surface of the n-type semiconductor region 40 close to 30. Such a phenomenon is particularly remarkable in a so-called energization life test in which a high temperature is applied while a forward voltage is applied.

When a reverse bias voltage is applied to the pn junction such that the anode electrode 120 of the diode in such a state becomes negative and the source electrode 130 becomes positive, the depletion layer becomes n- From the pn junction of the p-type semiconductor region 10 and the p-type semiconductor region 20 to the η − -type semiconductor region 1. Since the surface at the element end of the ρη junction has a regular bevel structure, the surface is more likely to expand than the inside. In the present embodiment, the surface of the η − type semiconductor region 10 is a positive bevel having a smaller bevel angle at a certain distance from the ρ η junction. By interposing the _η- type semiconductor region 40 having an impurity concentration between the η + -type semiconductor region 33 and the η + -type semiconductor region ₃₃ , the reverse bias voltage is applied, and the η − -type semiconductor region 10 Even if the entire surface is depleted, the depletion layer extends to the η-type semiconductor region 40, so that the surface electric field is reduced.

Therefore, the electric field intensity on the surface does not become extremely high as compared with the case of the η η + junction of the η − type semiconductor region 10 and the η + type semiconductor region 30 with a high impurity concentration, so that high reliability and high withstand voltage are obtained. Can be compatible. If the η − type semiconductor region 10 and the η + type semiconductor region 30 are directly adjacent to each other without interposing the η type semiconductor region 40, the negative charge in the first insulating film or the second insulating film will be reduced. And the ρ-type inversion layer is formed on the surface of the η-type semiconductor region 10 close to the η + type semiconductor region 30, the surface electric field becomes extremely high at the η-η + junction and the withstand voltage decreases. Would.

In this embodiment, the η-type semiconductor region 40 is parallel to the beveled inclined surface a and the force source electrode forming surface and is adjacent to the n + -type semiconductor region 30. Surface b. As a result, the distance between the n + type semiconductor region 30 and the n − type semiconductor region 10 along the exposed surface of the n type semiconductor region 40 is larger than the distance c inside the device. Thus, during conduction, electron injection from the n + type semiconductor region 30 to the n − type semiconductor region 10 near the bevel surface can be suppressed, and the first insulating film formed on this bevel surface 5 can be prevented from accumulating electrons. Therefore, the withstand voltage of the diode is stabilized, and the reliability is improved.

Electrons can be injected from the n + type semiconductor region 30 to the vicinity of the exposed surface a of the n type semiconductor region 40. However, since the exposed surface a exists between the n + type semiconductor region 30 and the bevel surface b, injection of electrons near the bevel surface b is suppressed. Therefore, if the impurity concentration of the n-type semiconductor region 40 is set so that the depletion layer does not reach the exposed surface a at the rated voltage, electrons are accumulated in the first insulating film 5 formed on the exposed surface a. However, there is no adverse effect on withstand voltage. Further, since the n-type semiconductor region 40 has a higher impurity concentration than the n − -type semiconductor region 10, P inversion is difficult. As described above, even if charges are accumulated in the first insulating film 5 formed on the exposed surfaces a and b of the n-type semiconductor region 40, the influence on the withstand voltage is small and high reliability is obtained.

FIG. 5 is a diagram showing a manufacturing process of the first embodiment.

First, as shown in (a), the surface impurity concentration is at most 1 × ^{10 17} / cm from one main surface of the high-resistance η − type semiconductor region 10 having a resistivity of 100 to 500 Ω. about 5 0 mu eta-type semiconductor region 4 0 diffusion depth of m so as to be ³ formed by any of the following methods. After forming a shallow deposition layer at a high impurity concentration of phosphorus using phosphorus dichlorite from the pair of main surfaces of the η − type semiconductor region 10 and removing the deposition layer on the back surface by etching, Drive-in diffusion at a temperature of 125 ° C. Or an oxide film only on the back Is formed, and the above-described deposition and drive-in diffusion are performed. Alternatively, n-type semiconductor region 40 is formed from one main surface of n − -type semiconductor region 10 by an epitaxy method.

Next, as shown in (b), a shallow deposition layer 20 having a high impurity concentration containing a P-type impurity such as aluminum, gallium or boron is formed from the pair of main surfaces.

Then, after removing the deposition layer on the surface of the n-type semiconductor region 40 by etching, windows of an oxide film are formed on the surface by oxidation and photo etching (not shown). An n-type impurity is selectively diffused from this window to form an n + -type semiconductor region 30 as shown in (c).

Next, as shown in (d), a metal such as aluminum is vapor-deposited, and the rear node electrode 120 and the cathode electrode 130 are formed to a predetermined size by ordinary photoetching. Further, the end face of the pn junction composed of the P + type semiconductor region 20 and the n − type semiconductor region 10 is processed with a sand blast or a grindstone so as to have a bevel angle α with respect to the horizontal plane. Work from any position on the 10 end face to a bevel angle smaller than the bevel angle. Finally, as shown in (e), the end face where each semiconductor region is exposed has a modulus of elasticity of 10 '° dyn / cm ² or more, such as polyimide silicone or a silicon dioxide film formed by a CVD method. 1 Deposit insulating film 5. Further, in order to prevent discharge, a second insulating film 6 made of, for example, silicone rubber and having an elastic modulus of 10 ^s to 10 '° dyn / cm ² is applied.

(Example 2)

FIG. 6 is a sectional view of a second embodiment of the high breakdown voltage diode according to the present invention. The difference from FIG. 1 is that a P + + type semiconductor region 120 having a higher impurity concentration than the p + type semiconductor region 20 is added to the anode side. p + When the p-type semiconductor region 20 is formed by diffusion, it is desirable that the surface impurity concentration of the p + -type semiconductor region 20 is lower than that described in FIG.

7 and 8 are diagrams showing the impurity concentration distribution in the C-C portion and the DD ′ portion of the high breakdown voltage diode of FIG. 5 according to the present invention.

As shown in FIGS. 1 and 8, from the anode side of the n − -type semiconductor region 10, which is a high-resistance semiconductor substrate of 100 to 500 Qcin, the p + -type semiconductor region 20 surface impurity concentration of 1 X 1 0 'are formed by deep rather diffused so as to be ^{5 ~ 1 X 1 0 "/} cm 3, further P ++ type semiconductor region 1 2 0 the surface impurity concentration of 1 X 1 0' ^{It is formed so as to be 8} to 1 X 10 ' ^s / cm ³ and shallower than the p + -type semiconductor region 20. As described above, by providing a two-stage diffusion layer on the anode side, When a reverse bias voltage is applied, the depletion layer almost spreads to the n − -type semiconductor region 10 of the high-resistance region, but easily spreads to the p + -type semiconductor region 20. The electric field strength of the Pn junction composed of P 0 and p + -type semiconductor region 20 can be lower than that of the structure shown in Fig. 1. Therefore, this embodiment is advantageous for increasing the breakdown voltage. + + When the forward bias voltage is applied to the mold semiconductor region 120, the effective semiconductor becomes a hole injection source, and the contact resistance with the anode electrode can be reduced, so that the forward voltage drop can be reduced.

(Example 3)

FIG. 9 is a sectional view of a third embodiment of the high breakdown voltage diode according to the present invention. Unlike the embodiment of FIG. 1, the nn + junction between the n-type semiconductor region 40 and the n + -type semiconductor region 30 having a high impurity concentration is exposed on the bevel surface. Therefore, since the photo-etching is not required when the n-type semiconductor region 30 is formed by diffusion, the manufacturing process can be simplified. Further, in this embodiment, the n + type semiconductor region from the end of the cathode electrode 130 to the bevel surface a is set. 30 width is enough. The width is set such that electrons injected from the cathode electrode 130 and passing through the n + type semiconductor region 30 are not trapped in the first insulating film 5 near the bevel surface a. Therefore, in the conduction life test, the p-type inversion layer is not easily formed on the surface of the n-type semiconductor region 40 close to the n-type semiconductor region 10, and even if a reverse bias voltage is applied, the n- The surface electric field near the n-n junction between the type semiconductor region 10 and the n-type semiconductor region 40 is not increased, and both high reliability and high withstand voltage can be achieved.

(Example 4)

FIG. 10 is a sectional view of a fourth embodiment of the high breakdown voltage diode according to the present invention. In this embodiment, the peripheral portion of the cathode electrode 130 of the n + type semiconductor region 30 in the embodiment of FIG. The exposed surface b of the region 40 is formed. Since the creepage distance of the n-type semiconductor region 40 exposed on the diode surface can be increased, higher reliability can be achieved.

(Example 5)

FIG. 11 is a sectional view showing a fifth embodiment of the high breakdown voltage diode according to the present invention. In the present embodiment, in the embodiment of FIG. 9, the exposed surface of the n + -type semiconductor region 30 having a high impurity concentration close to the force source electrode is partially removed, and the surface parallel to the cathode electrode 130 is removed. In this case, a Q 1 portion where the n-type semiconductor region 40 is exposed is formed. By doing so, the electrons injected from the force source electrode 130 or the n + type semiconductor region 30 at the time of forward bias cause the n-type in the first insulating film 5 or the first insulating film 5 in the Q 1 part. Even if negative charges are accumulated at the interface of the semiconductor region 40, when a reverse bias voltage is applied, the depletion layer extending from the pn junction consisting of the P + type semiconductor region 20 and the n − type semiconductor region 10 is n-type. It can be stopped in the semiconductor region 40 and the n-type of Q 1 It is possible to prevent the semiconductor region 40 from reaching the surface. Further, when a reverse bias voltage is applied, a depletion layer extending from the pn junction to the n − -type semiconductor region mainly at the end face portion due to electric charges in the first insulating film 5 and the second insulating film 6 even if the n-type semiconductor region Even if it extends to the surface of 40, it can be stopped at the n + -type semiconductor region 31 on the outer periphery, and the influence of the P-type inversion layer generated on the surface of the n-type semiconductor region 40 of Q 1 is eliminated, and reliability is improved. Performance can be improved.

(Example 6)

FIG. 12 is a sectional view of a sixth embodiment of the high breakdown voltage diode according to the present invention. Inside the semiconductor, ap + type semiconductor region 20, an n − type semiconductor region 10, and a high impurity concentration n + type semiconductor region 30 are formed adjacent to each other, and the p type semiconductor region 20 and the high impurity concentration n In the + type semiconductor region 30, an anode electrode 120 and a cathode electrode 130 are formed, respectively. The n-type semiconductor region 41 is formed so as to be interposed between the n + -type semiconductor region 30 and the n − -type semiconductor region 10 on the end face. Between the n + -type semiconductor regions. Since there is no n-type semiconductor region inside the device, there is an advantage that the forward voltage drop can be reduced because the operating region is thin. In order to stabilize the surface of the diode, the semiconductor region exposed on the surface has a first insulating film 5 with an elastic modulus of 10 '° dyn / cni ² or more and an elastic modulus of 10 ^s to 10'. ° The second insulating film 6 of dy ri Zcni ² is formed by lamination.

Furthermore, under the conditions of high carrier injection during conduction, the n + -type semiconductor region 30 with a high impurity concentration becomes an emitter for highly-injected electrons, while the n-type semiconductor region 41 becomes an emitter for low-injection. . Therefore, the current density inside the diode is increased, and the forward voltage drop can be reduced. Furthermore, since the current density can be reduced at the outer periphery of the diode, especially at the end face, More electrons flow in the first insulating film 5 or at the interface between the first insulating film 5 and the semiconductor region, for example, at the interface between the n-type semiconductor region 40 near the n + type semiconductor region 30 and the first insulating film 5, The phenomenon of accumulation as a negative space charge in the first insulating film 5 near the n + type semiconductor region 30 is unlikely to occur. Therefore, n + -type semiconductor area 3 0 p-type inversion layer in the n-type semiconductor region 4 1 surface is not easily formed near the _t Thus, if current life test near the n + -type semiconductor regions 3 0 by n-type half Even if a p-type inversion layer is formed on the surface of the conductor region 41, a p-type inversion layer is extremely unlikely to be formed on the surface of the n-type semiconductor region 41 near the n-type semiconductor region 10. Even if a reverse bias voltage is applied, the surface electric field near the n-n junction between the n-type semiconductor region 10 and the n-type semiconductor region 40 on the end face does not increase, and both high reliability and high breakdown voltage can be achieved.

FIGS. 13 and 14 are cross-sectional views of a modification of the sixth embodiment (FIG. 12). The difference from FIG. 12 is the depth of the n-type semiconductor region formed on the end face. In FIG. 13, the n-type semiconductor region 42 is formed at the same depth as the n + -type semiconductor region 30. In FIG. 14, an n + -type semiconductor region 30 and a deeper n-type semiconductor region 43 are formed. When a reverse bias voltage is applied when the n-type semiconductor region is deep, the depletion layer extending mainly from the P n junction consisting of the P + -type semiconductor region and the n--type semiconductor region to the n--type semiconductor region becomes an n-type semiconductor region. Reach 1 or 4 2. At this time, the depletion layer hardly reaches the surface of the n-type semiconductor region 41 or 42 close to the n + -type semiconductor region 30 by forming the n-type semiconductor region 41 or 42 as thick as the n-type semiconductor region 41. Therefore, reliability can be further improved.

(Example 7)

FIG. 15 shows a sectional view of a seventh embodiment of the high breakdown voltage diode according to the present invention. The difference from the embodiment of FIG. 14 is that the surface of the n-type semiconductor region 44 is The exposed part is partially removed. In the embodiment shown in FIG. 14, the n + type semiconductor region 30 and the n type semiconductor region 43 are selectively formed.In this embodiment, however, the n + type semiconductor region 30 is formed over the entire surface. after forming diffused by Rukoto to remove the n + -type semiconductor regions 3 0 of the end surface portion partially in the main, _t thus it is possible to lengthen the creepage distance of the n-type semiconductor region 4 4, diffusion The photo-etching step at the time of ripening can be omitted. (Example 8)

FIG. 16 is a sectional view of an eighth embodiment of the high breakdown voltage diode according to the present invention. The difference from the embodiment of FIG. 14 is that the portion Q2 exposed on the surface of the n-type semiconductor region 45 near the force source electrode is partially removed. As a result, the creepage distance of the n-type semiconductor region 45 can be further increased, so that high reliability can be achieved.

(Example 9)

FIG. 17 is a sectional view showing a ninth embodiment of the high breakdown voltage diode according to the present invention. Inside the semiconductor, ap + type semiconductor region 20, an n − type semiconductor region 10, and a high impurity concentration n + type semiconductor region 30 are formed adjacent to each other, and the p type semiconductor region 20 and the high impurity concentration n In the + type semiconductor region 30, a cathode electrode 120 and a cathode electrode 130 are formed, respectively. The n-type semiconductor region 46 is formed so as to be interposed between the n + -type semiconductor region 30 and the n − -type semiconductor region 10 on the end face, and has a high impurity concentration near the cathode electrode 130. The portion Q3 exposed on the surface of the region 30 is removed, and the n + type semiconductor region 32 is left on the outer periphery. The details of the operation of this embodiment are the same as those of the embodiment of FIG.

FIG. 18 is a diagram showing the manufacturing process of this example.

First, as shown in (a), the high resistivity of 100-500 Qcm The n-type semiconductor region 46 having a diffusion depth of about 50 μιη is subjected to normal oxidation and heat treatment so that the surface impurity concentration from the one main surface of the n- type semiconductor region 10 becomes at most 1 X 1 O'Vcm ^3. After the etching process, a shallow deposition layer with a high P (phosphorus) impurity concentration is selectively formed using phosphorous dichlorite, for example, at a temperature of 1150 to 1250 ° C. And formed by drive-in diffusion.

After that, after removing the deposition layer on the surface by etching, a window of an oxide film is formed on the surface by oxidation or photo-etching (not shown), and an n + type semiconductor region is selectively formed as shown in (c). Form 30.

Thereafter, as shown in (d), a metal such as aluminum is deposited, and a rear node electrode 120 and a force source electrode 130 are formed to a predetermined size by ordinary photoetching. Further, the end face of the pn junction composed of the P + type semiconductor region 20 and the n− type semiconductor region 10 is processed with a sand blast or a grindstone so as to have a bevel angle α with respect to the horizontal plane. Work from any position on the 0 end face to a bevel angle smaller than the bevel angle α.

Finally, as shown in (e), the end face where each semiconductor region is exposed has a first insulating film having a modulus of elasticity of 10 '° dyn Xcm ² or more, such as polyimide silicon or a silicon dioxide film formed by CVD. 5 is applied, and a silicone rubber 6 having an elastic modulus of 10 ^s to 10 '° dynZcni ² is applied to prevent discharge.

(Other variations)

The high-breakdown-voltage diodes whose sectional views are shown in FIGS. The anode electrode 120 of the first embodiment (FIG. 1) and the ninth embodiment (FIG. 17) is replaced with an alloy type. In FIGS. 19 and 20, the anode electrode 220 uses a thick plate such as tungsten or molybdenum, and uses a P + type semiconductor region 20 and a solder material 121 such as aluminum, for example. Alloyed. Operation of the modifications shown in the first 9 view and the second 0 Figure, _t still the same as the wafer pressure type shown in Figure 1 and the first 7 FIG respectively, the first 9 view and a second 0 The alloy-type electrode shown in the figures can be applied to each of the embodiments shown in FIGS.

The high-breakdown-voltage diodes shown in cross-sectional views in FIGS. 21 and 22 are also modifications of the first embodiment (FIG. 1) and the ninth embodiment (FIG. 17), respectively: In order to stabilize the surface of the diode, the semiconductor area exposed on the surface has a third elastic modulus of more than 10 ^ε dyn / cm ² , for example, silicone rubber, polyimide silicone, silicon dioxide, glass, etc. An insulating film 7 is formed. The elastic modulus 1 0 ¹ The semiconductor region in the first view and the first 7 FIG exposed on the surface. dyn Bruno cm ² or more first but second insulating film 6 of insulating film 5 and the elastic modulus is ^{1 0 S ~ 1 0 '°} dyn / cm 2 was formed by laminating, the present inventors have always surface Even if there were no two types of stabilizing films, it was confirmed that sufficiently high withstand voltage and high reliability could be achieved with only one type as in this example. The operation of each modification shown in FIGS. 21 and 22 is the same as that of the diode to which the two types of insulating films shown in FIGS. 1 and 17 are applied. The end face structure to which one type of insulating film shown in FIGS. 21 and 22 is applied depends on the embodiment shown in FIGS. 5 to 16, FIGS. 19 and 20, and FIGS. It can be applied to the modification.

In the description of FIG. 1 and FIG. 22, the end face shape of the diode is sandblasted or a grindstone to determine whether the P + type semiconductor region 20 and the n − type semiconductor region 10 The end face of the pn junction is processed so as to have a bevel angle α with respect to the horizontal plane, and the end face of the η − type semiconductor region 10 is processed so that the bevel angle β is smaller than the bevel angle α 2 A step bevel structure is applied. However, the present invention is not limited to these two-stage bevels, but a ρ η junction composed of a ρ + type semiconductor region 20 and an η − type semiconductor region 10, and a η − type semiconductor region 10 and an η type semiconductor region 4 The effect of the present invention can be achieved even if the end face of the η-η junction of 0 is processed so as to have the same bevel angle with respect to the horizontal plane. When the positive charge in the first insulating film or the second insulating film for stabilizing the surface is small, when a reverse bias voltage is applied, the surface of the η-type semiconductor region 1 An electric field may be concentrated on the surface of the η-type semiconductor region 10 near the η-type semiconductor region 40 because the depletion layer easily extends, and it is preferable that the bevel angle is not too small. Therefore, when the positive charge in the first insulating film or the second insulating film is small, the bevel angle γ may be used.

As described in detail above, according to the present invention, it is possible to achieve both high breakdown voltage and high reliability of the diode.

Claims

The scope of the claims

1. A pair of main surfaces,

A first semiconductor region of a first conductivity type;

A second semiconductor region of a first conductivity type adjacent to the first semiconductor region and having a lower impurity concentration than the first semiconductor region;

A semiconductor substrate having a second conductivity type third semiconductor region adjacent to the second semiconductor region; and

A first electrode is provided on the surface of the first semiconductor region on one main surface, and a second electrode is provided on the surface of the third semiconductor region on the other main surface, and the end of the semiconductor substrate has a bevel structure. ,

A diode located between the end of the first electrode and the bevel surface and provided in a region parallel to the first electrode forming surface of the semiconductor substrate, for suppressing injection of a carrier near the bevel surface. .

2. The diode according to claim 1, wherein the means for suppressing injection of a carrier near the bevel surface is provided in a region parallel to a first electrode forming surface of the semiconductor substrate, and wherein the first conductivity type is provided. Wherein the fourth semiconductor region has an impurity concentration lower than that of the first semiconductor region and higher than that of the third semiconductor region.

3. The diode according to claim 2, wherein the third semiconductor region is exposed on a bell surface.

4. The diode according to claim 2, wherein a recess reaching the fourth semiconductor region is provided between an end of the first electrode and a bevel surface.

5. The diode according to claim 3, wherein a recess reaching the fourth semiconductor region is provided between an end of the first electrode and a bevel surface. Diode.

6. The diode according to claim 1, wherein on the bevel surface, a first insulator having an elastic modulus of 10 '° dyn / cm ² or more and an elastic modulus of 10 ^ε to 10' ° dy η cm are provided. ^2. A diode, wherein the second insulator is laminated and covered.

7. A pair of main surfaces,

A first semiconductor region of a first conductivity type;

The first semiconductor region adjacent to the first semiconductor region and having a lower impurity concentration than the first semiconductor region.

1 a second semiconductor region of conductivity type;

A first electrode is provided on the surface of the first semiconductor region on one main surface, and a second electrode is provided on the surface of the third semiconductor region on the other main surface. The end of the semiconductor substrate has a bevel structure. , The bevel surface is covered with an insulator,

A device is provided between the end of the first electrode and the bevel surface, and in a region parallel to the first electrode forming surface of the semiconductor substrate, means for suppressing injection of the carrier into the insulator near the bevel surface is provided. Diode.

8. The diode according to claim 7, wherein the means for suppressing injection of the carrier into the insulator near the bevel surface is provided in a region parallel to the first electrode forming surface of the semiconductor substrate, A diode comprising: a fourth semiconductor region having a lower impurity concentration than the first semiconductor region and a higher impurity concentration than the third semiconductor region.

9. The diode according to claim 8, wherein the third semiconductor region is exposed on a bell surface.

10. The diode according to claim 8, wherein a recess reaching the fourth semiconductor region is provided between an end of the first electrode and a bevel surface.

11. The diode according to claim 9, wherein a recess reaching the fourth semiconductor region is provided between an end of the first electrode and a bevel surface.

12. The diode according to claim 7, wherein the insulator has a modulus of elasticity of at least ^{1 10} dyn / cm ^{2 and} a first insulator having an elastic modulus of 1 (Γ to 10 ′ ° dyn / cm ² ). a diode, which is formed by stacking a second insulator having a size of 2 cm ² .

1 3. A pair of main surfaces,

A first semiconductor region of a first conductivity type;

A first electrode is provided on the surface of the first semiconductor region on one main surface, and a second electrode is provided on the surface of the third semiconductor region on the other main surface. The end of the semiconductor substrate has a bevel structure. ,

In a region located between the end of the first electrode and the bevel surface and parallel to the surface on which the first electrode is formed of the semiconductor substrate, the impurity concentration of the first conductivity type is lower than that of the first semiconductor region and lower than that of the third semiconductor region. A diode having a high fourth semiconductor region.

14. The diode according to claim 13, wherein the third semiconductor region is exposed on a bevel surface.

15. The diode according to claim 13, wherein a recess reaching the fourth semiconductor region is provided between an end of the first electrode and a bevel surface.

16. The diode according to claim 14, wherein a recess reaching the fourth semiconductor region is provided between an end of the first electrode and a bevel surface.

17. The diode according to claim 13, wherein a first insulator having an elastic modulus of 10 '° dyn / cm ² or more and an elastic modulus of 10 ^ε to 10' ° dy η are formed on the bevel surface. characterized in that a second insulator of / cm ² is laminated and covered.