WO1997011530A1 - Procede de decodage d'une grappe d'erreurs du code de reed-solomon et dispositif correspondant - Google Patents

Procede de decodage d'une grappe d'erreurs du code de reed-solomon et dispositif correspondant Download PDF

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Publication number
WO1997011530A1
WO1997011530A1 PCT/JP1995/001883 JP9501883W WO9711530A1 WO 1997011530 A1 WO1997011530 A1 WO 1997011530A1 JP 9501883 W JP9501883 W JP 9501883W WO 9711530 A1 WO9711530 A1 WO 9711530A1
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WO
WIPO (PCT)
Prior art keywords
error
code
pattern
polynomial
sequence
Prior art date
Application number
PCT/JP1995/001883
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English (en)
Japanese (ja)
Inventor
Yasuhiro Hirano
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1995/001883 priority Critical patent/WO1997011530A1/fr
Publication of WO1997011530A1 publication Critical patent/WO1997011530A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials

Definitions

  • the present invention relates to a method for decoding a parity error of a Reed-Solomon code and a decoding device.
  • the present invention relates to a decoding method and a decoding device for an error correction code, and more particularly to a decoding method and a decoding device suitable for correcting a burst error in a Reed-Solomon code.
  • the digital transmission 'recording system' employs a code is re-correction technology that decodes the original information even if a friendship occurs during the transmission or recording 'reproduction process.
  • a code S is formed by adding a check bit for detecting an erroneous detection or correction to information to be transmitted or recorded, and transmitting or recording is performed; and On the receiving side, errors are detected and K-correction is performed using the check bits added on the transmitting side.
  • RS code Reed-Solomon code
  • the t-checker RS code can correct up to t pit errors contained in the code word. Therefore, the t-checker RS code is a random code in which the code is randomly generated. »Res can be used as t random correct codes. In addition, t-fold 38 re-correction RS code, code K is concentrated in one place. The burst error that occurs when the burst error occurs can be used as a code for correcting the burst error of length t-pites.
  • the decoding process is complicated because the error correction is assisted by the decoding method according to the random error correction decoding procedure even for the burst error correction. Therefore, a method of decoding a burst error with a simple decoding process is desired.
  • a method of decoding a burst error with a simple decoding process is desired.
  • burst errors due to scratches on the recording medium, etc. frequently occur, so it is extremely important to determine how to simplify the decoding process of the burst errors.
  • the present invention has been made in view of the above-described SJ8, and has as its object to provide a decoding method and a decoding device that can perform a burst IS recorrection decoding process on an RS code extremely efficiently.
  • the error pattern is corrected by adding the error pattern to a position corresponding to the above-mentioned error position.
  • the first, second, and fourth steps in this decoding method are the same as those in the conventional technique, but the third step is a completely different technique from the conventional technique. Which enables the calculation of the position.
  • the basis of the decoding method in the present invention is to calculate a burst error position ⁇ using the burst pattern equation in the third step described above; ⁇ ⁇ ( ⁇ ).
  • Figure 2 shows the codeword of a triple error correction RS code with code length ⁇ and number of information points ⁇ -6, and its generator polynomial G 0 (X) is
  • ⁇ 0 ( ⁇ ) ( ⁇ -1) ( ⁇ - ⁇ ) ( ⁇ - ⁇ 2 ) ( ⁇ - ⁇ 3 ) ( ⁇ - ⁇ 4 ) ( ⁇ - ⁇ 5 ) ... (Equation 1).
  • the dot part in the code firewood shown in FIG. 2 indicates the region where the code error occurs, and the code new i + 2, i + 1, i-th position is a peri-pattern; E [ + E1 + 1 , ⁇ ( There is a parse error of length 3 bits. Therefore, the receiving polynomial; ⁇ ( ⁇ ) is the transmitting polynomial; W (X) plus the L polynomial EB (X). .
  • BP (X) a new burst pattern equation that uses 1 as the coefficient of X when there is a code error in 1) and 0 when there is no code error, is introduced.
  • this burst pattern equation; BP (X) is
  • Equation 9 add Equation 9 to ⁇ and the burst pattern equation; ⁇ ⁇ ⁇ ( ⁇ ) Product defined by the burst position polynomial; (a)
  • Fig. 3 shows the burst pattern equation; B ⁇ ( ⁇ ) in the t-ary positive RS code.
  • the »real number in the figure is the actual code Is the number of occurrences.
  • Fig. 4 compares the worst value of the number of searches required to find the position of a burst error between the present invention and the prior art.
  • the numbers in parentheses in the figure are for the Chien search method used in the prior art. Is shown. In the prior art, when the number of errors is 2 or more, the number is n-1 times (n is the code length). In many cases, the code length n is about 100 to 200. Therefore, the present invention makes it possible to efficiently obtain the position of a burst error with a very small number of steps, from one-several to several tenths of the prior art.
  • FIG. 8 is a configuration example of a multiplication circuit of the first embodiment
  • FIG. 9 is a configuration example of a division circuit of the first embodiment
  • FIG. 10 is a diagram illustrating a second decoding procedure of the JS recorrection of the RS code according to the present invention
  • FIG. 11 is a diagram illustrating a second embodiment of the present invention.
  • FIG. 5 is a block diagram showing the overall configuration of the first embodiment of the present invention. I will explain.
  • the present embodiment is suitable for performing the RS error correction of the RS code by the decoding procedure shown in FIG.
  • 1 is a syndrome operation unit
  • 2 is an error position polynomial operation unit
  • 3 is a burst pattern detection unit
  • 4 is a peri-pattern operation unit
  • 5 is a delay unit
  • 6 is an addition ffi.
  • Y0 is input to the syndrome calculation section 1 and the extension section 5.
  • the error pattern calculation unit 4 calculates the error pattern; Ei, which is the fourth step in the decoding procedure. That is, when the signal; EN is 1, the erroneous position sequence: ⁇ hysteresis sequence; Ei is measured at each error position; Ei is calculated; and an error pattern sequence is output; E is added.
  • the adder 6 is a signal delayed by Noburo 5; Y0D error occurs. No place! Correcting the error by adding the error pattern corresponding to, and obtaining an RS code; YD that has undergone burst 18 correction decoding processing on the output.
  • Y0 is ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ Y Y
  • Equation 4 The operation shown in Equation 4 is performed on the received code S; ⁇ 0, and the following syndrome is obtained.
  • Useful codeword Perform the operation shown in Equation 4 for $ 0 to obtain the following syndrome.
  • N 1 S, S, S 2 + S s S 1 S 1 -l- S ⁇ S, So + S »S J S ol- S 4 S J S 1
  • the code S is located at the second (N), third ( ⁇ 1 ) and fourth ( ⁇ positions) from the right end of the received code fi.
  • Example 4 Received codeword; When Y0 is 0 0 0 0 0 0 0 0 0 0 0 0 a 2 3 a [First step] Syndrome calculation
  • N 2 S 4 S, S J + S, S, So + S «S, S 1 + S 4 S 4 S o + S 5 S 1 S 1 + S 3 S, S
  • N 3 S. S 2 S J + S, S S S 3 + S. S 4 S 1 + S, S 5 S I -1- S S S J S 1 + S, S s S 2
  • FIG. 7th is a configuration example diagram of the syndrome operation unit 1 in the first step of the decoding method.
  • the combination of an EXOR circuit 7, a shift register circuit 8, and a coefficient multiplication unit 9 has the syndrome S.
  • the calculation of to S S Note that coefficient multiplying portion 9, the coefficient values;. Performs 1, ⁇ ', ⁇ ⁇ ⁇ , a multiplication of a s respectively, an input signal (a,, a 2, a, a 0 ), each output can be obtained by the following calculation,
  • Multiplication coefficient value ⁇ ' (. A, a 3 + a, a s + a 2, a 2)
  • FIG. 8 is a structural example diagram of a circuit that performs multiplication of a in the second, third, and fourth steps of the decoding method.
  • FIG. 9 is a diagram showing a configuration example of a circuit that divides a′Zii ′ in the second, third, and fourth steps of the decoding method. It is composed of a ROM circuit 12 and a multiplication circuit 13 shown in FIG. 8.
  • the ROM circuit 12 has an input; ⁇ (j j ,,
  • FIG. 10 shows a decoding procedure in the present embodiment.
  • the third, fourth and fourth steps are the same as the decoding procedure shown in FIG. 1.
  • the error position is calculated by the conventional Chien search method. According to this decoding process, the error position of a random error included in the received code S can be calculated. Therefore, in the decoding procedure according to the present embodiment, the present invention can be applied to a burst error. For the ffi-go method, it is possible to perform the same Didi correction as in the prior art for random attacks.
  • FIG. 11 is an example of a configuration for performing this decoding method.
  • 1 is a syndrome operator
  • 2 is a periposition polynomial operation unit
  • 3 is a burst pattern detector
  • 4 is a burst pattern detector.
  • Peripattern calculation unit 5 is the delay unit
  • 6 is the addition unit
  • 14 is the Chien search ffi.
  • the received code of the t-ary re-correction RS code; Y0 is input to the syndrome calculation unit 1 and «Noburou 5;
  • the syndrome calculation unit 1 calculates the syndrome, which is the first step of the signing procedure. That is, the syndrome calculation unit 1 performs the calculation shown in Expression 4 on the received code; Y0, and calculates the syndrome: S ⁇ i-O, ,..., 2 t — 1) is calculated, and this S i ⁇ O, 1,..., 2 t—1) is output as a syndrome sequence;
  • 0 is output to EN.
  • ⁇ When 0, output signal 1;
  • the error return pattern calculation unit 4 calculates the error pattern; ⁇ ⁇ , which is the fourth step in the decoding procedure. That is, when the signal: ⁇ is 1, the position sequence sequence of the game: ⁇ or / 9/9 and Calculate the erroneous return pattern of the erroneous position; And output an error pattern sequence;
  • Adder 6 is the signal delayed by delay 5; Y0D error has occurred
  • the Q code is corrected by adding the pattern corresponding to the position, and an RS code; YD, which has been subjected to decoding processing for burst error correction, is obtained from the output.
  • the burst correction of the RS code can be performed by a very simple decoding process, and the random number can be corrected in the same manner as in the related art.
  • a code in which a burst error and a random error in a storage medium and the like are wetted can have a significant effect on correcting the code K.
  • a burst error in an RS code can be obtained.
  • the decoding method and decoding device for a parse error of a Reed-Solomon code according to the present invention are used as a decoding method and a decoding device 31 for an R-read positive code in a reproducing device such as a compact disk or digital VTR. It is useful, and in particular, since bursting in the Rs code can be corrected by extremely simple decoding processing, it is possible to reduce bursting that occurs in storage media such as storage compact disks and digital VTRs. Or a sign error of a random string can have a significant K effect.

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Algebra (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

L'invention a trait à un procédé ainsi qu'au dispositif correspondant de décodage de code correcteur d'erreurs au titre desquels on peut calculer la position d'une grappe d'erreurs avec un volume de calculs des plus réduits en calculant, dans un premier temps, le syndrome Si (i = 0,1, 2, .., 2t-1) de codes correcteurs d'erreurs RS à binaires multiples de t et, dans un deuxième temps en calculant les facteurs (j) (j≤t) d'un polynôme de position d'erreurs (Z) = 1 + σi Z + .. + σj Zj à l'aide du syndrome Si. Dans un troisième temps, on établit les positions de la grappe d'erreurs (j) au moyen de BP (α) . η par l'extraction d'une équation de configuration de grappe satisfaisant η = σ¿i?/BP (α) et σ (η?-1¿) = 0 de l'équation de configuration de grappe BP (α) = 1 + αp + .. + αr que déterminent des entiers (j), 1, p, .., r (1∫p∫..∫r≤t). Dans un quatrième temps, on corrige la grappe d'erreurs (j) en établissant les configurations d'erreurs (j). Il est, de la sorte, possible de calculer les positions d'une grappe d'erreurs avec un volume de calculs des plus réduits.
PCT/JP1995/001883 1995-09-20 1995-09-20 Procede de decodage d'une grappe d'erreurs du code de reed-solomon et dispositif correspondant WO1997011530A1 (fr)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001073952A1 (fr) * 2000-03-27 2001-10-04 Matsushita Electric Industrial Co., Ltd. Decodeur et procede de decodage
US6697989B1 (en) 1999-09-08 2004-02-24 Matsushita Electric Industrial Co., Ltd. Method and apparatus for error correction
US7327218B2 (en) 1998-01-19 2008-02-05 Zih Corp. Electronic identification system with forward error correction system
US8301886B2 (en) 2001-08-24 2012-10-30 Zih Corp. Method and apparatus for article authentication
USRE44220E1 (en) 1998-06-18 2013-05-14 Zih Corp. Electronic identification system and method with source authenticity
US9639150B2 (en) 1999-07-31 2017-05-02 Craig L. Linden Powered physical displays on mobile devices
CN109379084A (zh) * 2018-09-08 2019-02-22 天津大学 一种针对突发错误的译码方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607544A (ja) * 1983-06-28 1985-01-16 Fujitsu Ltd ランダム多重訂正復号化回路方式
EP0147041A2 (fr) * 1983-12-22 1985-07-03 Laser Magnetic Storage International Company Dispositif de protection d'erreurs
JPS63286026A (ja) * 1987-05-19 1988-11-22 Mitsubishi Electric Corp 誤り訂正方法
JPH03149924A (ja) * 1989-11-06 1991-06-26 Mitsubishi Electric Corp 誤り訂正復号装置
JPH05335969A (ja) * 1992-06-03 1993-12-17 Matsushita Electric Ind Co Ltd 誤り訂正装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607544A (ja) * 1983-06-28 1985-01-16 Fujitsu Ltd ランダム多重訂正復号化回路方式
EP0147041A2 (fr) * 1983-12-22 1985-07-03 Laser Magnetic Storage International Company Dispositif de protection d'erreurs
JPS63286026A (ja) * 1987-05-19 1988-11-22 Mitsubishi Electric Corp 誤り訂正方法
JPH03149924A (ja) * 1989-11-06 1991-06-26 Mitsubishi Electric Corp 誤り訂正復号装置
JPH05335969A (ja) * 1992-06-03 1993-12-17 Matsushita Electric Ind Co Ltd 誤り訂正装置

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7327218B2 (en) 1998-01-19 2008-02-05 Zih Corp. Electronic identification system with forward error correction system
USRE44220E1 (en) 1998-06-18 2013-05-14 Zih Corp. Electronic identification system and method with source authenticity
US9639150B2 (en) 1999-07-31 2017-05-02 Craig L. Linden Powered physical displays on mobile devices
US6697989B1 (en) 1999-09-08 2004-02-24 Matsushita Electric Industrial Co., Ltd. Method and apparatus for error correction
WO2001073952A1 (fr) * 2000-03-27 2001-10-04 Matsushita Electric Industrial Co., Ltd. Decodeur et procede de decodage
US8301886B2 (en) 2001-08-24 2012-10-30 Zih Corp. Method and apparatus for article authentication
US8667276B2 (en) 2001-08-24 2014-03-04 Zih Corp. Method and apparatus for article authentication
CN109379084A (zh) * 2018-09-08 2019-02-22 天津大学 一种针对突发错误的译码方法
CN109379084B (zh) * 2018-09-08 2021-09-17 天津大学 一种针对突发错误的译码方法

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