WO1997008737A3 - Schaltungsanordnung mit einer hybridschaltung - Google Patents
Schaltungsanordnung mit einer hybridschaltung Download PDFInfo
- Publication number
- WO1997008737A3 WO1997008737A3 PCT/DE1996/001596 DE9601596W WO9708737A3 WO 1997008737 A3 WO1997008737 A3 WO 1997008737A3 DE 9601596 W DE9601596 W DE 9601596W WO 9708737 A3 WO9708737 A3 WO 9708737A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- hybrid
- arrangement including
- ceramic substrates
- mounted components
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
Die Erfindung bezieht sich auf eine Schaltungsanordnung mit einer Hybridschaltung, die auf einem Keramik-Substrat eine Schichtschaltung und oberflächenmontierbare Bauelemente aufweist. Um eine solche Schaltungsanordnung möglichst klein und kostengünstig herstellen zu können, weist erfindungsgemäß die Hybridschaltung ein weiteres Keramik-Substrat (2) auf, und die Schichtschaltung und die oberflächenmontierbaren Bauelemente (22 bis 25) sind vorzugsweise auf beide Keramik-Substrate (1, 2) verteilt angeordnet. Dabei liegen Teile (5, 6) der Schichtschaltung auf verschiedenen Teilbereichen (16; 17', 18') jeweils einer Seite (3, 4) der Keramik-Substrate (1, 2) und die oberflächenmontierbaren Bauelemente (22 bis 25) auf der jeweils anderen Seite (20, 21) der Keramik-Substrate (1, 2). Die Keramik-Substrate (1, 2) sind mit ihren jeweils einen Seiten (3, 4) zusammengeklebt.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE1995132653 DE19532653C1 (de) | 1995-08-24 | 1995-08-24 | Schaltungsanordnung mit einer Hybridschaltung |
DE19532653.9 | 1995-08-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1997008737A2 WO1997008737A2 (de) | 1997-03-06 |
WO1997008737A3 true WO1997008737A3 (de) | 1997-04-10 |
Family
ID=7771250
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1996/001596 WO1997008737A2 (de) | 1995-08-24 | 1996-08-22 | Schaltungsanordnung mit einer hybridschaltung |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE19532653C1 (de) |
WO (1) | WO1997008737A2 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10203827C2 (de) * | 2002-01-31 | 2003-12-18 | P21 Power For The 21St Century | Leiterplattenanordnung sowie elektrisches Bauteil |
DE102009040914A1 (de) * | 2009-09-10 | 2011-03-31 | Conti Temic Microelectronic Gmbh | Leiterplattenverbund und Leiterplattensystem |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE8428437U1 (de) * | 1984-09-27 | 1986-01-30 | Robert Bosch Gmbh, 7000 Stuttgart | Schaltungshybrid für elektronische Schaltungen |
JPH01173777A (ja) * | 1987-12-28 | 1989-07-10 | Matsushita Electric Ind Co Ltd | 積層型集積回路モジュール |
JPH01226192A (ja) * | 1988-03-07 | 1989-09-08 | Matsushita Electric Ind Co Ltd | 混成集積回路装置 |
JPH02105595A (ja) * | 1988-10-14 | 1990-04-18 | Nec Corp | 混成集積回路 |
JPH02114697A (ja) * | 1988-10-25 | 1990-04-26 | Matsushita Electric Ind Co Ltd | 混成集積回路装置 |
-
1995
- 1995-08-24 DE DE1995132653 patent/DE19532653C1/de not_active Expired - Fee Related
-
1996
- 1996-08-22 WO PCT/DE1996/001596 patent/WO1997008737A2/de active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE8428437U1 (de) * | 1984-09-27 | 1986-01-30 | Robert Bosch Gmbh, 7000 Stuttgart | Schaltungshybrid für elektronische Schaltungen |
JPH01173777A (ja) * | 1987-12-28 | 1989-07-10 | Matsushita Electric Ind Co Ltd | 積層型集積回路モジュール |
JPH01226192A (ja) * | 1988-03-07 | 1989-09-08 | Matsushita Electric Ind Co Ltd | 混成集積回路装置 |
JPH02105595A (ja) * | 1988-10-14 | 1990-04-18 | Nec Corp | 混成集積回路 |
JPH02114697A (ja) * | 1988-10-25 | 1990-04-26 | Matsushita Electric Ind Co Ltd | 混成集積回路装置 |
Non-Patent Citations (4)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 13, no. 445 (E - 829) 6 October 1989 (1989-10-06) * |
PATENT ABSTRACTS OF JAPAN vol. 13, no. 548 (E - 856) 7 December 1989 (1989-12-07) * |
PATENT ABSTRACTS OF JAPAN vol. 14, no. 320 (E - 0950) 10 July 1990 (1990-07-10) * |
PATENT ABSTRACTS OF JAPAN vol. 14, no. 338 (E - 0954) 20 July 1990 (1990-07-20) * |
Also Published As
Publication number | Publication date |
---|---|
WO1997008737A2 (de) | 1997-03-06 |
DE19532653C1 (de) | 1997-01-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
AU7391196A (en) | Printed circuit board interconnection between layers | |
AU7385698A (en) | An electronic component package with posts on the active surface | |
AU8648598A (en) | Adhesive for bonding circuit members, circuit board, and method of producing thesame | |
SG89299A1 (en) | Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument | |
AU7839098A (en) | Hybrid substrate for cooling an electronic component and method for forming the substrate | |
CA2073211A1 (en) | Method of manufacturing a rigid-flex printed wiring board | |
AU6053996A (en) | Bear chip mounting printed circuit board | |
EP0650197A3 (de) | Intergrierter Dünnfilm-Halbleiterschaltkreis und dessen Herstellungsverfahren. | |
EP0829930A3 (de) | Elektrischer Steckverbinder für Oberflächenmontage mit integrierten Leistungsanschlüssen | |
DE69008963D1 (de) | Elektronisches Schaltungssubstrat. | |
EP0738007A3 (de) | Mehrschichtschaltungssubstrat mit einer Metallbasis | |
AU1917895A (en) | Integrated circuit lamination process | |
EP1041633A4 (de) | Halbleiterbauelement, seine herstellung, leiterplatte und elektronischer apparat | |
AU6483199A (en) | Electronic circuit board | |
CA2202426A1 (en) | Mounting structure for a semiconductor circuit | |
EP0777268A3 (de) | Herstellung einer integrierten Schaltung | |
DE59006957D1 (de) | Plättchenförmige Substrate. | |
DE69535391D1 (de) | Mehrlagenschaltungssubstrat | |
DE3873938T2 (de) | Laminiertes substrat fuer integrierte schaltungen. | |
EP0784384A4 (de) | Antennenschalter | |
CA2309216A1 (en) | Laminated parts and method of making same | |
GB2392560A (en) | Manufacture of solid state electronic components | |
EP0335679A3 (en) | Bonded ceramic-metal composite substrate, circuit board constructed therewith and methods for production thereof | |
EP0289197A3 (de) | Elektrooptische Vorrichtung | |
EP0782376A3 (de) | Polyimid-Metallfolie-Verbundfilm |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
AK | Designated states |
Kind code of ref document: A3 Designated state(s): US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
122 | Ep: pct application non-entry in european phase |