WO1996034394A1 - Memoire de donnees - Google Patents

Memoire de donnees Download PDF

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Publication number
WO1996034394A1
WO1996034394A1 PCT/DE1996/000368 DE9600368W WO9634394A1 WO 1996034394 A1 WO1996034394 A1 WO 1996034394A1 DE 9600368 W DE9600368 W DE 9600368W WO 9634394 A1 WO9634394 A1 WO 9634394A1
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WO
WIPO (PCT)
Prior art keywords
memory
lines
type
memory cell
control lines
Prior art date
Application number
PCT/DE1996/000368
Other languages
German (de)
English (en)
Inventor
Werner Henze
Original Assignee
Werner Henze
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Werner Henze filed Critical Werner Henze
Priority to AU48746/96A priority Critical patent/AU4874696A/en
Publication of WO1996034394A1 publication Critical patent/WO1996034394A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Definitions

  • the invention relates in the broadest sense to a data store.
  • a data memory is composed of individual memory cells for storing one of two possible memory states that represent logical information.
  • the invention thus relates in the narrower sense to a single storage cell.
  • each state represents a possible piece of information that corresponds, for example, to a logical one or a logical zero.
  • each state in the other must be reversible by an energy supplied from outside and the process should be able to be repeated at any time without restriction.
  • remagnetizable particles are used, such as, for example, in the known magnetic tapes or magnetic hard disks, or, for example, changeable magneto-optically reflecting parts of a surface, and in particular also states of semiconductor circuits which result from numerous flip Flops exist, such as the RAMs known in computer technology; or semiconductor zones, like an EPROM or EEPROM.
  • the memory cell is to be understood as the smallest logical unit of a data memory. All of the conventional storage media or data storage media mentioned have the disadvantage that the storage cells have to be arranged in a surface-oriented manner, ie essentially in one plane.
  • the object of the invention is therefore to provide a data memory
  • the storage capacity of the usable volume of the storage is much larger than that of conventional storage
  • each memory cell can be controlled directly and therefore can be written and read immediately
  • - Can be easily fed and removed from a device with which it can be operated. whose address line can also be used for reading and writing data.
  • a data memory which is composed of memory cells according to the invention, a memory cell according to the invention being characterized by the following features:
  • the storage cell has a cavity filled with an electrolyte, which is surrounded by an electrically non-conductive wall,
  • the capillaries are filled with a metal and act as electrodes, with at least two capillaries forming electrodes of the first type and the at least one further capillary forming an electrode of the second type,
  • the two pole faces of the capillaries forming the electrodes of the first type are so closely arranged relative to one another and the dimensions of the at least one further capillary forming an electrode of the second type are dimensioned such that the mass of the metal forming the electrode of the second type is at one Operation of the electrode of the second type as anode and the two electrodes of the first type as cathodes is sufficient to establish a metallically conductive connection between the pole faces of the
  • the invention also includes the manner in which a data memory is constructed from the memory cells according to the invention.
  • a memory cell is the smallest logical unit of the data memory according to the invention. Certain spatial dimensions are assigned to it.
  • Several memory cells can be arranged in one memory line.
  • Several storage lines form a storage level.
  • Several storage levels can be combined to form a storage block.
  • Memory blocks can be divided electrically or logically into memory segments.
  • a data memory consists of at least one memory block, which is preferably structured logically or by electrically conductive connections in memory segments.
  • a control circuit is required which can either be formed separately from the actual data memory or can be integrated into it.
  • the control circuit can, for example, be integrated in a computer, the computer housing having an insertion slot into which the actual data memory is inserted in the manner of a drawer.
  • the data storage device can have contacts on its upper and lower cover surface.
  • FIG. 1A shows a schematic illustration of a memory cell according to the invention
  • FIG. 1B - a top view of the memory cell according to FIG. 1A
  • FIG. 1D an electrical equivalent circuit diagram for the original state of the memory cell shown in FIG. IC
  • FIG. 2A shows a memory cell according to the invention in section in the state "0"
  • FIG. 2B an electrical equivalent circuit diagram for the state "0"
  • FIG. 2C - a summarized equivalent circuit diagram according to FIG. 2B
  • FIG. 3B an equivalent circuit diagram of the state "1"
  • FIG. 3C - a calculated equivalent circuit diagram according to FIG. 3B
  • FIG. 4A - a resistance matrix, each resistance corresponding to a memory cell
  • FIG. 4B - the resistance matrix according to FIG. 4A in a modified optical arrangement
  • FIG. 5 shows a memory cell matrix with additionally inserted diode pairs, each memory cell in turn being symbolized by a resistor
  • FIG. 6 - a table with possible control potentials for the memory cell matrix
  • Figure 7A - a schematic plan view of the geometric arrangement of an inventive
  • FIG. 7B an electrical equivalent circuit diagram for a memory cell according to the invention
  • FIG. 7C - a perspective illustration of a breakout from a storage level according to FIG. 7A
  • FIG. 8 shows a geometric arrangement of conductor tracks and memory cells in a memory level, composed of memory cells according to FIG. 7A or 7C,
  • FIG. 9A - a schematic representation of a memory block or data memory composed of several memory levels
  • FIG. 9B - a schematic representation of the construction of a memory level from individual memory lines
  • FIG. 9C - a schematic representation of the geometrical space requirement of a memory cell according to the invention
  • FIG. 10 shows a schematic illustration of the arrangement of memory cells and the routing of control lines in a memory level 5
  • FIG. ILA shows a plan view of six storage planes arranged perpendicular to the drawing plane and a wiring diagram of control lines within a storage block, which is carried out on the end faces of the storage planes.
  • FIG. 11B - a perspective view of a memory block, illustrating the wiring diagram of the control lines, 5
  • FIG. 12 shows a plan view of a memory block, illustrating the crossing laws of the wiring scheme according to the invention
  • FIG. 14 the logical structure of a data memory according to the invention, consisting of memory blocks combined to form memory segments,
  • FIG. 15 shows a perspective illustration of a wiring diagram according to the invention for a memory segment according to the invention
  • FIG. 16 shows a wiring diagram of the control lines a of a plurality of memory segments, 5 FIG. 17 - line elements with which the control lines a can be connected to several segments and to which external contact points can be connected,
  • FIG. 18 - a schematic representation of matrices MX and MY for controlling the lines a, b and ⁇ ,
  • FIG. 19A - a control circuit of the matrix MX
  • FIG. 20A - a control circuit of the matrix MY
  • FIG. 2OB - a table with the specification of voltage potentials of the control circuit according to FIG. 20A for several cases
  • FIG. 21A - a control diagram of the matrix MX
  • FIG. 21B - a schematic representation of the respective control circuit for operating the matrix lines ax and ay
  • FIG. 2IC - a control circuit for the matrix line axl
  • FIG. 22A - a control diagram of the matrix lines bx and by the matrix MY
  • FIG. 22B - a control diagram of the respective control circuit for operating the matrix lines by.
  • FIG. 22C a drive circuit for the matrix line byl.
  • FIG. 22D a circuit for the selection of memory segments,
  • FIG. 23 - a table with voltage potentials for the matrix lines ax, ay, bx and by for different cases for generating alternating voltages for reading data
  • FIG. 24 - a circuit for obtaining read data from measured AC voltage amplitudes
  • FIG. 25 an alternative embodiment of a memory cell in a side view
  • FIG. 26A - a memory cell in section according to FIG. 25 in the low-resistance state
  • Figure 26B - a memory cell in section according to Figure 25 in the high-resistance state
  • FIG. 27 an electrical equivalent circuit diagram of the memory cell according to FIGS. 25, 26A and 26B.
  • FIG. 1A shows a schematic illustration of a memory cell according to the invention.
  • the memory cell initially consists of a cavity 5 which is embedded in a layer of insulating material 11 and is closed by a second layer of insulating material 10. It is not essential for the functioning of the memory cell according to the invention that two layers 10 and 11 are provided; this only results from the production process. It is essential that a cavity 5 is provided which is surrounded by an insulating wall.
  • the cavity 5 contains an electrolyte and is preferably cylindrical. He has one Thickness a x and a diameter a 2 .
  • the insulating wall can for example consist of silicon dioxide (Si0 2 ). Such layers can be obtained in production terms by converting silicon oxide gas (SiO) into silicon dioxide.
  • capillaries 1, 2, 3 and 4 lead through layers 10 and 11, as the cross section according to FIG. IC shows.
  • the capillaries are filled with a metal and therefore act as electrodes.
  • Two capillaries, namely 1 and 2 form electrodes of the first type and the other two capillaries 3 and 4 form electrodes of the second type.
  • each capillary 1 to 4 (FIG. IC) is almost completely filled with a metal.
  • the process can be carried out electrolytically or with liquid metal under pressure.
  • FIG. IC shows, an external circuit of the memory cell is provided, consisting of a voltage divider, formed from the resistors Ra and Rb.
  • the resistor Rb is connected to a control line 6, the resistor Ra is connected to a control line 7.
  • the node between the resistors Ra and Rb is connected to an electrode of the first type 1.
  • the control line 7 is connected to the other electrode of the first type 2.
  • the control line 6 is connected to the two electrodes of the second type 3 and 4.
  • FIG. 1D shows the electrical equivalent circuit diagram of the original state of the memory cell shown in FIG. IC, ie before the first programming.
  • the resistances Rx, Ry and Rz resulting from the electrolyte must be taken into account become.
  • the resistor Rx is connected to the resistor Ra and the resistor Ry is connected in parallel to the resistor Rb.
  • the size of the resistors Rx, Ry and Rz depends in the original state of the memory cell essentially on the conductivity of the electrolyte, as well as on the contact area of the electrolytes with the metal in the capillaries 1 to 4 (FIG. IC) and Size of the cavity 5 ( Figure 1A and 1B).
  • control lines 6 and 7 are now subjected to a voltage as in FIG. 2A such that the negative potential is on the control line 6 and the positive potential is on the control line 7, in other words that the electrodes 3 and 4 are connected as cathodes electrolysis takes place.
  • the metal in capillaries 1 to 4 each acts as an electrode.
  • FIG. 2A shows the state which arises after a current II has flowed partly directly from the control line 7 and partly via the interconnected resistors Ra and Rb through the memory cell to the control line 6 for a predetermined time due to the applied voltage U.
  • the electrodes of the third type 3 and 4 were connected as the cathode and the electrodes of the first type 1 and 2 as the anode.
  • the two cathode potentials were the same and the anode potentials were different because of the voltage division carried out with the resistors Ra and Rb.
  • FIG. 2A shows, the electrolysis carried out caused a material transport, which leads to the electrodes 1 and 2, which were connected as anodes, having given off material. This material has been deposited on the electrodes of the second type 3 and 4.
  • the electrical equivalent circuit diagram shown in FIG. 2B exists in accordance with the state of the memory cell in FIG. 2A.
  • the resistors Ry and Rz of the original memory cell (FIG. 1D) have changed their value only slightly and are labeled Ry 'and Rz' in FIG. 2B.
  • the change in resistance of the resistors is negligible because the large distance a 2 between the electrodes of the second type has changed relatively slightly.
  • the total resistance between the control lines 6 and 7 has increased compared to the original memory cell because the resistor Rx is no longer connected directly in parallel to the resistor Ra, but is only connected to it via the additional, relatively larger resistors R V1 and R V2 .
  • the total resistance increases in that instead of the resistor Ry, the series resistors Ry 'and R V1 are connected to the resistor Rb and instead of the resistor Rz, the series resistors Rz' and R V2 are connected in parallel to the resistors Ra and Rb .
  • the state of the memory cell according to the invention shown in FIG. 2 is assigned to the logic state "0".
  • FIG. 3 shows how the memory cell can be reprogrammed into the logic state "1". If, for a limited period of time, a voltage U with the opposite polarity as in FIG. 2 is applied such that the control line 6 is connected to the positive pole and the control line 7 is connected to the negative pole of the voltage source, then part of the current flows from the terminal 6 via the electrodes of the second type 3 and 4, which are now connected as anodes. There is a material transport in the opposite direction, which leads to a conductive connection being established between the electrodes of the first type 1 and 2. The state shown in FIG. 3A is reached after a predetermined time.
  • the capillaries 3 and 4 and thus the mass contained in them are dimensioned such that the removal of mass from the electrodes of the second type to build the bridge between the electrodes of the first type does not result in as much material or mass at the Electrodes of the second type are removed so that there is a leak through which the electrolyte can flow out.
  • the distance a 2 between the electrodes of the second type 3 and 4 has increased accordingly.
  • FIG. 3B shows the electrical equivalent circuit diagram for the state "1" of the memory cell shown in FIG. 3A.
  • the resistance Rx has become almost zero, so that the resistance Ra is short-circuited, as a result of which the total resistance between the control lines 6 and 7 (terminals 6 and 7) is compared with the original state of the memory cell or with the logic shown in FIG State "0" has been significantly reduced.
  • the resistor Ry '' is connected to the resistor Rb and the resistor Rz '' is connected in parallel to the resistors Ra and Rb via the comparatively large resistor Rv 3 .
  • the resistances Rx, Ry ', Rz', Rvj and Rv 2 to be taken into account in the state "0" according to the equivalent circuit in FIG. 2B due to the electrolyte can be converted in connection with the resistors Ra and Rb so that there is a difference between the control lines lines 6 and 7 in FIG. 2B, for all the resistances specified there, a series connection results from the calculated resistances Ra 'and Rb', which is shown in FIG. 2C.
  • the calculated resistances Ra 'and Rb' differ only slightly from the resistances Ra and Rb shown in FIG. 2B.
  • the calculated resistance Rb ′′ essentially corresponds to the resistance Rb according to FIG. 3C.
  • the memory cell can also be read by measuring the total resistance of the cell with an alternating voltage.
  • the measured resistance value is compared with a predetermined value K, which can also be variable and depends, for example, on the temperature of the data memory.
  • K can also be variable and depends, for example, on the temperature of the data memory. The comparison result then delivers a "0" or "1" according to the state of the memory cell.
  • the conductivity of metals towards electrolytes generally differs by several orders of magnitude (10 5 ). This difference is particularly noticeable in a capillary when metal is replaced by an electrolyte or an electrolyte by metal.
  • the space in the metal is filled, it is equal to 0.2 ⁇ and if there is an electrolyte, it is equal to 20,000 ⁇ .
  • the resistances Rv x and Rv 2 contained in FIG. 2B rapidly increase from the point in time at which the degradation of the metal in capillaries 1 and 2 (FIG. 2A) begins. The same effect occurs with capillaries 3 and 4 (FIG. 3A) when the resistance Rv 3 indicated in FIG. 3B begins to form. Due to the relatively rapid increase in the resistance values of the resistors Rvj and Rv 2 (FIG. 2B) when writing a "0" and the same behavior of the resistor Rv 3 (FIG.
  • Electrochemical processes are very slow, for example compared to data storage in semiconductor memories.
  • the data memory according to the invention is provided for storing large amounts of data. Compared to conventional memories, in which only small amounts of data can be stored simultaneously or bit by bit, the amount of data that can be stored at the same time is much larger in the data memory according to the invention. This means that the amount of data that can be stored per unit of time is sufficiently large.
  • the following example illustrates the length of time t £ in order to set a memory cell from the state shown in FIG. 2A to the state shown in FIG. 3A. The following prerequisites are assumed.
  • the relative atomic mass of the metal e.g. of tin (Sn) is:
  • the mass m of the metal to be cut results from the density ⁇ of the metal and the volume V, which is a function of the quantities al, a3 and F.
  • the time period t t can be calculated according to Faraday law. Then the deposited mass m of the metal is:
  • the time t s for writing a byte is very much shorter than the time t £ previously reached.
  • the electrolysis must be carried out in such a way that no secondary processes, e.g. due to high current densities. It must be ensured that no solvent can be decomposed, so that no gaseous substances can form, no discharged particles react with the solvent, - no discharged anions react with the electrolyte, and no chemical intermediates are formed.
  • an electrolyte is used to which no solvent, for example water, has been added.
  • Salt melts are usually electrolytes that do not have to contain solvents.
  • the conductivity of molten salt is higher than that of salt solutions, but there is still a sufficiently large difference between the conductivity of the electrolyte and the metal in capillaries 1 to 4 (FIGS. 2A and 2B).
  • the melting point of most salts is far above room temperature (20 ° C). Own some salts however relatively low melting points.
  • Tin (IV) chloride SnCl_, melting point -33.3 ° C.
  • Tin (IV) bromide SnBr_, melting point 33.0 ° C.
  • Tin (IV) iodide Snl_.
  • the data memory can be programmed at a temperature that is significantly above room temperature. A change in the programmed Subsequently, data can only be made at an increased temperature of the data memory.
  • the electrolyte is converted from the liquid to the solid state, its volume decreases in most salt melts, so that no increased pressure can arise in space 5 (FIGS. 1A and 1B) of the storage cell.
  • the resistors Ra and Rb can consist of the materials used in semiconductor technology, the doping and switching being carried out in such a way that the same conductivity is present in both directions of each resistor.
  • FIG. 4A shows part of a matrix with the control lines Xj to x 4 and yi to y 4 as an example.
  • the x and y lines are each connected to a resistor at the crossing points.
  • the resistors are denoted by Rl to R16.
  • Each resistor represents a memory cell. If the memory cell, which is characterized by the resistor R7, which is shown with an increased strength, is to be reprogrammed, for example from 0 to 1, then a positive voltage must be applied to the control line x 2 relative to the line y 3 . To distinguish them, the lines x 2 and y 3 are marked more strongly than the other high-resistance connected lines. The current direction is marked with arrows for each of the resistors and each line. In addition, for the following considerations, the connection side of each resistor R1 to R16, which faces the x lines, is marked more strongly.
  • the matrix indicated in FIG. 4A is redrawn in FIG. 4B in such a way that the resistance combination lying parallel to the selected resistance R7 can be better recognized.
  • the one to resistor R7 Resistance lying in parallel and resulting from the other resistances of the matrix would be so small that it would almost short-circuit the selected resistance R7.
  • a more or less large current would flow through the memory cells, which would change the state of the cells to an unacceptable extent.
  • the current direction is compared in opposite directions with respect to the position of the strengthened resistance sides in the resistors which are not directly connected to the control lines x 2 and y 3 with the remaining resistors.
  • the two aforementioned disadvantages namely a small parallel resistance to R7 and current through unselected memory cells, can therefore be avoided by connecting two diodes upstream of each memory cell.
  • each resistor is connected on one side to the cathode of one and the anode of the other diode. Due to the two diodes which are connected upstream of each resistor, there are two separate control lines, the additional lines required being designated y x to y 4 .
  • the connections of the diodes, which are not connected to resistors, are made in such a way that the cathode connections are connected to the assigned y lines and the anode connections are connected to the assigned y lines.
  • diodes cannot be considered ideal switches.
  • a diode reverse current therefore flows across all resistors because a reverse voltage is present at at least one of the two diodes which are assigned to a resistor.
  • diodes can be used whose reverse current is extremely small. The order of magnitude of 1 nA is an achievable value.
  • FIG. 7A shows a top view of the structure of a memory cell within a matrix
  • FIG. 7C shows the arrangement of a memory cell within a matrix according to FIG. 7A in a perspective view.
  • the x control line is on the top and the y and y lines are on the bottom of the memory cell.
  • the resistors Ra and Rb on the top and diodes D1 and D2 on the bottom are only entered as a circuit symbol, but the position of the symbol indicates the space that the respective component can occupy.
  • the contact points of the resistors and diodes are marked on the underside with small circles and on the top with dots.
  • a via 8 is provided, to which the anode of the diode D1, the cathode of the diode D2 and a connecting line to the metal in the capillary 2, shown in broken lines, are connected on the underside.
  • the cathode of the diode Dl is connected to the y line and the anode of the diode D2 to the y line.
  • the resistor Ra connected to the plated-through hole 8 on the top of the memory cell is on its the side of which is connected to the metal in the capillary 1 and the resistor R2 connected to the x line.
  • the metal in capillaries 3 and 4 is connected to the x line on the top.
  • the resistors Ra and Rb and the diodes Dl and D2, including the plated-through hole 8, can form a compact unit which consists of a correspondingly doped semiconductor.
  • the spatial separation of the capillaries 3 and 4 results in a reduction in the current density at the electrodes, so that the intensity of the formation of "ion clouds" is reduced.
  • FIG. 7B shows the electrical circuit diagram of the memory cell shown in FIG. 7A. The state of the memory cell is symbolized by the status of the switch S1.
  • FIG. 8 shows part of a memory level which contains a multiplicity of memory cells. Each memory cell is constructed as indicated in Fig. 7A. For better illustration, the connections to the capillary 2 are shown in FIG. 8 as a dashed line and the resistors Ra and Rb and the diodes D1 and D2 as a symbol. The components of the uppermost memory cell are labeled for comparison with the other cells. The cavities 5 are not entered for a better overview.
  • FIG. 9A the data memory is shown schematically with its external dimensions, length 1, width b and depth t. It contains the memory levels E 1 to E u , the position of which within the memory is marked and the number of which is u.
  • a storage level E x selected from the data storage which is shown in FIG. 9B, illustrates how the storage cells are arranged in each storage level.
  • the level is formed by memory cells which are arranged one below the other in rows L_ to L z .
  • the memory cells are identical to one another and have a cuboid shape. They each have four identical rectangular and two square sides and are arranged and joined together so that the square sides of the memory cells form a total of two opposite, equally large, flat surfaces.
  • the number of rows per memory level is z and that of the memory cells per row alternately v and v-1.
  • the first line L_ in FIG. 9B contains the memory cells Si to S v .
  • One of the memory cells S x is shown in Fig. 9C.
  • the side length of each of the two square surfaces is a and the thickness d.
  • the dimensions of the memory cell S x result from the dimensions a and d. Assuming that the dimensions b and 1 of the data memory (FIG. 9A) already represent the space usable for memory cells, the number u of the memory levels is:
  • the depth t of the data memory results from:
  • FIG. 10 shows a memory level in which the x lines are routed to one side and the y and y lines to the other side of the memory level. Each y and y line are symbolized by just one line.
  • the x, y and y lines are identified as lines.
  • the associated y and y lines are each combined into a line.
  • the memory cells are marked with dashed lines.
  • the x and y, y lines intersect at the center of each memory cell.
  • the left and right marginal areas are separated from the middle part of the storage level by a line with a stronger line.
  • All x, y and y lines of all memory levels of the data memory must be connected to one another in such a way that each memory cell has only one active line pair, i.e. an x line and a y or y line, can be controlled.
  • the x lines are e.g. connected to each other on the top of the memory so that each x-line only crosses each y-line pair once.
  • all x lines of each storage level must be connected to each other at a distance of z (number of lines / storage level). The following number h of lines, which form a group, then results for a storage level.
  • FIG. 11A shows how multiple superimposed connecting lines per memory level for connecting the x lines can be avoided.
  • the entire data memory is divided into memory blocks, one memory block containing h memory levels.
  • the six storage levels in FIG. 11 are arranged perpendicular to the drawing level and are each organized as shown in FIG.
  • the successive line groups which are each assigned to an original storage level in FIG. 11A, are denoted by A to F.
  • Two wiring levels are required to connect the x lines of the geometric memory levels.
  • the x lines of each original storage level are interconnected according to their ordinal number.
  • the connecting lines to the underlying second wiring level are plated through and connected there to the lines of the first wiring level so that the line groups of each original memory level are continued.
  • the wiring diagram is used on the top and bottom of the data memory because, as will be described later, the x-lines are partly led to the top and partly to the bottom of the memory.
  • the memory cells of the geometric planes are combined, so to speak, into electrically organized planes.
  • Each line group of each memory level is arranged in the adjacent memory level within a memory block, geometrically offset by the width of a line group.
  • all x lines which have the same position within each line group and belong to the same line group are connected to one another.
  • the connections that can be made in one plane are indicated by solid lines.
  • the respective connections of the x lines of the memory levels are marked with dots. net.
  • the connections in the edge areas of the storage levels are indicated by dashed lines.
  • FIG. 11B The end part of the first and the beginning part of the adjacent storage level is shown three-dimensionally, the lines of the line groups F of the two storage levels, as indicated in FIG. 11A, having to be connected to one another. Between the storage levels there are two insulating layers 45 and 46. Between the layers there are connecting lines to which the x lines of line group F of storage level 1 and those of storage level 2 are connected, the connections at storage level 1 in the connecting level of the remaining x lines and at storage level 2 are executed on their edge opposite the level. For a better spatial idea, the last y line pair (y 18 , Yi ⁇ ) is shown in the storage level 1 and the first y line pair (y lf yj) is shown in the storage level 2.
  • the memory cell Sp a encircled in FIG. 12 is activated.
  • the x and y, y lines are each folded out of the perpendicular storage plane into the drawing plane of FIG. 12 in order to make them representable.
  • six storage levels are arranged in the actually existing spatial arrangement perpendicular to the drawing level of FIG. 12, but folded 90 ° into the drawing level of FIG. 12, to make it representable.
  • This example shows that it is possible to uniquely assign control lines a and b, b to a memory cell. The individual storage levels are shown shifted from one another in FIG.
  • FIG. 13 shows how the x, y and y lines of a memory level are led to the top and bottom of the data memory.
  • the line routing concept presented in FIG. 13 is a further development of the basic concept shown schematically in FIG. 10. In contrast to
  • Control lines b and b are available on the surface of the underside of the data memory for external contacting. On the other hand, for reasons of space for later contacting, it makes sense for the same number of contact points to be arranged on the top and bottom of the memory, each having the same distance from one another. Since there is a larger number of y and y lines than there are of x lines, it makes sense to first connect a part of the y lines to control lines b on the upper side in accordance with their ordinal number , as will be described below, per
  • Data storage segment are each led to the bottom of the data storage.
  • the control lines b arranged on the top are symbolized by short dashed arrows, the tips of which point towards the bottom of the memory.
  • FIG. 14 shows the schematic structure of a data memory. It consists of several memory segments 21, each of which contains an equal number of memory blocks 20.
  • the drive lines b and b which can be connected to the underside of the data memory and which are connected to y and y lines are indicated on the left in FIG. 14 and the drive lines a which are connected to x lines are located on the upper side.
  • the number of b and b lines is twice as large as the number of a lines.
  • control lines a and b and E In order to obtain the same number of control lines a and b and E as possible when linking memory blocks that complement each other to form a data memory, it is necessary first of all to connect the x lines of several memory blocks with those of the y- and y- Cross lines of the first memory segment. This increases the number of control lines a. In the further memory segments, all x lines connected to the control lines a are crossed with further y and y lines which are connected to further control lines b and E, whereby the number of control lines b and E per memory segment increases by v. In FIG. 14, the control lines a of the first memory block are labeled aj to a v .
  • the last memory block contains the control lines a (m _ 1) v + 1 to a ⁇ .
  • the control lines b of the first memory segment are designated b x to b v .
  • the control lines b of the last segment are b ⁇ , ⁇ ,. ⁇ To b nv .
  • the designation of the control lines E corresponds to that of the control lines b.
  • the total number of control lines a is equal to the total number of control lines b plus E if the number m of memory blocks per memory segment is twice as large as the total number n of memory segments.
  • the total number Ga of the control lines a depends on m, the number of memory blocks per memory segment and on the number v of memory cells per row of a memory level.
  • the total number Gb of the control lines b and E is:
  • the number m of memory blocks per memory segment is the same:
  • Ga 159 744
  • Gb 159 744
  • the number n s of the usable memory cells of the data memory results from the number n f of the usable memory cells per memory level and the number u of the memory levels. This means:
  • n s n f * u
  • the number of unusable memory cell spaces in the edge region of the memory levels is relatively small because the depth is small compared to the length and width dimensions of the data memory.
  • the total number of memory cells is therefore
  • the storage capacity of the data storage is with
  • FIG. 15 schematically shows a three-dimensional data storage segment 21 with a view of the underside, around which
  • control lines b and E The storage levels in the storage segment are designated by E.
  • a part of the y lines of the memory levels is connected to control lines b on the top of the memory segment.
  • these control lines b running in the wiring plane 24 are guided with an odd number at the edge of the memory segment from the top to the surface of the underside of the memory segment and are forwarded there approximately to the middle of the surface.
  • control lines E running on the underside of the memory segment in the wiring level 25, the ordinal number of which is also odd, are guided to and on the surface of the memory segment in such a way that they run in parallel with the control lines b coming from the top and with them Form line pairs with the same ordinal number.
  • the control lines b and E with an even atomic number are also carried in pairs from the wiring level 25 to the surface of the underside of the memory segment and are passed on there approximately to the middle. All control lines b and E each have a contact point on the surface of the memory segment.
  • the contacting point 23 of the control line b 10 and the point 22 of the line E 10 are entered in FIG. 15 as an example.
  • the wiring level 26 represents the wiring level of the control lines x.
  • the level 27 contains cross-segment conductor elements, the description of which will follow.
  • Memory blocks in all memory segments must have several each Lines, the number of which is equal to the number of memory segments, are routed one above the other.
  • FIG. 17 shows the electrical diagram of the line routing for the control lines a v / a 2v to a_m shown in FIG. 16 as an example.
  • Conductor elements can be used which are perpendicular to the storage levels, form an angle of 90 ° with them, have conductor tracks on both sides and are insulated from one another.
  • the drive connection lines and on the other side the plated-through connections to the drive line connections a of the memory blocks and to the outer contact points, as indicated, for example, by 14 and 15, are arranged on one side of each conductor track element.
  • the connections to the control lines a and to the outer contact points 14 and 15 are shown in dashed lines.
  • the area p of a contact point is
  • the side length w of a contact point is:
  • the dimensions of the contact area p is a function of the depth dimension t of the data memory.
  • t increases, the number z of memory cell rows increases in each memory level. Fewer x lines can then be connected to one another, which increases the number of control lines a.
  • the control lines a are connected on the top and the control lines b and E on the underside of the data memory to the outside with contact areas such that each area is assigned to a control line and that the adjacent contactable areas on each side of the data memory are used for insulation have the same distance from each other.
  • the data memory is constructed in a planar manner in order to be able to use the largest possible area for contacting. All contact areas of the data memory must be connected to the contact areas of control electronics.
  • the control electronics can be permanently installed in a device, so that the data memory can be replaced with each device.
  • Each contact area of the data memory must be opposed to a contact area of the control electronics.
  • a film can be arranged on each side of the memory between the contact surfaces of the data memory and those of the control electronics.
  • the film consists of an insulating material and contains particles of a conductive material that have no con in the film itself have tact with each other, but can be contacted on both sides of the film.
  • each contactable particle area must be so small that there is definitely no connection between the contact areas of the data memory or the control electronics.
  • the security of contact of the conductive particles in the film with the contact surfaces of the data memory to be connected and the associated surfaces of the control electronics can be increased by permitting pressure on both
  • both contact foils are part of each storage device, the contacting of all particles to the contacting surfaces of the data storage device can be replaced by fixed connections.
  • the wear of the contact foils is then reduced when the memory is replaced, because each memory has contact foils and the device for contacting only needs to contain the contact surfaces of the control electronics.
  • the control electronics are part of the data memory, much fewer contact points are required to control the memory. The depth of the memory can then be increased even further.
  • the control lines a are operated using a matrix MX and the control lines b and E are operated using a matrix MY.
  • a section of the two matrices MX and MY with part of a memory level is shown as an example in FIG. 18.
  • the matrix MX and via the matrix lines bx x to bx 5 and by x of the matrix MY the connected part of the drawn memory level with the control lines aj to a 5 and b is to b 5 , which are drawn more, and Ei to E 5 , controllable.
  • Fig. 18 all line crossings in the matrices MX and MY are marked with a square point.
  • the dots symbolize circuits which are identical to one another within each matrix.
  • 19A shows the circuit used in the matrix MX.
  • the inputs of the circuit are labeled ax and ay and the output is labeled a.
  • the input ax is connected via a series resistor 54 to the gates of the transistors 50 and 52 and the input ay to the source connections.
  • Output a is connected to the anode of diode 51 and the cathode of diode 53.
  • the cathode of the diode 51 is connected to the drain connection of the transistor 50 and the anode of the diode 53 is connected to the drain connection of the transistor 52.
  • the transistor 50 can be used to switch a positive voltage at output a, which comes from a control line E (FIG.
  • MOS-FET transistors In the neutral state there is half the operating voltage at the inputs ax and bx, ie + 2.5V in the example mentioned above.
  • MOS-FET transistors which have an increased gate / source threshold voltage (2.1 to 4.0 V). In the previous example, a threshold voltage is assumed, which is approximately 3V.
  • the transistors also have the advantage that only a small reverse current flows (a few nA) before the threshold voltage is reached.
  • the N-channel transistor 50 and the P-channel transistor 52 are each non-conductive if the gate / source voltage based on the example is within the limits ⁇ 2.5V.
  • the diodes 51 and 53 in the transistors 50 and 52 prevent their inverse diodes from becoming conductive. In addition, the blocking current is reduced with each blocked transistor.
  • FIG. 20A shows the circuit with which the drive lines b and E are operated in accordance with the matrix MY (FIG. 18).
  • An N-channel MOS-FET transistor 60 and a P-channel MOS-FET transistor 62 are used.
  • the gates of the transistors are connected to one another and connected to the input bx via a series resistor 64, and the connected source connections form the input by.
  • the drain connection of the transistor 60 represents the output E and is connected to the positive operating voltage via the resistor 61.
  • the drain connection of the tran forms accordingly sistor 62, which is connected to ground potential via the resistor 63, the output b.
  • the switching functions of the transistors 60 and 62 are carried out via the inputs bx and by as in the circuit shown in FIG. 19A.
  • a conductive transistor 60 there is almost ground potential at the output E instead of the operating voltage
  • the operating voltage is almost at the output b instead of the ground potential. If both inputs bx and by are selected, the outputs b and E have either ground or operating voltage potential levels depending on the polarity of the signals at the inputs.
  • control lines b and E of the data memory segments can be given an average operating voltage potential (+ 2.5 V), for which there is currently no data traffic.
  • the operating voltage and the ground potential indicated in FIG. 20A can be set to + 2.5 V.
  • the connections of most of the memory cells are then at a potential of + 2.5 V, so that no diode reverse current can flow through these cells.
  • the diode blocking current that arises from data traffic in a memory segment is then negligibly small.
  • FIG. 21A shows the diagram of the matrix MX indicated in FIG. 18. Based on the example ZAB, it consists of the
  • Matrix lines ax to ax 400 which are in line with lines ayi to cross ay ⁇ 00 .
  • the number of matrix lines ax is equal to the number of bx lines, because in this case the total number of necessary matrix lines is lowest.
  • the lines ax, to ax 400 can be driven.
  • the same circuit can be used to drive lines ayj to ay_ 00 .
  • a shift register 100 is provided, the input of which is connected to the output of the last flip-flop. With a set pulse N x at terminal 101, all flip-flops of the shift register are set to "0" and the first flip-flop to "1", and with the clock signal Tj at terminal 102, the set "1" can be shifted in a circle become.
  • the number of clock pulses can be used to determine which matrix line ax is to be selected.
  • Circuits SAXi to SAX_, 0 o are connected to the outputs of the shift register 100 and are constructed identically to one another and to which an enable signal Fi is also supplied by the terminal 103 and a polarity signal Pj by the terminal 104.
  • the inputs of the circuit shown in FIG. 21B and the other circuit for controlling the matrix input lines of the matrices MX and MY can be controlled with a microcomputer.
  • FIG. 2IC shows how the circuit SAXj is constructed, for example. It consists of a gate 105, the output ax of which can be switched to a high resistance with the output of an AND gate 106.
  • the output ax, of the gate 105 only becomes low-resistance if the enable signal Fi is "1" and the circuit with the shift register 100 has been selected, ie the output signal A x of the shift register 100 is then "1", otherwise a potential is established at the output of gate 105, which is determined by high-resistance resistors 107 and 108 of equal size. With the potential P ⁇ at the terminal 104, the level of the output signal of the gate 105 is controlled when the latter is switched to low resistance.
  • FIG. 22A shows the diagram of the matrix MY indicated in FIG. 18. Based on the example ZAB, it consists of the matrix lines bx. x to bx 208 and the lines by x to by_, 992 . To operate the control lines b and E of each memory segment, 13 matrix lines bx intersect with 384 matrix lines by, so that there are 4992 crossing points per memory segment. The division of the matrix lines bx and by enables a sufficiently large number of data bits (384) to be written at the same time and 16 or 32-bit words, for example, to be subsequently read.
  • the matrix lines bx, to bx 208 are driven by a circuit which is constructed in principle like the circuit shown in FIG. 21B, but in which the shift register length is 208 bits.
  • Each matrix line bx : to bx 208 is assigned to a certain number of clock pulses that the shift register receives.
  • FIG. 22B shows a circuit with which data can be written and read via the matrix lines byj to by 992 .
  • 16 shift registers 216 to 231 are provided, each of which is 384 bits long. Each shift register is assigned to a storage segment. With the input signals E x to E 16 at the terminals 250 to 265, one of the shift registers 216 to 231 can be selected for writing or reading. Data inputs D to D 16 are assigned to the shift registers at terminals 200 to 215, via the data with that at terminal 232
  • Clock signal T 2 can be read if this was released with one of the signals E x to E 16 .
  • the selected part of the memory (384 bits) is first read in order to determine which memory cells have to be reprogrammed. It can thus be avoided that the state of cells which have already been correctly described is changed further.
  • the writing of the selected memory part is divided into two successive processes. During the first write process, all memory cells are reprogrammed. mized, which must be changed from the state "0" to "1” and in the second write operation all memory cells are reprogrammed, the state of which is to be changed from “1" to "0". Accordingly, a "1" is inserted into the selected shift register during the first write operation wherever a
  • each of the circuits also receives the polarity signal P 3 specified at terminal 249 and, in accordance with the assignment to one of the shift registers, one of the signals FS to FS 16 / which are derived from the signals Ej to E 16 .
  • the circuits SBY : to SBY_, 992 are constructed identically to one another.
  • the output of gate 302 can be switched to high and low resistance with the output signal of AND gate 301.
  • the potential of the matrix cable by ! is equal to half of the operating voltage when gate 302 is switched to high impedance, because high-resistance resistors 304 and 305 have the same value.
  • the gate 302 is only switched to low impedance if the selected memory cells are to be reprogrammed during the write operation, ie the output signal Bj of the shift register 216 (FIG. 22B) is then equal to "1" and the signal FS X is also equal to "1". This means that the shift register 216 is selected and the previous reading of the data into the shift register 216 has ended.
  • the polarity of the signal P 3 at the terminal 249 is assigned to the write processes and is the opposite for all first write processes compared to that for all second write processes.
  • the polarity of the output signal by is the same as that of the signal P 3 when the gate 302 is switched to low resistance.
  • 22D is shown how the signals E x to E 16 for selecting the shift registers 216 and 231 shown in FIG. 22B and the signals FS ! to FS ⁇ 6 for selecting the circuits SBYi to SBY 4992 assigned to the shift registers.
  • the output of the last flip-flop of the 16-bit shift register 400 is connected to the D input of the first flip-flop, which can be set at terminal 401 with a pulse N 3 .
  • All other flip-flops of the shift register are set to "0" with the pulse N 3 , so that the set “1” can then be shifted in a circle with the clock T 3 at the terminal 402.
  • the number of clock pulses can be used to determine which of the output signals Ej to E 16 should become “1".
  • the output signals E to E 16 of the shift register 400 are each linked via AND gates 405 to 420 with a signal F 3 at the terminal 403.
  • the signal F 3 is always switched to "0" when data is read into one of the shift registers 216 to 231 (FIG. 22B) or when the state of the shift register 400 is changed.
  • the write duration for the matrix MX (FIG. 21A) depends on the signal Fi (FIG. 2IC) and for the matrix MY (FIG. 22A) on the signal F 3 (FIG. 22D). Both signals, F, and F 3 , must become “1" at the same time and then again "0".
  • the write duration results from the time at which the signals Fi and F 3 are equal to "1". If, as in the numerical example mentioned above, it takes 189.32 ⁇ s to write a memory cell and 384 memory cells are programmed in two writes, the following time t s is necessary to write an 8-bit word:
  • the time to write any part of the memory is significantly less than conventional mass storage devices.
  • the time required for writing per bit can be increased further by increasing the number of memory cells programmed at the same time.
  • one of the shift registers 216 to 231 (FIG. 22B) is selected with the circuit shown in FIG. 22D, as is the case when writing.
  • a data pattern is read into the selected shift register, which consists of leading zeros and then a certain number of consecutive ones. The number of ones is equal to the number of bits that can be read simultaneously. The number is selectable. With e.g. 32-bit words result in 12 words with 384 bits per shift register.
  • the ones are moved to the position to be read in the grid of the number of ones.
  • the signal F 3 (FIG. 22D) must be equal to 0.
  • Case 23 shows a table in which cases 1 to 3 are distinguished.
  • the potentials of the matrix lines ax, ay and bx, by and the control lines a, b and b are given.
  • Case 3 is to be regarded as a state of rest. where no data is read.
  • cases 1 and 3 In order to generate alternating voltages, cases 1 and 3 must be set alternately for the same period of time. The following assignment exists for the polarity control of the matrix lines:
  • Matrix line polarity control line ax Pi (Fig. 21B and 21C) ay principle as for ax bx principle as for ax by P 3 (Fig. 22B and 22C)
  • Each of the alternating currents flows via one of the circuits SBYi to SBY 4992 not directly to the negative pole of the operating voltage with ground potential, but via one of the resistors 500 to 531.
  • the operating voltage connections of those circuits SBYi to SBY A992 leading to ground potential are connected to one another and passed over one of the resistors 500 to 531, which cannot be selected at the same time during reading.
  • the resistors 500 to 531 are selected to be equal to one another and so small that the operating voltage drop for the circuits SBYi to SBY 4992 is negligibly small.
  • the circuits 564 to 595 each of which contains an AC voltage amplifier and a comparator circuit, are supplied with the AC voltage present at the resistors 500 to 531, which is proportional to the flowing AC currents.
  • a comparator circuit is used, which also rectifies of the amplified voltage, differentiate whether the measured voltage amplitude exceeds a threshold value K specified at terminal 560 or not.
  • the data read is made available at terminals 600 to 631 in the form of a "0" or "1".
  • the threshold value K at the terminal 560 can be a function of the temperature that the data storage device currently has for better decision certainty.
  • FIG. 25 shows an alternative embodiment of a storage cell, in a side view
  • FIGS. 26A and 26B show sections along the line AB in FIG. 25.
  • the cavity 5 filled with an electrolyte is located between two insulating layers 10 and 11, only two capillaries 61 and 62 are connected, which differ significantly from one another in terms of the size of their cross section.
  • the capillary 61 with a smaller cross section is connected as a cathode, while the capillary 62 with a larger cross section is connected as an anode.
  • the capillary 61 with a smaller cross section now acts as an anode and delivers mass to the capillary 62 with a larger cross section, which is connected as the cathode.
  • the capillary 61 with a smaller cross-section has a higher specific resistance per unit length than the capillary 62 with a larger cross-section, this causes a significant change in the resistance of the memory cell.
  • the removal of material from the electrode with a smaller cross-section leads to a relatively greater change in length of the electrode itself than the increase in material than the larger cross-section 62 connected as an electrode connected as a cathode. Since the electrode 61 with a smaller cross-section has the higher specific resistance and above If the mass balance is shortened more than the other electrode is extended, the differences in the 26A and 26B clearly show the states with regard to the resistance.
  • Such a change in resistance can also be used to store information content, with such a memory cell construction also being able to store analog intermediate values.

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  • Semiconductor Memories (AREA)

Abstract

La présente invention concerne une nouvelle mémoire de données constituée d'éléments de données, pour le stockage de l'un des deux états possibles représentant des informations logiques. Une cellule de mémoire selon l'invention est caractérisée en ce qu'elle a un espace creux (5) rempli d'un électrolyte, ceint par une paroi non électroconductible (10.11); cette paroi comprend au moins trois tubes capillaires (1, 2, 3, 4) reliant l'espace creux à des points de contact extérieurs; les tubes capillaires sont remplis d'un métal et font office d'électrodes, deux tubes capillaires (1, 2) au moins étant des électrodes du premier type (1, 2) et l'autre tube capillaire au moins (3, 4) étant un électrode du second type (3, 4); les deux faces polaires des tubes capilaires formant les électrodes du premier type (1, 2) sont si rapprochées l'une de l'autre et les dimensions d'au moins un autre tube capillaire formant un électrode du second type (3, 4) sont telles que la masse de métal formant l'électrode du second type, ladite électrode du second type ayant la fonction d'anode et les deux électrodes du premier type la fonction de cathode, suffit à former une connexion conductible par métal entre les faces polaires des électrodes du premier type.
PCT/DE1996/000368 1995-04-27 1996-03-01 Memoire de donnees WO1996034394A1 (fr)

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US6132643A (en) * 1998-01-06 2000-10-17 Pavel; Eugen Fluorescent photosensitive vitroceramics and process for the production thereof
US6228787B1 (en) 1998-07-27 2001-05-08 Eugen Pavel Fluorescent photosensitive glasses and process for the production thereof

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DE102004041894B3 (de) * 2004-08-30 2006-03-09 Infineon Technologies Ag Speicherbauelement (CBRAM) mit Speicherzellen auf der Basis eines in seinem Widerstandswert änderbaren aktiven Festkörper-Elektrolytmaterials und Herstellungsverfahren dafür

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6132643A (en) * 1998-01-06 2000-10-17 Pavel; Eugen Fluorescent photosensitive vitroceramics and process for the production thereof
US6228787B1 (en) 1998-07-27 2001-05-08 Eugen Pavel Fluorescent photosensitive glasses and process for the production thereof

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