WO1996013779A1 - Systeme de multiprocesseur - Google Patents

Systeme de multiprocesseur Download PDF

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Publication number
WO1996013779A1
WO1996013779A1 PCT/JP1995/002232 JP9502232W WO9613779A1 WO 1996013779 A1 WO1996013779 A1 WO 1996013779A1 JP 9502232 W JP9502232 W JP 9502232W WO 9613779 A1 WO9613779 A1 WO 9613779A1
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WIPO (PCT)
Prior art keywords
memory
processor
memory access
hierarchy
data
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Application number
PCT/JP1995/002232
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English (en)
Japanese (ja)
Inventor
Hajime Takamatsu
Original Assignee
Nkk Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nkk Corporation filed Critical Nkk Corporation
Priority to US08/817,934 priority Critical patent/US6131153A/en
Publication of WO1996013779A1 publication Critical patent/WO1996013779A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory

Definitions

  • the present invention relates to a multi-processor system composed of a plurality of data processors. Background technology
  • a conventional multiprocessor system is a single system node composed of an address bus, a data bus, and a control bus. By distributing the data to a plurality of data processors interconnected via the CPU and performing desired data processing, the processing time as a whole is shortened. By the way, in a conventional multiprocessor system, a plurality of data processors mutually share a system bus. It has a relationship. For this reason, multiple task sets obtained by decomposing the desired data processing are assigned to these data processors, and the system processing is performed. Scheduling must be performed to determine the processing order of the processors so that the noise can be used efficiently. . This scheduling is performed using a multi-processor system-specific operating system program. It is done.
  • the above-mentioned manipulation processor system is limited to the development and application system capabilities of the application software. It has the following shortcomings that occur when it is constrained. In other words, the limit of the system capability is to increase the number of processors and to increase the number of processors. Increasing the number of services will change the scheduling environment, so a new operating system program will be implemented. It must be prepared. In addition, this new operating system program implements some of the existing application software. There is power to make it impossible. In such a case, some application software will be compatible with the new operating system programs. It must be rewritten. Therefore, extending system capabilities is difficult except for special uses that do not need to take into account the useful use of software assets.
  • the purpose of the present invention is to provide a multi-processor system that can increase the number of data processors without changing the operating system program.
  • a processor system is to be provided. Disclosure of the invention
  • the main program that stores the application program and the operating system program It includes a memory section and at least one data processor, each of which must be updated according to the programming system. Connection between the multiple processor sections for distributing and processing the retention program, and between the multiple processor sections and the main memory section.
  • the system memory and the main memory section, with the main memory section at the top level, are located on the main memory section and the processor sections. It is inserted into the system nodes to set the layer order and enable data transmission between the layers and below, and each one below the corresponding one layer.
  • the main memory section is divided into the main memory section and the main memory section.
  • a hierarchy is set in the multiple processor sections and inserted into the system node to enable data transmission between the layers.
  • Monitor memory access requests from the lower hierarchy than the corresponding one hierarchy, and this memory access request is monitored for the corresponding hierarchy. It is configured to control to reserve this memory access request when it interferes with the memory access.
  • This control allows each processor section to interfere with memory access by the upper-level data processor. It is possible to access the main memory via the system memory provided for the user.
  • the operating system program does not need to perform the conventional scheduling. Therefore, if the maximum number of hierarchies is set in advance in the operating system program, the operating system can be operated within this number of hierarchies. The number of processors can be changed without changing the program.
  • FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention.
  • FIG. 2 is a block diagram showing an example of the configuration of each gate section shown in FIG.
  • FIG. 3 is a state transition diagram showing the operation of the gate-and-air unit shown in FIG.
  • FIG. 4 is a diagram showing a change in memory access information in the buffer memory shown in FIG.
  • Fig. 5 is a diagram for explaining the role of the operating system program stored in the main memory shown in Fig. 1. .
  • FIG. 6 is a diagram showing a modified example of the multiprocessor system shown in FIG.
  • FIG. 7 is a view showing a modification of the multiprocessor system shown in FIG. Best mode for carrying out the invention
  • FIG. 7 is a view showing a modification of the multiprocessor system shown in FIG. Best mode for carrying out the invention
  • FIG. 1 shows a block diagram of this manifold processor system.
  • This multiprocessor system is composed of a system board 1A-1E, a gateway section 2A-2E, and a data processor 3 — It is equipped with 6, and main memory 7.
  • System Nos. 1B-1E are provided corresponding to data processors 3-6.
  • Each of these system buses 1 A to 1 E includes an address signal line, a data signal line, a control signal line, and the like, and is different from the conventional system bus. Similarly, independent data transmission can be achieved.
  • Main memory 7 is used to store application programs, operating system programs, etc.
  • the data processors 3-6 are controlled by the operating system program, and the rear processor program is controlled by the operating system program. Used to distribute the program.
  • the data processor 3-6 and the main memory 7 are the interface section that manages these I / Os to the intelligent. It has 3 A, 4 A, 5 A, 6 A, and 7 A.
  • the gateway sections 2A to 2E are located on the main memory 7 and the data processor 3-6 with the main memory 7 at the top. It is inserted into system nodes 1A-1E to set the layer order and enable data transmission between layers and layers. That is, the gateway section 2A is connected to the main memory 7 and further allocated to a lower hierarchy than the main memory 7. It is connected to the gateway section 2B via the connected system node 1A-1E. The gateway section 2B is connected to the data processor 3 and further has a data processor. It is connected to the gateway unit 2C via the system nodes 1A-1D assigned to the lower hierarchy than 3. The gateway unit 2C is connected to the data processor 4, and is further allocated to a lower hierarchy than the data processor 4. It is connected to the gateway 2D via the system 1A-1C.
  • the gateway section 2D is connected to the data processor 5, and further allocated to a lower hierarchy than the data processor 5. It is connected to the gateway section 2E via the buses 1A and 1B.
  • the gateway section 2E is connected to the data processor 6, and further connected to the system node 1A.
  • Each of these gateway units 2A-2E monitors memory access requests from the lower hierarchy than the corresponding one hierarchy, and monitors this memory. When a request for access interferes with memory access in the corresponding layer, control is performed to suspend the request for memory access.
  • FIG. 2 shows a configuration example of each of the gateway sections 2B-2E shown in FIG. 1, and FIG. 3 shows a configuration example of the gateway section 2A.
  • the number of system nodes connected to these gateways decreases as the hierarchical order becomes lower. In Figures 2 and 3, this number is represented by n instead of the system BO-Bn force system 1A-1E. You.
  • Each gateway section includes a transmission mission gate TG for gaining system BO-Bn and a corresponding floor, respectively.
  • a memory BF that holds the memory access information of the layer and a memory that is supplied from the lower hierarchy to the system memory B11-Bn
  • the access request is checked against the contents of the buffer memory BF, and this check is performed.
  • a control circuit CNT for controlling the transmission gate TG based on the result.
  • the control circuit CNT is used when the buffer PC of the corresponding hierarchy is used for flushing the buffer memory BF and performing other exceptional operations. That is, control is performed to interrupt the operation of the outlet sensors 3, 4, 5, 6) or the main memory 7 shown in FIG.
  • the processor PC does not perform data transfer with the upper layer via the system node B0, and transfers data with the lower layer via the system node B11-Bn. Perform data transfer.
  • Each of the processor PC and the main memory 7 is connected to the transmission mission gate TG via the system node B0. It is done.
  • the transmission gate TG not only connects B1-1 connected to upper debris to B1-1 connected to lower hierarchy, but also At the highest level, the system nos that are in the same hierarchy as ⁇ are replaced by the system buses that are connected to the lower levels.
  • the system node 1 ⁇ is set up in the ⁇ to add the lowest level ⁇ .
  • the transmis- sion gate TG is an extension for adding a processor and an extension for adding a main memory. It has a gate.
  • the system nos 1A-1E extending to the upper part of the gateway 2 ⁇ is used when main memory is added.
  • the control circuit CNT is a decoding circuit DE1, a buffer I / O control circuit BC, a selector circuit SL, a decoding circuit DE2, and a comparison circuit. It has a circuit CM, a judgment circuit DT, and a gate switch control circuit GS.
  • the decoding circuit DE 1 is a memory that decodes the nos signal supplied to the system node B 0 in the corresponding layer and stores it in the memory. Detect access request. This memory access request is a buffer I / O control circuit BC consisting of address, data, and access type signals. Provides memory access information corresponding to the memory access request obtained from the decoding circuit DE 1 sequentially. Store or renew in BF.
  • the memory access information is the address information AD indicating the address accessed in the main memory 7, the write operation, and the write operation.
  • Access format information which represents one of the read operations
  • Access frequency information which represents the number of access times of the data N
  • the memory It consists of valid flag information V, which indicates whether the access information is valid or invalid.
  • the buffer I / O control circuit BC updates the contents of the buffer memory BF to reflect the access status of the main memory 7. You.
  • the selector circuit SL is connected to the system nodes B 1 —B n on the lower hierarchical level side from the transmission mission gate TG, and A nos signal is selectively extracted from these system nodes B11-Bn.
  • the decoding circuit DE 2 requires a memory access by decoding the bus signal extracted by the selector circuit SL.
  • This memory access request consists of address, data, and access-type signals.
  • the memory access request is supplied to the comparative circuit CM.
  • the address signal for requesting memory access is also supplied to the knocker I / O control circuit BC.
  • Buffer I / O control circuit BC is a decoding circuit DE 2 Reads memory access information and memory access information corresponding to the response signal and supplies it to the comparison circuit CM.
  • Comparison circuit C is a decoding circuit DE 2 Reads memory access information and memory access information corresponding to the response signal and supplies it to the comparison circuit CM.
  • the M compares the memory access request of the decoding circuit DE 2 with the memory access information of the buffer memory BF and the like.
  • the judgment circuit DT receives the collation result from the comparison circuit CM, and decides on how to approve the memory access request in accordance with the collation result. You.
  • the gate switch control circuit GS receives and transmits the transmission mission gate TG based on the judgment result from the judgment circuit DT. Control the direction. In other words, if the collation result indicates that the memory access is approved, the transmission mission gate TG corresponds to the memory access request. It is opened in the corresponding transmission direction of the system.
  • the gate switch control circuit GS controls the processor PC of the corresponding layer and the processor PC (or the PC) through the decode circuit DE1.
  • This interface uses the gate switch control circuit GS to transmit information about the transmission gate TG's gating. Forces are configured to capture.
  • the determination circuit DT enables or disables the operation of the processor PC (or the main memory 7) of the corresponding layer by supplying the ready signal READY.
  • the interrupt signal INT is disabled if the collation is disabled due to flushing of the reference result memory BF or other special operations. Enables the exception operation of the processor PC.
  • the decoding circuit DE 2 has the memory power ⁇ Connected to the gate switch control circuit GS to supply a signal for freely passing the noise signal that accesses the extended memory of the You.
  • the above-described gateway operates as shown in FIG. 3 for a request for memory access from the lower hierarchy. That is, the gateway portion is in the idle state ST1 in which the transmission gate TG is closed first.
  • the gateway unit transitions to the state ST2. In this state ST2, the memory access request is hit to the memory BF for the memory access information of the corresponding address. The force is checked.
  • Memory access 3 ⁇ 4 : If the requested access format is write, the gateway ifU transitions to state ST3. In this state ST 3, this 3 ⁇ 4 ⁇ is a force or check that hits the decap memory memory with respect to the Idekawa memory access information. It is done.
  • This memory access 3 ⁇ 4 If the “7 ' ⁇ ⁇ ⁇ is out ⁇ , the gateway part power; Status ::...
  • state ST 4 memory access. ⁇ ., ': The force or check that hits the memory memory BV with respect to the memory access information.
  • the state ST 3 is maintained while the hit of the memory memory B 'is confirmed, and is the state ST 4 when the hit is no longer confirmed.
  • the state ST 4 is maintained while the hit of the memory BF is confirmed, and changes to the state ST 5 when the hit is no longer confirmed.
  • state ST5 the transmission gate TG is opened, and the transmission gate TG is opened, the gate is opened. State of way is ST 6 You transition.
  • the gateway section is maintained in state ST5 while the memory access is being accessed, and the termination of this memory access has been confirmed. Return to state S ⁇ 1.
  • FIG. 4 shows the change of memory access information in the buffer memory BF.
  • the buffer memory BF initially stores memory access information as shown in the memory map on the left.
  • the memory address ADDR1 is accessed via the processor PC for reading the memory address ADDR1
  • the central memory is accessed.
  • the access frequency information N of the memory access information corresponding to the memory address ADDR1 is "2". Changes to "1”.
  • the memory address ADDR2 is accessed for writing via the processor PC system system B0, the right side
  • the access frequency information N of the memory access information corresponding to the memory address ADDR2 is "1".
  • the force changes to "0".
  • the valid flag information V is changed from “1" to "0” because this memory access information is no longer necessary. E. If the valid flag information V is "0", this memory access information becomes invalid.
  • the control circuit CNT modifies the memory access requirements supplied to the processor PC system B0 as described above. Contents of BF memory and lower hierarchical power, system nose B 1 —
  • Controls the transmission mission gate TG based on the memory access requirements supplied to Bn and based on the results of the verification. You. Here, it supplements the case where the main memory is added.
  • the processor in the lower hierarchy is assigned to the additional main memory.
  • the above-mentioned first-level processor and lower-level processor conflict with each other in the system node.
  • the first-level transmission mission TG transmits the request of the lower-level client to the upper-level hierarchy without any change. it can.
  • the decoding circuit DEC 2 is connected to the signal in the address section corresponding to the additional main memory and to the existing main memory 7.
  • a system from the lower hierarchy that identifies the signal in the corresponding address section and requests access to the main memory of the tracking U. It emits a trigger signal to connect the mnox to the higher hierarchy.
  • the gate switch circuit GS releases the gate of the corresponding bus in response to the trigger signal.
  • the decision circuit DT responds to the trigger signal generated by the decode circuit DE 2 and gains a response to a specific system node. There is also a function that allows the bird to be released.
  • Figure 5 shows the role of the operation system program.
  • the programmer generates an application program and uses a compiler to generate this application program. It is broken down into multiple task sets (eg, threads S1-S5), and then the application consisting of these threads S11-S5 Store the case program in main memory 7.
  • the application program thread S1-S4 is regained by the operation system program control.
  • Gateway section 2A-2B group GW1, Gateway section 2A-2C group GW2, Gateway Data processor 3, 4 via group GW 3 of A part 2A-2D and group GW 4 of gateway part 2A-2E , 5, and 6 are broadcasted. Thread S5 is similarly provided to data processor 3 after processing of thread S1.
  • the configuration shown in Figure 1 has the highest priority access to the processor 3 main memory 7.
  • Access to the main memory 7 by the processor 4 requires the permission of the gateway 2B of the hierarchy corresponding to the processor 3. It is important.
  • Access to the main memory 7 by the processor 5 includes the gateway 1B of the hierarchy corresponding to the processors 3 and 4.
  • a 2C permit is required.
  • access to the main memory 7 by the processor 6 includes a gateway of the hierarchy corresponding to the processors 3, 4, and 5.
  • a permission of 2A, 2C, and 2D is required.
  • the gateway 2B has the lower hierarchy of the processors 4, 5, or 6 in the lower hierarchy.
  • the ability to grant access permission to the processor 3 depends on the memory access state of the processor 3 and the lower-level process.
  • the memory access information in the Knob Memory BF is used as the basis for this processing.
  • Each lower-level processor 4, 5, or 6 force has a corresponding memory access requirement for the corresponding system 1 D, 1 C, IB power is supplied to the comparison circuit CM via the selector circuit SL and the decoding circuit DEC 2, where it is supplied to the control circuit CM.
  • the signal is output as a READYINT signal, and is output as a signal for controlling the opening and closing of the gate to the gate switch control circuit GS.
  • the decoding circuit DEC 2 output, the obtained memory access request address reads the contents of the buffer memory BF. For this purpose, it is used in the input / output control circuit BC.
  • the memory access information of the BF memory is controlled by the operating system program operating system. It is generated in response to the memory access request output to the system node B0.
  • the processor 3 usually accesses the upper hierarchy, ie the main memory 7, via the system node B0. Exceptional Force Processor 3 Power, if the transmission gate TG needs to be actively controlled,
  • the gate switch control circuit GS is controlled based on the request output to the system node B0. Control. In the gateway section of the uppermost layer, only one of the system nodes ⁇ 1- ⁇ ⁇ is connected to * system node ⁇ . As a result, collisions between system buses are reliably prevented.
  • supplementary information on the function of the operating system program 0S for setting the address division of the main memory is provided.
  • Program S is provided in case you want to add a main memory that holds the address division information corresponding to the main memory. You can also save the address division information for the main memory.
  • the address division information is set, for example, according to the maximum number of additional main memories.
  • the power is applied to the main memory 7 and the processors 3-6.
  • Supplement the functions of the interface provided.
  • the first function of this interface is to determine the number of active higher-level system buses connected to the transmission gate TG and the number of active system buses.
  • the number of lower system paths and the number of system paths are obtained from the gate switch control circuit GS, and the numbers of these nodes are compared, and based on the comparison result, the number of nodes is determined.
  • the hierarchy level of the hierarchy to which the interface belongs belongs to the hierarchy level, that is, the force that is the highest level, the lowest level, or the middle level. It is to judge.
  • the second function is to determine the connection direction of the system node B0 of the hierarchy to which this interface belongs.
  • the interface at the top hierarchy 7 If it is A, the system node B0 must always be connected to the lower hierarchy side. In other words, the system node B0 connecting the interface 7A and the transmission gate TB is located at the lower hierarchical level. It is connected to the system bus B1 and the power of B ⁇ , and is separated from the system bus B0 of the upper hierarchy side. If the interface is 3A, 4A, 5A, or 6A at the lowest or middle tier, this interface and the The system node B0 that connects the mission gate TB is connected to the system node B0 in the upper hierarchy.
  • each interface detects the hierarchical order of the corresponding hierarchy, and sends the transmission switch TG to the gate switch control circuit GS. Instruct the gating of.
  • the hierarchy order is detected, for example, as follows.
  • N (BU) the number of active upper-layer system buses
  • N (BL) the number of active lower-layer system buses.
  • the application programs are shared by sharing the data processors 3, 4, 5, 6 and the main memory 7.
  • the decentralization process reduces the load on each data processor.
  • the main memory section 2 and the main memory section 7 and the data are arranged with the output main memory section 7 at the top.
  • the hierarchy is set in processors 3-6, and the system bus is inserted into system bus 1--1E to enable data transmission between the layers and between layers. It monitors memory access requests from the lower hierarchy level below the corresponding first floor, and this memory access request is monitored. When it interferes with the memory access of the hierarchy, it is configured to control to reserve this memory access request. This control allows each data processor to interfere with memory access by the higher-level data processor. Rather, it is possible to access the main memory 7 via the self-provided system nos. In this case, the operating system program does not need to perform the conventional scheduling. Therefore, if the maximum number of hierarchies is set in the operating system program in advance, the number of operating hierarchies is within the range of this number of hierarchies. The number of data processors can be increased without changing the swing system program.
  • the main memory is only the main memory 7.
  • the top level of this hierarchy may consist of a main memory and a processor.
  • Fig. 6 shows a modification of the multiprocessor system shown in Fig. 1.
  • the processor groups 31, 41, 51, 61 are the data processors 3, 4, 5, 6 shown in FIG. It is set up instead.
  • the gateway sections 2 A-2 E are connected to the sub-systems 11 A-11 D, respectively, and these processors are connected via processors D. 1, 41, 51, 61 are connected.
  • the processor groups 31, 41, 51, 61 have three data processors 10, each having an interface section 1 OA. And are similarly configured with each other.
  • the three data processors 10 of the processor group 31 are interconnected by a subsystem system 11A, and the processors are connected to each other.
  • the three data processors 10 of the group 1 are interconnected by a subsystem system 11B, and the processor groups 10 are connected to each other.
  • the three data processors 10 of the loop ⁇ 1 are interconnected by the subsystem system 11C, and the processor The three data processors 10 in the step 61 are interconnected by a subsystem node 11 [].
  • each of the three data processors is a sub-processor.
  • System No. 11 1A The corresponding one of 11D is shared. For this reason, the operating system program must be able to use the subsystem system 11A--11D effectively. Scheduling must be performed. This schedule Since the number of layers does not depend on the number of layers, it is not necessary to change even if the number of data processors is increased by increasing the number of layers.
  • FIG. 7 shows a modification of the multi-processor system shown in FIG.
  • the processor groups 31, 41, 51, and 61 are each provided with a secondary cache memory 20.
  • Each of these secondary cache memories 20 has an interface section 2 OA and has a sub-system memory 1 1 A — 11 1 D is connected to each.
  • the same effect as in the modified example shown in FIG. 6 can be obtained.
  • the data can be obtained without changing the operating system program.
  • the number of tap mouth processors can be increased.

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  • General Engineering & Computer Science (AREA)
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Abstract

Système de multiprocesseur dans lequel on peut augmenter le nombre de processeurs de données sans modifier le programme du système d'exploitation. Ledit système comporte une mémoire centrale (7) qui mémorise les programmes d'application et le programme du système d'exploitation, une pluralité de processeurs de données (3-6) assurant le traitement réparti des programmes d'application en fonction du programme du système d'exploitation, et une pluralité de bus système (1A-1E) connectés entre les processeurs (3-6) et la mémoire centrale (7). La mémoire (7) et les processeurs (3-6) sont classés par ordre hiérarchique, la mémoire (7) étant au premier rang. De plus, des sections passerelles (2A-2E) sont connectées aux bus système (1A-1A) de sorte que les données puissent être transmises entre les couches. Ces sections passerelles (2A-2E) contrôlent les demandes d'accès en mémoire dans les couches situées au rang directement inférieur par rapport aux couches ayant fait les demandes d'accès en mémoire, et assurent la commande de l'interruption de la réponse aux demandes d'accès en mémoire lorsque ces demandes perturbent les accès en mémoire dans la couche correspondante.
PCT/JP1995/002232 1994-10-31 1995-10-31 Systeme de multiprocesseur WO1996013779A1 (fr)

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US08/817,934 US6131153A (en) 1994-10-31 1995-10-31 Multiprocessor system having a plurality of gateway units and wherein each gateway unit controls memory access requests and interferences from one hierchical level to another

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JP29062294 1994-10-31

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US7383347B2 (en) * 2001-07-18 2008-06-03 International Business Machines Corporation Method and apparatus for providing extensible scalable transcoding of multimedia content
US7085866B1 (en) * 2002-02-19 2006-08-01 Hobson Richard F Hierarchical bus structure and memory access protocol for multiprocessor systems
US6959372B1 (en) * 2002-02-19 2005-10-25 Cogent Chipware Inc. Processor cluster architecture and associated parallel processing methods
US7263598B2 (en) * 2002-12-12 2007-08-28 Jack Robert Ambuel Deterministic real time hierarchical distributed computing system

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JPH02217941A (ja) * 1989-02-20 1990-08-30 Canon Inc ネットワーク管理システム
JPH06119368A (ja) * 1991-09-26 1994-04-28 Hitachi Ltd 緩和法による連立方程式解析計算機

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US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
JPH02253356A (ja) * 1989-03-28 1990-10-12 Toshiba Corp 階層キャッシュメモリ装置とその制御方式
US5469575A (en) * 1992-10-16 1995-11-21 International Business Machines Corporation Determining a winner of a race in a data processing system
US5689679A (en) * 1993-04-28 1997-11-18 Digital Equipment Corporation Memory system and method for selective multi-level caching using a cache level code

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
JPH02217941A (ja) * 1989-02-20 1990-08-30 Canon Inc ネットワーク管理システム
JPH06119368A (ja) * 1991-09-26 1994-04-28 Hitachi Ltd 緩和法による連立方程式解析計算機

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