WO1996013062A1 - Dispositif et procede de fabrication d'empilements de series de plaquettes - Google Patents

Dispositif et procede de fabrication d'empilements de series de plaquettes Download PDF

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Publication number
WO1996013062A1
WO1996013062A1 PCT/US1995/013375 US9513375W WO9613062A1 WO 1996013062 A1 WO1996013062 A1 WO 1996013062A1 US 9513375 W US9513375 W US 9513375W WO 9613062 A1 WO9613062 A1 WO 9613062A1
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Prior art keywords
wafer
hole
conductive material
bottom side
adjacent
Prior art date
Application number
PCT/US1995/013375
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English (en)
Inventor
Stefan Linder
Original Assignee
Ceram Incorporated
Em Microelectric - Marin S.A.
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Filing date
Publication date
Application filed by Ceram Incorporated, Em Microelectric - Marin S.A. filed Critical Ceram Incorporated
Publication of WO1996013062A1 publication Critical patent/WO1996013062A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08148—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a bonding area protruding from the surface of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]

Definitions

  • the present invention is in the field of semiconductor wafer arrays wherein an undiced wafer is arrayed with at least one other undiced wafer to form a "stack".
  • the present invention relates to an apparatus of stacked wafers having a novel system for making electrical connections therebetween, and a method of manufacturing and assembling the wafers to produce such electrical connectors using plated through-hole contacts.
  • Computer processing and storage devices have for many years been fabricated from wafers of semiconductor materials which include large numbers of integrated transistor circuits.
  • the wafers have traditionally comprised many connected chips.
  • the manufactured wafer is "diced” or cut into these chips, and the diced chips are adhered to carriers and interconnected by fine wiring.
  • This process of manufacturing finished chips is somewhat expensive.
  • the fine wiring and the wiring connections tend to be unreliable, and the length of the wires reguired to make the necessary interconnections among various chips tends to result in undesirable signal delays.
  • the signal delays have become an increasing problem in recent years as the maximum speed of the systems in which the devices are used has steadily increased.
  • WSI wafer scale integration
  • Such WSI approaches have included connecting the undiced chips that test good in a wafer with discreet wiring; however, that approach has presented technical difficulties associated with the discreet wiring and has resulted in poor yields and high costs.
  • Another approach also utilizes undiced wafers which are interconnected, but the interconnection is achieved by a software mapping scheme to bypass the bad chips rather than using fine wiring. An undiced wafer mapped out with the mapping scheme is then placed on each side of a PC board. A serial access through intermediate chips is used, which produces rather long signal delays due to the long path of the serial access.
  • DRAMs dynamic random access memories
  • intact wafers of dynamic random access memories are interconnected by bundles of gold wires threaded through a set of through-holes etched into the wafers, to allow the wafers to be stacked one on top of the other to produce a very high packing density.
  • the pliability of the gold wires can accommodate relative motion between the stacked wafers caused by variable thermal expansion. While this approach provides very high memory densities, it is prohibitively expensive because it requires careful and exact wire placement and entails high cost and handling problems associated with automated equipment used for that placement.
  • a stacked wafer design is taught in U.S. Patent No. 5,229,647 by Gnadinger, the contents of which are hereby incorporated by reference.
  • interconnections between wafers are established using bumps and through-holes aligned with metal pads.
  • the bumps on one wafer contact with metal pads on a mating wafer.
  • Serial addressing and data access are used for the memory units to minimize the number of connections necessary between adjoining wafers.
  • Gnadinger device teaches a simple contact between adjacent wafers to establish electrical communication therebetween, without any mechanical bonding. Mechanical bonding is avoided to allow differential thermal expansion in adjacent wafers without breaking the electrical connection. While that does solve the problem of differential thermal expansion in adjacent wafers, it also results in a less certain electrical connection, and greater resistance in the circuit. Also, such an approach becomes infeasible when multiple contacts must be made, due to the amount of force required to maintain such contacts. Also, the preferred embodiment of the
  • Gnadinger patent teaches completely filling the through-hole with metal to carry a signal from one side of the wafer to the opposite side. It has now been discovered, however, that a fully metalized through- hole is undesirable from an electrical standpoint because it results in an undesirably large electrical capacitance due to its relatively large dimensions. It is true that a fully metalized through-hole has desirable low resistivity characteristics, but the resistance of the metal typically used for the metalization (usually gold) is sufficiently low that resistivity is not normally a limiting factor.
  • the present invention includes an apparatus and method for manufacturing the same, wherein standard silicon CMOS and/or bi-polar technology wafers (or, for that matter, wafers utilizing other technologies such as GaAs, ferroelectrics, etc.) are assembled in stacked or arrayed configurations.
  • the electrical interconnections between the layers are accomplished using plated through-hole contacts.
  • Such through-hole contacts offer the advantage that the average signal line length and the maximum number of interconnections per unit area does not depend upon the chip area. This is in contrast to the alternative approach where all signals are drawn to the edges of the stack or vertical interconnection, resulting in the average signal line length and the maximum number of interconnections being roughly proportion to the square root of the area of each wafer layer.
  • the through-holes are anisotropically etched through the wafer layer and insulated.
  • a conducting layer preferably of gold, is electroplated or otherwise placed in the through-hole to feed the electrical signal from the conventional circuitry on the wafer face via a standard contact pad to the back of the substrate.
  • the anisotropically etched through-holes are etched from the back of the wafer, which results in very small openings on the wafer face holding the integrated circuits; thus, only a small portion of the silicon area must be sacrificed for each vertical interconnection.
  • An oxide serves as the etch stop on the wafer front.
  • the etching is carried out in a KOH solution at elevated temperatures, using a fixture to seal the wafer face against the etchant; the seal protects the wafer face, in particular the aluminum metalization, from being attacked by the KOH. Moreover, using the fixture, the alkaline metal- contaminated zone is limited to the wafer back where it can be easily removed. After stripping the etch stop membrane, the side walls of the holes are protected with another oxide layer, and the electrical interconnection is applied with a selective electrode deposition of gold.
  • FIG. 1 shows a final assembly of stacked intact wafers in accordance with the present invention.
  • FIG. 2 shows a side sectional view of a set of stacked wafers, showing the electrical interconnections thereof.
  • FIG. 3A is a pictorial view of a plated through-hole in accordance with the present invention.
  • FIG. 3B is a pictorial view of a plated through-hole in accordance with an alternative embodiment of the invention.
  • FIG. 3C is a pictorial view of a plated through-hole in accordance with an alternative embodiment of the invention.
  • FIG. 3D is a pictorial view of a plated through-hole in accordance with an alternative embodiment of the invention.
  • FIGs. 4A-4P show steps in a process in accordance with the present invention.
  • FIG. 5 shows a side sectional view of a device used in practicing the present invention.
  • FIG. 6 shows a side sectional view of another device used in practicing the present invention.
  • FIG. 1 A final assembly of a high density storage system utilizing stacked intact wafers in accordance with the present invention is shown in FIG. 1.
  • the assembly 10 includes an enclosure 12 such as a metal case mounted on a base plate 14.
  • a wiring plane 18 is positioned on the base plate 14.
  • a plurality of silicon wafers 16 are stacked or arrayed within the space defined by the enclosure 12 and base plate 14.
  • FIG. 2 shows a detail of three wafer layers, 32, 34 and 36 in stacked configuration. As evident from the illustration of FIG. 2, each of the three wafer layers 32, 34 and 36 includes a through-hole 38, 40 and 42, respectively, which is plated with an electrical conductor 44, 46 and 48, respectively.
  • Each electrical conductor 44, 46 and 48 includes a bottom side portion, 50, 52 and 54, which plates a portion of the through-holes 38, 40 and 42, respectively, and a pad portion 56, 58 and 60 to make contact with the through-hole portion of the adjacent wafer as well as with a micro circuit located on the wafer face.
  • the pad of each electrical conductor contacts makes electrical communication with the plated through-hole portion of the adjacent wafer by a in-flow solder joint 62 and 64. It can be appreciated that, while only three wafers are shown in the depiction of FIG. 2, the assembly could instead include only two wafers or any number of wafers greater than three or only one wafer on a base plate.
  • FIG. 3A shows a fully metalized through-hole, in which the wafer back side is fully metalized in the form of a electrical conductor electroplated thereon.
  • the electrical conductor 82 extends from the pyramid of the shaped through-hole surface to the wafer back side surface where it forms a pad 84 to contact the adjacent wafer (not shown).
  • the through- hole surface 74 is partially metalized with partial metal plating 70 which extends onto the wafer back side to form an electrical contact pad 72 for electrical communication with the adjacent wafer (not shown).
  • the through-hole surface 90 is once again partially metalized by an electrical conductor plating 92.
  • the electrical conducting electroplate 92 extends around the apex of the pyramid of the shaped through-hole surface 90, and includes a tab 94 extending from the apex to the backside surface which terminates in a pad 96 in communication with the adjacent wafer (not shown).
  • the goal of the designs are to reduce the surface area of the electroplated electrical conduits in order to minimize capacitance with respect to a fully metalized through-hole. Furthermore, the production costs are reduced because of the reduced mass of the electroplated gold.
  • the device of the present invention may utilize multiple independent circuit pathways as shown in FIG. 3D.
  • the through-holes may include several electrical conducting electroplate surfaces or "traces.” In that manner, a single through-hole can be used to accommodate several electrical connections. Each trace on each side of the through-hole terminates in a conductive pad for contact with an adjacent wafer in the manner of the single trace design already described.
  • FIG. 4A A typical CMOS processed wafer 110 is shown in FIG. 4A.
  • the wafer 100 includes a silicon body 101 having an unfinished back side 102 coated with oxides and/or nitrides 103.
  • the front side includes a field oxide/insulation oxide layer 104, a passivation layer 105 and a series of pads 106.
  • FIG. 4B shows the application of a protective layer 112 of oxide or nitride to a thickness of 3,000 - 5,000 angstroms for the purpose of protecting the uncovered aluminum pads from mechanical or chemical damage.
  • Mechanical damage is common in the form of scratches and abrasions due to the wafer 110 being placed repeatedly upside down on processing equipment. Chemical damage is possible due to contact with traces of the etchant.
  • the etchant used in the preferred embodiment - potassium hydroxide - is highly corrosive to aluminum.
  • the oxide or nitride protective layer 112 must be thick enough to cover all hillocks and edges of the aluminum.
  • the oxide and/or nitride layer 103 (see FIG. 4A) on the back side 102 of the wafer 100 is stripped either wet chemically or in a plasma etcher. Because the wet chemical approach requires front side protection (such as a photoresist layer), the plasma method is preferable.
  • the back side 102 should be made as planar and defect-free as possible. A low defect density is important since anisotropic etching is crystal orientation dependent. Defects in the crystal increase the etch rate significantly and cause poor control over the etch pit dimensions. Likewise, surface planarity is critical for a uniform, defect-free coverage with PECVD films which are later deposited on the wafer backside 102.
  • a planarization back etching can be accomplished using mechanically assisted isotropic silicon back etch (so called chemical polishing) .
  • mechanically assisted isotropic silicon back etch so called chemical polishing
  • Such an approach results in a defect-free mirror-like surface, and the method is well established, inexpensive and straight forward. Further, no wafer front side protection is needed.
  • a brief potassium hydroxide etch may be used for planarizing the wafer back side 102. It is believed that a potassium hydroxide etch is not as desirable as mechanically assisted isotropic silicon etching for this purpose, since the resulting planarity is less than perfect and requires durable processing efforts.
  • the next step is deposition of a KOH etch mask 122, as shown in FIG. 4C on the planarized wafer back side 102.
  • the etch mask 122 is a PECVD nitride which serves as a mask for the subsequent KOH etching of through-holes in the wafer.
  • the minimum thickness of the mask 122 depends on the nitride etch rate in KOH; for 700 ⁇ m thick wafers, the mask typically needs to have a thickness of 0.5 - 1.0 ⁇ m.
  • a photoresist layer 123 is applied over the KOH etch mask 122 as shown in FIG. 4D for the purpose of defining the interconnection holes.
  • the next step, as shown in FIG. 4E is to nitride etch the etch mask 122 and then strip the photoresist 123.
  • the nitride etch is to isotropically etch 1 - 2 ⁇ m deep into the silicon after the nitride has been removed. This can be accomplished with a pure SF 6 plasma driven at low power. A properly etched nitride will result in an undercut at the nitride edges.
  • 4F shows the results of anisotropic etching of the through-holes using potassium hydroxide.
  • the preferred embodiment utilizes a KOH concentration of 4 - 6 M at about 95°C.
  • An etch rate of approximately 150 ⁇ m per hour is achieved; because the wafer 110 is approximately 500 - 700 ⁇ m thick, the total etch time is on the order of 4 1/2 hours.
  • the end point of the etching can easily be detected by the cessation of hydrogen bubbles produced by the reaction of OH with silicon.
  • FIG. 5 shows a cross-sectional view of a mechanical fixture for that purpose.
  • the fixture 210 includes a stainless steel base plate 212, an overplate 214 and a PTFE insert 216.
  • the wafer 110 is mounted on the PTFE insert 216, top
  • the next step is to strip the mask on the wafer backside 102 and the oxide membranes 112 on the wafer front side.
  • the fact that the KOH etch mask consists of non-stoichiometric PECVD nitride allows it to be stripped in buffered hydrofluoric acid.
  • the front side of the wafer must be protected during this operation, since the etchant otherwise attacks both the passivation and the underlying layers such as the intermetal oxides.
  • Front side protection can be accomplished using a photoresist layer 131 which may be spun on as shown in FIG. 4G.
  • the next step is a substrate back etch step also shown in FIG. 4H. The purpose of this step is to remove roughly 1 - 2 ⁇ m of silicon on the wafer back side. This removes any remaining contamination of alkaline metals on the side wall of the etch pits, and also conditions the edge of the edge pit on the wafer front side for a conformal insulator coverage.
  • FIG. 41 shows before and after views of the border between the etch pit and the oxide layer illustrating the conditioning of the edge.
  • the next step is to deposit an interconnection insulator 170 as shown in FIG. 4J.
  • FIG. 4K shows the sputter deposition of TiW as a diffusion barrier and Au as a seed layer 172.
  • the next step is probimide spin-on.
  • the goal of this step is to cover both sides of the wafer 110 with PROBIMIDE 348 or PROBIMIDE 7020 brand of Ciba- Geigy. Proper coverage of the wafer back side is not difficult, since the probimide has a very high viscosity and planarizes even etch pits.
  • the major difficulty is in the fact that there are holes in the wafers in the form of the through-holes, and a standard spin-on procedure using a vacuum chuck causes the probimide to be sucked through the holes.
  • FIG. 6 shows a special chuck which is used to overcome this difficulty.
  • the special chuck 310 holds the wafer 110 in place at the wafer periphery using pins 312.
  • the probimide is first spun onto the wafer back side to planarize the etch pits. Surface tension prevents it from flowing through the holes onto the wafer front side, as shown in FIG. 4M.
  • the probimide is quite tough and all holes in the wafer are thereby closed, and the front side of the wafer can then be coated using a standard vacuum chuck.
  • FIG. 4N is the lithography step to define the pad sides. Both sides of the wafer 110 are exposed sequentially utilizing conventional lithographic methods. Wafer handling at this point does not pose special problems since the probimide is fairly tough and invulnerable. Development of the probimide is carried out in an ultrasonic bath. Finally, the wafer 110 is electroplated to a thickness 190 of about 25 ⁇ m as shown in FIG. 40, and the plating mask and seed layers are stripped as shown in FIG. 4P.

Abstract

La présente invention concerne un dispositif à semi-conducteurs utilisant un empilage de plaquettes non découpées en microplaquettes ainsi qu'un procédé de fabrication de ce dispositif. Un jeu de plaquettes (36, 34, 32) empilées, non découpées en microplaquettes, présente des trous traversants (42, 40, 38) partiellement ou totalement revêtus d'une substance électro-conductrice (48, 46, 44) débordant du trou traversant sur la surface de la plaquette pour constituer une plage de connexion conductrice (60, 58, 56). La plage de connexion supérieure d'une plaquette touche la plage de connexion inférieure de la plaquette adjacente, créant ainsi entre elles une communication électrique. La substance électro-conductrice n'étant disposée qu'en revêtement, et non en remplissage, de chaque trou traversant, la connexion ne crée qu'un effet capacitif limité. Les trous traversants sont en outre traités par attaque chimique anisotropique.
PCT/US1995/013375 1994-10-19 1995-10-19 Dispositif et procede de fabrication d'empilements de series de plaquettes WO1996013062A1 (fr)

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EP0851492A2 (fr) * 1996-12-06 1998-07-01 Texas Instruments Incorporated Structure de substrat à montage de surface et méthode
FR2767223A1 (fr) * 1997-08-06 1999-02-12 Commissariat Energie Atomique Procede d'interconnexion a travers un materiau semi-conducteur, et dispositif obtenu
WO2000060662A1 (fr) * 1999-03-31 2000-10-12 Infineon Technologies Ag Procede de fabrication d'un dispositif destine a raccorder electriquement un composant semi-conducteur et une surface de montage, et dispositif associe
EP1267402A2 (fr) * 2001-06-14 2002-12-18 Shinko Electric Industries Co. Ltd. Dispositif semi-conducteur et méthode de fabrication associée
EP1267401A2 (fr) * 2001-06-14 2002-12-18 Shinko Electric Industries Co. Ltd. Dispositif semi-conducteur et méthode de fabrication associée
WO2004006382A1 (fr) 2002-07-02 2004-01-15 Robert Bosch Gmbh Composant electrique, en particulier composant haute frequence micro-electronique ou micro-electromecanique
EP1429388A1 (fr) * 2002-12-11 2004-06-16 Northrop Grumman Corporation Trous d'interconnexion à haute performance pour l'empilement de circuits intégrés
US6780770B2 (en) 2000-12-13 2004-08-24 Medtronic, Inc. Method for stacking semiconductor die within an implanted medical device
DE10319538A1 (de) * 2003-04-30 2004-11-25 Infineon Technologies Ag Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
EP1248295A3 (fr) * 2001-04-06 2005-07-13 Shinko Electric Industries Co. Ltd. Elément semi-conducteur, structure de connection, dispositif semi-conducteur utilisant plusieurs de ces éléments et procédés de fabrication
EP1564810A1 (fr) * 2004-02-17 2005-08-17 Sanyo Electric Co., Ltd. Dispositif semi-conducteur et son procédé de fabrication
WO2006084028A2 (fr) * 2005-02-03 2006-08-10 Analog Devices, Inc. Liaison conductrice pour interconnexion transversale de plaquette
DE102005006280A1 (de) * 2005-02-10 2006-08-24 Infineon Technologies Ag Halbleiterbauteil mit einem Druckkontakt durch eine Gehäusemasse und Verfahren zur Herstellung desselben
US7339273B2 (en) 2004-10-26 2008-03-04 Sanyo Electric Co., Ltd. Semiconductor device with a via hole having a diameter at the surface larger than a width of a pad electrode
US7485967B2 (en) 2005-03-10 2009-02-03 Sanyo Electric Co., Ltd. Semiconductor device with via hole for electric connection
US7582971B2 (en) 2004-10-26 2009-09-01 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method of the same
US7608534B2 (en) 2004-06-02 2009-10-27 Analog Devices, Inc. Interconnection of through-wafer vias using bridge structures
US7646100B2 (en) 2004-10-28 2010-01-12 Sanyo Electric Co., Ltd. Semiconductor device with penetrating electrode
EP2317544A1 (fr) * 2008-08-06 2011-05-04 Fujikura, Ltd. Dispositif à semi-conducteurs
US7943411B2 (en) 2008-09-10 2011-05-17 Analog Devices, Inc. Apparatus and method of wafer bonding using compatible alloy
US8100012B2 (en) 2007-01-11 2012-01-24 Analog Devices, Inc. MEMS sensor with cap electrode
US8736028B2 (en) 2005-09-01 2014-05-27 Micron Technology, Inc. Semiconductor device structures and printed circuit boards comprising semiconductor devices
US8956904B2 (en) 2008-09-10 2015-02-17 Analog Devices, Inc. Apparatus and method of wafer bonding using compatible alloy
CN110400787A (zh) * 2019-06-26 2019-11-01 中国电子科技集团公司第三十八研究所 一种硅基垂直互联结构及制备方法

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EP0851492A2 (fr) * 1996-12-06 1998-07-01 Texas Instruments Incorporated Structure de substrat à montage de surface et méthode
EP0851492A3 (fr) * 1996-12-06 1998-12-16 Texas Instruments Incorporated Structure de substrat à montage de surface et méthode
FR2767223A1 (fr) * 1997-08-06 1999-02-12 Commissariat Energie Atomique Procede d'interconnexion a travers un materiau semi-conducteur, et dispositif obtenu
WO1999008318A1 (fr) * 1997-08-06 1999-02-18 Commissariat A L'energie Atomique Procede d'interconnexion a travers un materiau semi-conducteur
WO2000060662A1 (fr) * 1999-03-31 2000-10-12 Infineon Technologies Ag Procede de fabrication d'un dispositif destine a raccorder electriquement un composant semi-conducteur et une surface de montage, et dispositif associe
US6780770B2 (en) 2000-12-13 2004-08-24 Medtronic, Inc. Method for stacking semiconductor die within an implanted medical device
EP1248295A3 (fr) * 2001-04-06 2005-07-13 Shinko Electric Industries Co. Ltd. Elément semi-conducteur, structure de connection, dispositif semi-conducteur utilisant plusieurs de ces éléments et procédés de fabrication
EP1267401A2 (fr) * 2001-06-14 2002-12-18 Shinko Electric Industries Co. Ltd. Dispositif semi-conducteur et méthode de fabrication associée
EP1267401A3 (fr) * 2001-06-14 2005-09-28 Shinko Electric Industries Co. Ltd. Dispositif semi-conducteur et méthode de fabrication associée
EP1267402A2 (fr) * 2001-06-14 2002-12-18 Shinko Electric Industries Co. Ltd. Dispositif semi-conducteur et méthode de fabrication associée
EP1267402A3 (fr) * 2001-06-14 2005-09-28 Shinko Electric Industries Co. Ltd. Dispositif semi-conducteur et méthode de fabrication associée
WO2004006382A1 (fr) 2002-07-02 2004-01-15 Robert Bosch Gmbh Composant electrique, en particulier composant haute frequence micro-electronique ou micro-electromecanique
EP1520320B1 (fr) * 2002-07-02 2012-09-26 Robert Bosch Gmbh Composant electrique, en particulier composant haute frequence micro-electronique ou micro-electromecanique
EP1429388A1 (fr) * 2002-12-11 2004-06-16 Northrop Grumman Corporation Trous d'interconnexion à haute performance pour l'empilement de circuits intégrés
US6936913B2 (en) 2002-12-11 2005-08-30 Northrop Grumman Corporation High performance vias for vertical IC packaging
US7247948B2 (en) 2003-04-30 2007-07-24 Infineon Technologies Ag Semiconductor device and method for fabricating the semiconductor device
DE10319538A1 (de) * 2003-04-30 2004-11-25 Infineon Technologies Ag Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
DE10319538B4 (de) * 2003-04-30 2008-01-17 Qimonda Ag Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
US7750478B2 (en) 2004-02-17 2010-07-06 Sanyo Electric Co., Ltd. Semiconductor device with via hole of uneven width
US7732925B2 (en) 2004-02-17 2010-06-08 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
EP1564810A1 (fr) * 2004-02-17 2005-08-17 Sanyo Electric Co., Ltd. Dispositif semi-conducteur et son procédé de fabrication
US7608534B2 (en) 2004-06-02 2009-10-27 Analog Devices, Inc. Interconnection of through-wafer vias using bridge structures
US7339273B2 (en) 2004-10-26 2008-03-04 Sanyo Electric Co., Ltd. Semiconductor device with a via hole having a diameter at the surface larger than a width of a pad electrode
US7582971B2 (en) 2004-10-26 2009-09-01 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method of the same
US7670955B2 (en) 2004-10-26 2010-03-02 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method of the same
US7646100B2 (en) 2004-10-28 2010-01-12 Sanyo Electric Co., Ltd. Semiconductor device with penetrating electrode
WO2006084028A2 (fr) * 2005-02-03 2006-08-10 Analog Devices, Inc. Liaison conductrice pour interconnexion transversale de plaquette
WO2006084028A3 (fr) * 2005-02-03 2007-01-04 Analog Devices Inc Liaison conductrice pour interconnexion transversale de plaquette
DE102005006280B4 (de) * 2005-02-10 2006-11-16 Infineon Technologies Ag Halbleiterbauteil mit einem Durchkontakt durch eine Gehäusemasse und Verfahren zur Herstellung desselben
DE102005006280A1 (de) * 2005-02-10 2006-08-24 Infineon Technologies Ag Halbleiterbauteil mit einem Druckkontakt durch eine Gehäusemasse und Verfahren zur Herstellung desselben
US9165898B2 (en) 2005-03-10 2015-10-20 Semiconductor Components Industries, Llc Method of manufacturing semiconductor device with through hole
US7485967B2 (en) 2005-03-10 2009-02-03 Sanyo Electric Co., Ltd. Semiconductor device with via hole for electric connection
US8736028B2 (en) 2005-09-01 2014-05-27 Micron Technology, Inc. Semiconductor device structures and printed circuit boards comprising semiconductor devices
US8100012B2 (en) 2007-01-11 2012-01-24 Analog Devices, Inc. MEMS sensor with cap electrode
EP2317544A4 (fr) * 2008-08-06 2012-02-15 Fujikura Ltd Dispositif à semi-conducteurs
CN102105969A (zh) * 2008-08-06 2011-06-22 株式会社藤仓 半导体装置
EP2317544A1 (fr) * 2008-08-06 2011-05-04 Fujikura, Ltd. Dispositif à semi-conducteurs
US7981765B2 (en) 2008-09-10 2011-07-19 Analog Devices, Inc. Substrate bonding with bonding material having rare earth metal
US7943411B2 (en) 2008-09-10 2011-05-17 Analog Devices, Inc. Apparatus and method of wafer bonding using compatible alloy
US8956904B2 (en) 2008-09-10 2015-02-17 Analog Devices, Inc. Apparatus and method of wafer bonding using compatible alloy
CN110400787A (zh) * 2019-06-26 2019-11-01 中国电子科技集团公司第三十八研究所 一种硅基垂直互联结构及制备方法

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