WO1996011463A1

WO1996011463A1 - Method and device for controlling frame memory

Info

Publication number: WO1996011463A1
Application number: PCT/JP1995/002058
Authority: WO
Inventors: Shuji Hori
Original assignee: Sega Enterprises, Ltd.
Priority date: 1994-10-07
Filing date: 1995-10-06
Publication date: 1996-04-18
Also published as: JPH08110770A

Abstract

Read coordinates X and Y are outputted to a frame memory (20) for display as a read address and image data are read from the memory (20) according to a read signal for display from a read signal generating circuit (42) for display. In addition, an X-coordinate comparator circuit (39) and a Y-coordinate comparator circuit (40) respectively compare the coordinates X and Y with the coordinates of a prescribed area set in registers (34-37). When it is judged that the coordinates are in the prescribed area, a write signal for display from a write signal generating circuit (41) for display is turned on. As a result, erase writing data set in an erase writing data register (38) are written at the read address immediately after the image data are read. Therefore, the write time of the image data in the frame memory (20) can be shortened.

Description

Specification

TECHNICAL FIELD The present invention relates to a method and an apparatus for controlling a frame memory.

The present invention relates to a frame memory control method and apparatus for writing image data to be displayed on a monitor to a frame memory and reading out the image data in units of dots for display on the monitor. [Background Art]

2. Description of the Related Art Conventionally, an image processing device used in a game machine has a frame memory for storing image data one frame at a time, and reads out the image data in the frame memory in synchronization with a horizontal / vertical synchronization signal to read the three primary colors RGB A video display processor (VDP) that outputs an RGB signal indicating a level is known.

In such a device, under the control of the CPU, the VDP reads the image data of the image to be displayed on the display screen of the display from the ROM and writes the image data to the frame memory as the program is executed. The image data written to this frame memory is read out in synchronization with the horizontal and vertical synchronization signals from the VDP, then converted to analog signals by a DZA converter connected to the VDP, and displayed on the display as RGB. It is input as a video signal and displayed on the surface.

By the way, the above-mentioned frame memory is usually composed of two frame memories, one for display and the other for drawing. While the image data is being damaged in one frame memory, the image data developed in the other frame memory is shot out and displayed on the TV screen of the display. When the period during which one frame of image is displayed ends, the display is switched between drawing and display, and the image data that has been expanded in the frame memory used for drawing is shot out and displayed. The image data of the frame two minutes ahead is written to the frame memory. Both frame memories are switched from display to drawing. Before the writing is started after the replacement, the contents written so far are erased (hereinafter, this erasing is referred to as erase write).

Fig. 5 shows a conventional method of frame memory erase writing. As shown in this figure, an area wider than the display area DP of the actual TV screen is taken as the frame memory plane FR. The area where the erase writing is performed may be the entire display area DP of the TV screen as shown in FIG. 5 (a), or the entire frame memory plane FR. Then, by writing data representing transparent or black on this area, the image data which has been written so far is erased. However, in such a method, the entire image data developed in the frame memory is erased. Therefore, when only a part of the image data is changed and displayed, the same image data must be written again. No. There is a limit to the number of dots that can be harmed to the frame memory during the frame memory switching period, that is, during the one-frame image display period described above. Therefore, there is a problem that it is difficult to increase the number of characters to be drawn in one frame or to draw a character with a large number of dots.

The present invention has been proposed in view of such problems of the prior art. The first object of the present invention is to reduce the time for writing image data to the frame memory when displaying the same image in succession. An object of the present invention is to provide a frame memory control method that can be shortened.

A second object is to provide a frame memory control device capable of realizing the first object.

A third object is to provide a frame memory control device capable of erasing designated image data in a short time.

A fourth object is to provide a frame memory control device capable of efficiently controlling two frame memories.

A fifth object is to provide a frame memory control device in which an area for erasing image data can be easily specified. DISCLOSURE OF THE INVENTION

In order to achieve the above object, a frame memory control method according to the present invention writes a frame memory with image data to be displayed on a monitor, and reads the image data from the frame memory for each dot. When reading the image data, the coordinates of an arbitrary area on the frame memory and erase data to be written as background data in an address in the area are set, and Read addresses, which are read positions in the horizontal and vertical directions of the memory, are sequentially generated in dot units, and the read addresses and the coordinates of the area are narrowed down. In the case, the image data is read from the read address of the frame memory, and If the read address is within the region, after reading the image data from said reading § address of the frame memory, it is characterized in that writing the I race data to the Adoresu.

Therefore, when reading the image data from the frame memory, only the image data is read from the frame memory outside the preset area, and after reading the image data inside the area, Erase data is harmed at that position. Then, the image data outside this area remains without being erased. Therefore, when writing image data to this frame memory, it is not necessary to continuously write the same image data outside this area, and the time for writing image data can be reduced.

Also, a frame memory control device according to the present invention includes: a drawing circuit that writes image data to be displayed on a monitor into a frame memory; and a display circuit that reads the image data from the frame memory in dot units. A display circuit configured to sequentially generate a read address in the horizontal direction and the vertical direction of the frame memory as a read address in dot units; and coordinates at which coordinates of an arbitrary area on the frame memory are set. A setting register, a coordinate comparing unit that compares the read address with the coordinates of the area, and determines whether the read address is within the area, and harms the address in the area as background data. An erase data setting register in which erase data to be written is set; If the read address is not within the area, the image data is read from the read address of the frame memory.If the read address is within the area, the image data is read. And an input / output control unit for writing the erase data to the read address after reading the data.

With such a configuration, the read address of the frame memory sequentially generated from the address generating means is compared with the coordinates of an arbitrary area set in the coordinate setting register by the coordinate comparing means. When it is determined that the read address is not within the above-mentioned area, the image data is read from the read address of the frame memory by the input / output control means. If it is determined that the read address is within the area, after the image data is read, erase data is written to the read address.

Thus, the image data inside the area set in the coordinate setting register is erased, but the image data outside is not erased. Therefore, when the same image is displayed for a while, the time for writing the image data to the frame memory can be reduced. The area can be arbitrarily changed by the value set in the coordinate setting register, and the erase data can also be arbitrarily changed by the value set in the erase data setting register.

Also, in the frame memory control device according to the present invention, the display circuit may include a read signal generating unit configured to generate a read signal to the frame memory, and a read address generated from the address generating unit by the coordinate comparison unit. Writing signal generation means for generating a write signal immediately after the generation of the read signal when it is determined that the read signal is within the area set in the coordinate setting register; An input / output buffer for holding image data read from the read address of the frame memory and erase data set in the erase data setting register; and, when the read signal is generated, the frame memory. The image data is read from the memory, and when the write signal is generated, And outputs the serial I race data to the read Adoresu of the frame memory And an input / output control circuit for controlling the input / output buffer.

With such a configuration, when a read signal is generated, image data is read from the read address of the frame memory under the control of the input / output buffer by the input / output control circuit. When a write signal is generated, the erase data set in the erase write setting register is output to the read address of the frame memory. In this case, a damage signal is generated immediately after the generation of the read signal, and the erase data is damaged at the position where the image data is read. Therefore, the designated image data is erased in a short time.

Also, in the frame memory control device according to the present invention, the frame memory is formed of two surfaces, and while the drawing circuit is writing the image data into one of the frame memories, the display circuit is configured to store the image data in the frame memory. The image data is read from the other side, and when the writing and reading are completed, switching between the drawing circuit and the display circuit is performed, and the drawing circuit writes the image data to the other side of the frame memory. The display circuit has a drawing selector for reading the image data from one of the frame memories.

With such a configuration, while the drawing circuit is writing image data to one of the frame memories, the display circuit reads the image data from the other of the frame memory, and when one screen is completed, the display selector selects the drawing data. Can be switched. Then, the drawing circuit writes image data to the other frame memory, and the display circuit reads one image data.

Further, the frame memory control device according to the present invention is characterized in that the area is a rectangle whose four points are specified by a horizontal start point and an end point and a vertical start point and an end point.

With such a configuration, since the area is rectangular, it is easy to specify the area and compare the coordinates.

[Brief description of the drawings] FIG. 1 is a block diagram showing the overall configuration of an image processing device using a frame memory control device according to one embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the frame memory control device according to this embodiment, and FIG. FIG. 4 is a diagram for explaining the damage of the image data to the frame memory 20 in the embodiment, FIG. 4 is a diagram for explaining the reading of image data from the frame memory 20 in the embodiment, and FIG. FIG. 9 is a diagram illustrating an erase light.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of a frame memory control device according to the present invention will be described with reference to the drawings.

A. Configuration of the embodiment

Overall configuration>

FIG. 1 is a block diagram illustrating an overall configuration of an image processing apparatus having a frame memory control device according to the present embodiment. The bus 14 includes a CPU 15 for controlling the entire system, a ROM 16 for storing programs, a sprite engine (VDP 1) 17 for processing foreground images, and a scroll engine (for image processing for a plurality of background images). VD P 2) 18 is connected. Also connected to the split engine 17 are a command RAM 19 for storing command data from the CPU and foreground image data, and a frame memory 20 for expanding foreground image data in association with the display screen. Have been. That is, the split engine 17 is the frame memory control device according to the present embodiment. Further, the scroll engine 18 is connected to a video RAM (hereinafter referred to as VRAM) 21 for storing image data for each dot of the background image.

In addition, the bright engine 17 selects and reads image data of a foreground image such as a character from the command RAMI 9, performs processing such as rotation, enlargement, reduction, and color calculation, and then executes processing of the frame memory 20. Damage to a given address in dot units. The split engine 17 sequentially reads out the image data for one frame written in the frame memory 20 in dot units, and supplies the image data directly to the scroll engine 18 without passing through the bus 14. The scroll engine 18 reads the image data of each background image from the VRAM 21 and outputs the image data in pixel units. In addition, the priorities of the foreground image data supplied from the split engine 17 and the background image data are compared, and the image data is synthesized based on those priorities to generate RGB data. Output at the timing synchronized with the dot clock. Then, this RGB data is supplied to the DA converter 22. Thereby, the DZA converter 22 converts the RGB data into an analog signal and outputs it as a video signal. This video signal is supplied to a monitor (not shown) and displayed on a TV screen.

Structure of Split Engine 17>

FIG. 2 is a block diagram showing a configuration of the split engine 17. In the figure, the frame memory 20 is composed of two frames of frame memories 20a and 20b, and when-is used for display, the other is used for drawing. Hereinafter, when it is not specified as any one of the frame memories, it is described as a frame memory 20. (1) Drawing circuit 30

First, the drawing circuit 30 that controls the drawing frame memory 20 will be described. The drawing circuit 30 reads out the image data of the character designated to be drawn from the command RAM 19 based on the command data from the command RAM 9, and outputs one dot of the image data as the drawing data. Further, a drawing address designating the address of the image data to be written to the frame memory 20 is output to the drawing no display selector 45. Since the frame memory 20 is given an address so as to match the scanning order of the TV screen, the address in the X direction and the address in the Y direction can be regarded as the coordinates of each pixel on the display screen.

Further, the drawing circuit 30 controls the timing of reading and damage to the frame memory 20 for drawing, and outputs a drawing-time read signal for specifying reading and a drawing-time write signal for specifying damage. Is output to the display selector 45. The read signal for drawing is output when the image data already written in the frame memory 20 for drawing is once read. This is generally done in two cases: ①When specific processing is performed in Scroll Engine 18

The most significant bit of the image data read by the drawing read signal is changed from “0” to “1”, and is written again to the original position S of the frame memory 20. The scroll engine 18 performs, for example, window processing and shadow processing on the image data whose uppermost bit has been changed in this way. Window processing is processing to display another surface inside or outside the area specified as a window, and shadow processing is processing to cast a shadow on a character displayed on the screen.

② When performing translucent calculation processing

The translucent operation is performed by calculating the average of the image data read by the drawing read signal and the image data generated in the splicing engine 17. This calculation result is newly written on the frame memory 20 as image data. As a result, a translucent image is displayed.

(2) Display circuit 31

Next, the readout X counter 32, which shows the display circuit 31 that controls the display frame memory 20b, stores the X coordinate in the display frame memory 20 at one dot clock for each display on the TV screen. It is generated by counting up and outputs it to the drawing display selector 45 as the read coordinate X. The readout Y counter 33 generates the Y coordinate in the display frame memory 20 by incrementing the Y coordinate by one for each line (raster) of the display on the TV screen. Output to selector 45.

The X0 register 34, the XI register 35, the Y0 register 36, the Y1 register 37, and the erase write data register 38 are all control registers whose values are set by the CPU 15. Here, FIG. 3 shows an example of the display frame memory 20, and it is assumed that the area AR in FIG. 3 is an area to be erased. In the present embodiment, the area to be erased is a rectangle having four points of coordinates (X0, Y0), (XI, Υ0), (X0, Yl), and (XI, Y1). And

That is, the X0 register 34 stores the X coordinate X0 at the upper left in the area AR. The Y 0 register 36 stores the Υcoordinate Υ0. The XI register 35 stores the X coordinate X1 at the lower right in the area AR, and the Y1 register 37 stores the Y coordinate Y1. Further, the erase write register 38 stores data that harms the area AR, for example, data indicating transparency or data indicating black.

The X coordinate comparison circuit 39 reads the read coordinate X output from the read X counter 32 with the X coordinate X 0 stored in the X 0 register 34 and the X coordinate X 1 stored in the X 1 register 35. And outputs the area signal XHIT. The area signal X HIT is a signal indicating whether or not the read coordinate X is within the specified range, and becomes “1” when X 0 ≤X ≤X 1. When the read coordinate X is other than the above, the area signal X HIT becomes “0”.

The Y coordinate ratio circuit 40 stores the read coordinate Y output from the read Y counter 33 in the Y coordinate Y 0 stored in the Y 0 register 36 and the Y coordinate Y 0 stored in the Y 1 register 37. Outputs the area signal YHIT in comparison with the Y coordinate Y1. This area signal YHIT is a signal indicating whether or not the read coordinate Y is within the specified range, and becomes “1” when Y0≤Y≤Y1. When the read coordinates Υ are other than the above, the signal Y HI と becomes “0”.

The display-time write signal generation circuit 41 outputs a display-time harmful signal for performing erase-write to the frame memory 20 for drawing based on the above-mentioned area signals XHI Τ and YHI, and a drawing-no-display selector. 4 Output to 5. The display-time write signal is ON when both of the above signals are "1", and is OFF when either one is "0". On the other hand, the display-time readout signal generation circuit 42 outputs a display-time readout signal to the display frame memory 20 to the drawing Z display selector 45.

The input / output control circuit 43 converts the display write signal output from the display harmful signal generation circuit 41 and the display read signal output from the display read signal generation circuit 42. Based on this, it outputs a data input / output control signal to the input / output buffer 44. In other words, the I / O buffer 44 is controlled by whether the read signal for display is ON, the write signal for display is ON, or both are 0FF. Output a signal. Neither the read signal for display nor the write signal for display is turned ON, and the write signal for display becomes 0 N immediately after the read signal for display becomes 0 FF. is there.

As described above, the display write signal generation circuit 41 sets the display-time write signal to ON when the area signals X HIT and Y HIT are both “1”. On the other hand, the display read signal generation circuit 42 causes the display read signal to be ONZOFF in the period of one to two of the dot clock. When the read signal for display is set to ON, a mask signal for suppressing the output of the write signal for display is simultaneously output to the display write signal generation circuit 41. This prevents the display-time write signal and the display-time read signal from colliding (overlapping). That is, it is possible to prevent the write signal for display and the read signal for display from being simultaneously output to the frame memory 20.

(3) I / O buffer 4 4

The input / output buffer 44 controls the data input / output direction to / from the data buses 46a and 46b as described below by the data input / output control signal. That is, when the readout signal for display is 0 N, the image data from the display frame memory 20 is input via the data bus 46, and is directly sent to the scale engine 1 as image data for display. Output to 8. When the write signal for display is ON, the erase write data set in the erase write data register 38 is output to the display frame memory 20 via the data bus 46. When both the display-time readout signal and the display-time harmful signal are 0FF, data is not input / output to / from the input / output buffer 44. The data bus 46a corresponds to the frame memory 20a, and the data bus 46b corresponds to the frame memory 46b.

(4) Drawing Z display selector 4 5

The drawing / display selector 45 determines the address in the frame memory 20 based on each input address signal, display-time write signal, and display-time readout signal, a display-time write signal, and a display-time signal. The read signal is supplied to the frame memory 20. That is, for the frame memory 20 for drawing, the drawing circuit 30 It outputs the supplied drawing address, writing signal for drawing and (in some cases, reading signal for drawing). For the display frame memory 20, the read coordinates X from the read X counter 32 and the read coordinates Y from the read Y counter 33 are output as addresses, and read for display. The display generation read signal from the signal generation circuit 42 is output. Further, when image data is read out from the display frame memory 20 and erase writing is performed, a display write signal from the display write signal generation circuit 41 together with the display read signal is used. Is output.

B. Operation of the embodiment

Next, the operation of the image processing apparatus according to the present embodiment having the above-described configuration will be described. Here, the case where the frame memory 20a is for drawing and the frame memory 20b is for display will be described.

(1) Drawing to frame memory 20a

First, the case of drawing in the frame memory 20a will be described. FIG. 3 shows an example of the frame memory 20a plane. In this case, the drawing circuit 30 reads out the image data of the character CHR 1 specified in the command data of the command RAM 19 from the command RAMI 9 and inputs one dot of the image data as the drawing data. Output to output buffer 4 4. At the same time, the drawing circuit 30 outputs a drawing address to which the frame memory 20a is to be written, and supplies the writing address to the frame memory 20a via the drawing display selector 45. Further, a writing signal for drawing to the frame memory 20a is output from the drawing circuit 30 and supplied to the frame memory 20a as a writing signal by the drawing display selector 45. The drawing data is written from the input / output buffer 44 to the frame memory 20a via the data bus 46 at the timing of the damage signal.

Further, as described above, when the image data already damaged in the frame memory 20a is once read out, subjected to specific processing, and then written back to the frame memory 20a, the drawing circuit is used. A readout signal for drawing is output from 30 and the drawing The image data of the address specified by the dress is read. After the most significant bit is changed or a translucent operation is performed, the image data is written to the same address again by the drawing damage signal.

Similarly, the image data of the characters CHR2 and CHR3 are also written in the frame memory 20a.

(2) Display of frame memory 20b

Next, the frame memory, which is performed simultaneously with the drawing to the frame memory 20a,

The display of the content of 20b will be described with reference to FIG. In this figure, assume that character CHR4 is erased, and characters CHR1 and CHR2 are not erased. That is, the area AR having the upper left coordinates (X 0, Y 0) and the lower right coordinates (X I. Y 1) is set as the area to be erased.

At this time, CPU 15 sets X0 register 34, X1 register 35, and Y0 register

Set the coordinate values X0, XI, Y0, and Υ1 in the 36 and Y1 registers 37, respectively. Then, erase write data to be written to the area AR is set in the erase write data register 38. Here, the erase light data is assumed to be transparent data.

First, a case where a character CHR1 is displayed as a portion other than the area AR will be described. When the read coordinate X is output from the read X counter 32 and the read coordinate Y is output from the read Y counter 33, these read coordinates X and Y are sent to the frame memory 2 O as a read address via the drawing / display selector 45. supplied to b. At this time, the display read signal output from the display read signal generation circuit 42 is turned ON.

The read coordinate X from the read X counter 32 is supplied to the X coordinate comparison circuit 39, and the read coordinate Y from the read Y counter 33 is supplied to the Y coordinate ratio / circuit 40. At this time, since the read coordinates X and Y are at least X and X0 or Y and Y0, at least one of the area signals XHIT and YHIT becomes "0". Therefore, the write signal for display from the display write signal generation circuit 41 is OFF.

Also, when the display read signal from the display read signal generation circuit 42 is ON, As a result, a data input / output control signal is supplied from the input / output control circuit 43 to the input / output buffer 44. As a result, the image data in the frame memory 20 b specified by the read address is input to the input / output buffer 44 via the data bus 46 in accordance with the display read signal. . Then, the image data is supplied to the scroll engine 18 as image data for display, and displayed on a TV monitor (not shown).

Next, a case where the character CHR4 in the area AR is displayed will be described. In this case, as in the above case, the read coordinates X from the read X counter 32 and the read coordinates Y from the read Y counter 33 are passed through the drawing / display selector 45 to the frame memory 2 as a read address. Supplied to 0 b. Also, the display read signal from the display read signal generation circuit 42 becomes ON. Then, the image data from the frame memory 20b is input to the input / output buffer 44 in the same manner as described above by the display read signal, and the scroll engine 18 is input from the input / output buffer 44 to the scroll engine 18. The output will be displayed on the TV screen.

On the other hand, the read coordinates X from the read X counter 32 are supplied to the X coordinate comparison circuit 39, and the read coordinates Y from the read Y counter 33 are supplied to the Y coordinate comparison circuit 40. At this time, since the read coordinate X is X 0 ≤ X ≤ X 1 and the read coordinate Y is Y 0 ≤ Y ≤ Y 1, the area signals X H I Τ and Y H I 双方 are both “1”. Therefore, the write signal for display from the display write signal generation circuit 41 becomes ON.

At this time, as described above, the display-time read signal from the display-read-signal generation circuit 42 changes from ON to 0FF. Therefore, the erase write data set in the erase write data register 38 is output from the input / output buffer 44 by the data input / output control signal. The erase write data is supplied to the frame memory 20b via the data bus 46. In this case, the above-mentioned read address becomes a harmful address, and the erase write data is written at the position indicated by this address. Here, transparent data is written as erase write data.

In this way, the read signal for display is output in the specified area AR. When the image data is read out by specifying the readout address and the write signal for display is output, the readout address becomes the write address, and the erase write data register 3 is set at the position specified by the address. The data set to 8 is written.

C Effect of the embodiment

As described above, according to the present embodiment, since the image data inside the area AR is erased and the image data outside is left, the same image is displayed by setting an arbitrary area AR. In this case, it is not necessary to write the same image data. For this reason, the damage time of image data can be reduced.

Further, in this embodiment, in the area AR, the display-time write signal is output immediately after the display-time read signal is output, and the image data is read out immediately after the image data is read from the read address. Since the race data is written, the image data can be erased in a short time. ◎

Furthermore, since the area AR is rectangular and the area AR is set by designating the four points, the area setting and the coordinate comparison can be easily performed.

[Industrial applicability]

As described above, according to the present invention, when continuously displaying the same image on the monitor, only the specified image data in the frame memory can be erased and the image data to be displayed continuously can be left. However, it is possible to reduce the time for damaging the image data in the frame memory. Therefore, even if the number of dots that can be written does not increase within the image display period for one frame, it is possible to harm the image data of the larger number of dots to the frame memory, and the number of dots is large. Characters can be displayed.

Claims

1. A frame memory control method for writing image data to be displayed on a monitor into a frame memory and reading out the image data from the frame memory for each dot.

When reading out the image data, the coordinates of an arbitrary area on the frame memory and erase data to be harmed as background data in an address in the area are set,

Sequentially generating read addresses which are read positions in the horizontal and vertical directions of the frame memory in dot units;

Comparing the read address with the coordinates of the area,

If the read address is not within the area, the image data is read from the read address of the frame memory;

When the read address is within the area, after reading the image data from the read address of the frame memory, write the erase data to the address.

2. A drawing circuit for writing image data to be displayed on a monitor into a frame memory,

A display circuit that reads the image data from the frame memory in dot units.

The display circuit,

Address generation means for sequentially generating the read position S in the horizontal and vertical directions of the frame memory as a read address in dot units;

A coordinate setting register in which coordinates of an arbitrary area on the frame memory are set; and a coordinate comparison for comparing the read address with the coordinates of the area to determine whether the read address is within the area. Means,

An erase data setting register in which erase data to be written as background data in an address in the area is set; As a result of the determination by the coordinate comparing means, if the read address is not in the area, the image data is read from the read address in the frame memory, and the read address is in the area. And I / O control means for reading the image data and then harming the erase data to the read address.

A frame memory control device comprising:

3. The display circuit according to claim 2,

The read signal generating means for generating a read signal for the frame memory and the coordinate comparing means determine that the read address generated from the address generating means is within the area set in the coordinate setting register. Write signal generating means for generating a write signal immediately after the read signal is generated,

The input / output control means,

An input / output buffer for holding image data read from the read address of the frame memory and erase data set in the erase data setting register;

When the read signal is generated, the image data is read from the frame memory, and when the harmful signal is generated, the erase data is output to the read address of the frame memory. An input / output control circuit that controls the input / output buffer

3. The frame memory control device according to claim 2, comprising:

[Course 4] The frame memory consists of two surfaces,

While the drawing circuit is writing the image data to one of the frame memories, the display circuit reads the image data from the other of the frame memories, and when the writing and reading are completed, Switching between the drawing circuit and the display circuit, the drawing circuit writes the image data to the other of the frame memories, and the display circuit reads the image data from one of the frame memories. Claims characterized by having a display selector Item 3. The frame memory control device according to item 2.

5. The frame memory comprises two surfaces,

While the drawing circuit is poisoning the image data into one of the frame memories, the display circuit reads the image data from the other of the frame memories, and when the writing and reading are completed, Switching between the drawing circuit and the display circuit, the drawing circuit writes the image data to the other of the frame memories, and the display circuit reads the image data from one of the frame memories. The frame memory control device according to claim 3, further comprising a selector.

6. The area,

3. The frame memory control device according to claim 2, wherein four points are specified by a horizontal start point and an end point and a vertical start point and an end point.

7. The area,

4. The frame memory control device according to claim 3, wherein four points are designated by a horizontal start point and an end point and a vertical start point and an end point.

8. The region,

5. The frame memory control device according to claim 4, wherein the rectangle is a rectangle in which four points are specified by a start point and an end point in a horizontal direction and a start point and an end point in a vertical direction.