WO1995030241A1 - Method for passivating the sides of a thin film semiconductor component - Google Patents

Method for passivating the sides of a thin film semiconductor component Download PDF

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Publication number
WO1995030241A1
WO1995030241A1 PCT/FR1995/000572 FR9500572W WO9530241A1 WO 1995030241 A1 WO1995030241 A1 WO 1995030241A1 FR 9500572 W FR9500572 W FR 9500572W WO 9530241 A1 WO9530241 A1 WO 9530241A1
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WIPO (PCT)
Prior art keywords
mesa
semiconductor
level
passivation
manufacturing
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Application number
PCT/FR1995/000572
Other languages
French (fr)
Inventor
Jean-Michel Vignolle
René CHAUDET
Claude Venin
Original Assignee
Thomson-Lcd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson-Lcd filed Critical Thomson-Lcd
Priority to JP7528040A priority Critical patent/JPH09512667A/en
Priority to EP95919467A priority patent/EP0757845A1/en
Publication of WO1995030241A1 publication Critical patent/WO1995030241A1/en
Priority to KR1019960706045A priority patent/KR970703043A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a process for passivation of the sides of a semiconductor component and in particular of a thin film transistor (TFT for Thin Film Transistor in English) making it possible to reduce conduction in the blocking state.
  • TFT Thin Film Transistor
  • This passivation process is particularly well suited to the TFT manufacturing processes used in liquid crystal flat screens with integrated or non-integrated driver circuits.
  • the present invention also relates to a screen obtained by such a manufacturing process.
  • a flat liquid crystal screen consists of a number of electro-optical cells (pixels for "picture elements") arranged in rows and columns, each controlled by a switching device and comprising two electrodes framing a liquid crystal whose properties optics are modified according to the value of the field which passes through it.
  • the addressing by the peripheral control electronics of these pixels is effected by means of the lines (selection lines) which control the on and off state of the switching devices, and of the columns (data lines). transmitting, when the switching device is on, the voltage to be applied across the electrodes corresponding to the data signal to be displayed.
  • the electrodes, the switching devices, the lines and the columns are deposited and etched on the same substrate plate. They constitute the active matrix of the screen.
  • the peripheral control circuits are also integrated on the substrate plate comprising the active matrix.
  • the manufacture of such screens is generally carried out in the following manner: on a non-conductive or passivated substrate plate (for example in glass in the case of projection screen) are deposited and engraved the active matrix (the electrodes, the electrode control transistors, connection lines to peripheral address circuits) and peripheral address circuits in the case of integrated control circuit technology. Then, calibrated shims are made so as to maintain a fixed and constant thickness over the entire screen, between the substrate plate comprising the active matrix, and the counter plate comprising the counter-electrode (s). The liquid crystal will be introduced under vacuum into the volume thus obtained and the whole sealed with an adhesive joint.
  • reverse stage TFT transistors are used as switching devices controlling the pixel electrodes and / or as switching devices for peripheral control circuits, that is to say TFT transistors having the gate directly on the substrate, under the source and drain.
  • FIGS. 1 a to 1 d A method of manufacturing one of these types of TFT transistors is shown in FIGS. 1 a to 1 d.
  • a metal level 2 is deposited and then etched making the gate of the TFT transistor (FIG. 1a).
  • An insulating layer 3 such as for example silicon nitride (SiN), is deposited on the whole of the substrate plate 1 then a semiconductor level 4 of amorphous silicon a-Si and a n + 5 doped semiconductor level (a -If-n +) are deposited and engraved. This produces a semiconductor mesa formed by layers 4 and 5 etched during the same process step ( Figure 1b). A metal layer is then deposited and etched so as to produce the source 6 and drain 7 of the TFT transistor (FIG. 1c). The part of the doped semiconductor level 5 (a-Si-n +) not covered by the source 6 and drain 7 is eliminated (FIG. 1d).
  • SiN silicon nitride
  • the doped semiconductor layer 5 makes it possible to block the injection of carriers when the TFT transistor is polarized in *
  • FIG. 2 representing the curve 8 source-drain current Isd as a function of the gate voltage Vg, illustrates this principle applied to the example of FIG. 1.
  • the current Isd (on the ordinate) is of the order 10 "6 A
  • part 8 'of the curve represents the values of the current Ids in the case of FIG. 1.d. The values of the current Isd then increase due to the absence of semiconductor
  • the part 8 "representing the desired values of the current Isd in the case where there is a doped semiconductor level 5.
  • the present invention relates to a method for manufacturing semiconductor components in thin layers, such as, for example, direct or reverse stage transistors, or diodes, during which a mesa comprising at least one semiconductor level is produced, and is characterized in that it comprises a step of passivation of the etched faces of the semiconductor level of the mesa 0 before the removal of a mask having been used during the etching.
  • This mask protects the parts of the semiconductor not to be oxidized, and was created during the photogravure of the mesa (for example, resin which was used to engrave the mesa).
  • Another important characteristic of the present invention is that the resin used to etch the mesa can be removed during this same step of passivation of the faces of the semiconductor level of the mesa, the passivation technique oxidizing the faces having another characteristic of attacking the resin.
  • the present invention also relates to a liquid crystal display in the manufacturing process of which one of these characteristics is integrated.
  • FIGS. 1a to 1d already described, show a method of manufacturing according to the known art, of a reverse stage TFT transistor
  • FIG. 2 already described, represents the curve of the source-drain current Ids as a function of the values of the gate voltage Vg, in the 0 case of a TFT transistor produced according to the example of FIG. 1,
  • FIGS. 3a to 3d represent a step in the method for manufacturing a reverse stage TFT transistor according to the invention, -
  • FIG. 4 represents a step in the process for manufacturing a direct stage TFT transistor produced according to the invention
  • FIG. 5a represents a sectional view of a diode produced according to the known art
  • Figure 5b shows a sectional view of a diode of the same type as that of the previous figure made according to the invention.
  • 3a shows a sectional view of a TFT transistor reverse stage at the start of the manufacturing phase, of the type made by the example of Figures 1a to 1d.
  • the gate level 2 was deposited and etched on the substrate 1 (FIG. 3a), the insulating level 3 was deposited and the mesa semiconductor level 4 - doped semiconductor level 5 etched on the insulator (FIG. 3b).
  • the flanks 41 and 42 of the mesa are passive, for example, by oxidation, nitriding or oxynitriding, by attacking the substrate plate attacked by a gas of type 02, N2 or N02 in a plasma device.
  • the flanks of the semiconductor level 4 which are not protected by the resin 9 are passive respectively in SiOx, SiNx or SiOxOy on the desired thickness, typically between 100 and 500 A.
  • the resin 9 (FIG. 3c) is removed, and the source 6 and drain 7 of conductive material are deposited and etched in order to completely produce the TFT transistor ( Figure 3d).
  • the leakage current loff is very greatly reduced thanks to this insulating layer without adding any costly or time-consuming step to the process.
  • the steps of passivation and removal of the resin can be carried out simultaneously, this making it possible to save time.
  • the upper surface of the resin is surface oxidized and a standard cleaning of the BHF type is necessary. This operation in front of all the ways to be done at the end of the process to clean the plates, so there is no addition of additional steps.
  • the passivation layer of the sides of the TFT transistor will be an oxide barrier, because the gap of a silicon oxide is of the order of 9eV while that of a nitride is of the order of 5eV.
  • an oxynitride layer can be advantageous because of the very good interface with the semiconductor and because of the quality of the layer obtained, compared with that obtained by oxidation of the semiconductor with 02.
  • a conventional "asher" plasma in French, “which reduces to ash" of the type used to remove the resin can be used.
  • the gas used will be 02 or N2O with a flow rate of 5 sccm for each gas, the power comprised between 600 and 1200 W, under a pressure comprised between 700 and 1500 mT, for a duration comprised between 20 and 60 Mn and at a temperature between 80 and 120 ° c.
  • Another method can be by reactive ion etching ("RIE” for "Reactive Ion Etching” in English), with 02, with a power between 600 and 800 W corresponding respectively to 0.2 and 0.3 Wcm “2 , under a pressure of the order of 100 mT and for a period of between 5 and 20 min.
  • RIE reactive ion etching
  • the passivation of the flanks of the mesa can also be carried out in a plasma dry etching reactor ("Hot Wall Dry Etcher” in English), at a temperature of more than 200 ° C., a pressure of the order of 100 mT, during a duration of the order of 600 s and with an N2O gas.
  • a plasma dry etching reactor ("Hot Wall Dry Etcher” in English)
  • FIG. 4 represents a sectional view of a direct stage TFT transistor.
  • Such transistors can be obtained with only three masking levels.
  • first mask On the substrate plate 1 are deposited and etched the source 10 and drain 1 1 (first mask), a mesa is then carried out comprising a first semiconductor level 12 and a second insulating level 13 (second mask), then a conductor-grid level 14 is deposited and engraved (third mask).
  • second mask second mask
  • third mask a conductor-grid level
  • Figure 5a shows a sectional view of a known PIN diode.
  • a mesa is produced superimposing on a n 20 doped semiconductor layer, a semiconductor layer 21 (for example in a-Si or in SiGe) and a p 22 doped semiconductor layer.
  • An insulating level 23 is then deposited and etched, then the conductive contact 24 is deposited and etched so as to form a contact with the last p-doped semiconductor level 22.
  • a problem of poor insulation between the sides of the mesa and the conductive level 24 can arise and a current unwanted to be established between the two electrodes at the side of the intrinsic semiconductor.
  • the resin used during the etching of the mesa and which remains on the upper part of it will be used to passivate the sides 25 and 26 by oxidation , nitriding or oxynitriding according to the step described above according to the invention. So a ⁇
  • double insulation can be carried out without adding additional complex steps, as shown in FIG. 5b on which appear the passivation layers 27 and 28, or a single insulation can also be carried out by passivation of the sidewalls by eliminating the step of the manufacturing process consisting to deposit then engrave the insulating level 23.
  • the present invention applies to all methods of manufacturing semiconductor type components in thin layers, and particularly to transistors, direct or reverse stages, and diodes constituting the devices for controlling pixel electrodes and integrated peripheral control circuits. or not integrated on the same substrate plate, for flat screens using liquid crystals.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

Method for passivating the sides of a semiconductor component and especially a thin film resistor for reducing conduction in the off state. The method is characterized in that the etched sides (41, 42; 15, 16; 27, 28) of the semiconductor layer (4, 12, 21) of the mesa (4, 5, 9) are passivated before removal of the mask (9) used during etching. The method is applicable to all methods for the manufacture of thin film transistors used in flat liquid cristal screens.

Description

PROCEDE DE PASSIVATION DES FLANCS D'UN COMPOSANT SEMICONDUCTEUR A COUCHES MINCES METHOD FOR PASSIVATING THE SIDINGS OF A THIN FILM SEMICONDUCTOR COMPONENT
La présente invention a pour objet un procédé de passivation des flancs d'un composant semiconducteur et en particulier d'un transistor à couches minces (TFT pour Thin Film Transistor en langue anglaise) permettant de réduire la conduction dans l'état bloquant. Ce procédé de passivation est particulièrement bien adapté aux procédés de fabrication de TFT utilisés dans les écrans plats à cristaux liquides à circuits de commande (drivers) intégrés ou non intégrés. La présente invention a aussi pour objet un écran obtenu par un tel procédé de fabrication.The present invention relates to a process for passivation of the sides of a semiconductor component and in particular of a thin film transistor (TFT for Thin Film Transistor in English) making it possible to reduce conduction in the blocking state. This passivation process is particularly well suited to the TFT manufacturing processes used in liquid crystal flat screens with integrated or non-integrated driver circuits. The present invention also relates to a screen obtained by such a manufacturing process.
Un écran plat à cristaux liquides est constitué d'un certain nombre de cellules électro-optiques (pixels pour "picture éléments") arrangées en lignes et colonnes, commandées chacune par un dispositif de commutation et comportant deux électrodes encadrant un cristal liquide dont les propriétés optiques sont modifiées en fonction de la valeur du champ qui le traverse. L'adressage par l'électronique de commande périphérique de ces pixels s'effectue par l'intermédiaire des lignes (lignes de sélection) qui commandent l'état passant et non-passant des dispositifs de commutation, et des colonnes (lignes de données) transmettant, lorsque le dispositif de commutation est passant, la tension à appliquer aux bornes des électrodes correspondant au signal de données à afficher.A flat liquid crystal screen consists of a number of electro-optical cells (pixels for "picture elements") arranged in rows and columns, each controlled by a switching device and comprising two electrodes framing a liquid crystal whose properties optics are modified according to the value of the field which passes through it. The addressing by the peripheral control electronics of these pixels is effected by means of the lines (selection lines) which control the on and off state of the switching devices, and of the columns (data lines). transmitting, when the switching device is on, the voltage to be applied across the electrodes corresponding to the data signal to be displayed.
Les électrodes, les dispositifs de commutation, les lignes et les colonnes sont déposés et gravés sur une même plaque substrat. Ils constituent la matrice active de l'écran. Avantageusement, les circuits de commande périphériques sont eux aussi intégrés sur la plaque substrat comportant la matrice active. La fabrication de tels écrans s'effectue généralement de la manière suivante: sur une plaque-substrat non-conductrice ou passivée (par exemple en verre dans le cas d'écran à projection) sont déposés et gravés la matrice active (les électrodes, les transistors de commande des électrodes, les lignes de connexions aux circuits d'adressages périphériques) et les circuits d'adressage périphériques dans le cas d'une technologie à circuits de commande intégrés. Puis, des cales d'épaisseurs calibrées sont réalisées de manière à maintenir une épaisseur fixée et constante sur tout l'écran, entre la plaque substrat comportant la matrice active, et la contre plaque comportant la ou les contre-électrodes. Le cristal liquide va être introduit sous vide dans le volume ainsi obtenu et l'ensemble scellé par un joint de colle.The electrodes, the switching devices, the lines and the columns are deposited and etched on the same substrate plate. They constitute the active matrix of the screen. Advantageously, the peripheral control circuits are also integrated on the substrate plate comprising the active matrix. The manufacture of such screens is generally carried out in the following manner: on a non-conductive or passivated substrate plate (for example in glass in the case of projection screen) are deposited and engraved the active matrix (the electrodes, the electrode control transistors, connection lines to peripheral address circuits) and peripheral address circuits in the case of integrated control circuit technology. Then, calibrated shims are made so as to maintain a fixed and constant thickness over the entire screen, between the substrate plate comprising the active matrix, and the counter plate comprising the counter-electrode (s). The liquid crystal will be introduced under vacuum into the volume thus obtained and the whole sealed with an adhesive joint.
Dans certains écrans à cristaux liquides, on utilise comme dispositifs de commutation commandant les électrodes de pixels et/ou comme dispositifs de commutation des circuits de commande périphériques, des transistors TFT étages inverses, c'est à dire, des transistors TFT comportant la grille directement sur le substrat, sous les source et drain. Un procédé de fabrication d'un de ces types de transistors TFT est représenté sur les figures 1 a à 1 d. Sur une plaque- substrat isolante 1 , est déposé puis gravé un niveau de métal 2 réalisant la grille du transistor TFT (figure 1a). Une couche d'isolant 3, comme par exemple du nitrure de silicium (SiN), est déposée sur l'ensemble de la plaque substrat 1 puis un niveau semiconducteur 4 de Silicium amorphe a-Si et un niveau semiconducteur dopé n + 5 (a-Si-n + ) sont déposés et gravés. On réalise ainsi une mesa semiconductrice formée des couches 4 et 5 gravées au cours de la même étape du procédé (figure 1 b). Une couche métallique est ensuite déposée et gravée de manière à réaliser les source 6 et drain 7 du transistor TFT (figure 1c). La partie du niveau semiconducteur dopée 5 (a-Si-n + ) non recouverte par les source 6 et drain 7 est éliminée (figure 1d).In certain liquid crystal displays, reverse stage TFT transistors are used as switching devices controlling the pixel electrodes and / or as switching devices for peripheral control circuits, that is to say TFT transistors having the gate directly on the substrate, under the source and drain. A method of manufacturing one of these types of TFT transistors is shown in FIGS. 1 a to 1 d. On a insulating substrate plate 1, a metal level 2 is deposited and then etched making the gate of the TFT transistor (FIG. 1a). An insulating layer 3, such as for example silicon nitride (SiN), is deposited on the whole of the substrate plate 1 then a semiconductor level 4 of amorphous silicon a-Si and a n + 5 doped semiconductor level (a -If-n +) are deposited and engraved. This produces a semiconductor mesa formed by layers 4 and 5 etched during the same process step (Figure 1b). A metal layer is then deposited and etched so as to produce the source 6 and drain 7 of the TFT transistor (FIG. 1c). The part of the doped semiconductor level 5 (a-Si-n +) not covered by the source 6 and drain 7 is eliminated (FIG. 1d).
Dans l'état bloqué, la couche semiconductrice dopée 5 permet de bloquer l'injection de porteurs lorsque le transistor TFT est polarisé en *In the blocked state, the doped semiconductor layer 5 makes it possible to block the injection of carriers when the TFT transistor is polarized in *
inverse, afin que le courant de fuite loff entre les source 6 et drain 7 soit le plus faible possible. Or, sur une telle structure, les flancs 41 et 42 de la mesa ne sont pas recouverts par la couche de semiconducteur dopée 5, et il y a injection de porteurs par ses flancs dans le niveau 5 semiconducteur 4, la conséquence étant que le courant de fuite loff augmente pour des tensions de grille Vg très négatives. La figure 2 représentant la courbe 8 courant source-drain Isd en fonction de la tension de grille Vg, illustre ce principe appliqué à l'exemple de la figure 1. Dans cet exemple, le courant Isd (en ordonnée) est de l'ordre 10"6 Areverse, so that the leakage current loff between the source 6 and drain 7 is as low as possible. However, on such a structure, the flanks 41 and 42 of the mesa are not covered by the doped semiconductor layer 5, and there is injection of carriers by its flanks in the semiconductor level 5, the consequence being that the current Loff leakage increases for very negative gate voltages Vg. FIG. 2 representing the curve 8 source-drain current Isd as a function of the gate voltage Vg, illustrates this principle applied to the example of FIG. 1. In this example, the current Isd (on the ordinate) is of the order 10 "6 A
10 (état passant) lorsque la tension de grille Vg (en abscisse) est positive jusqu'à 20 Volts, et de l'ordre de 10"12 à 1O 4 A (état bloqué) lorsque la tension de grille Vg est négative. La partie 8' de la courbe représente les valeurs du courant Ids dans le cas de la figure 1.d. Les valeurs du courant Isd augmentent alors du fait de l'absence de semiconducteur10 (on state) when the gate voltage Vg (on the abscissa) is positive up to 20 Volts, and of the order of 10 "12 to 10 4 A (blocked state) when the gate voltage Vg is negative. part 8 'of the curve represents the values of the current Ids in the case of FIG. 1.d. The values of the current Isd then increase due to the absence of semiconductor
15 dopé sur le flanc 42 du semiconducteur 4, la partie 8" représentant les valeurs souhaitées du courant Isd dans le cas où il y a un niveau semiconducteur dopé 5.15 doped on the side 42 of the semiconductor 4, the part 8 "representing the desired values of the current Isd in the case where there is a doped semiconductor level 5.
Pour pallier à cet inconvénient, plusieurs solutions sont actuellement proposées. La première consiste à déposer et graver laTo overcome this drawback, several solutions are currently proposed. The first is to file and engrave the
20 couche semiconductrice dopée 5 de manière à ce qu'elle recouvre totalement la mesa formée par le niveau semiconducteur 4 seul. Cette solution ajoute au procédé de fabrication un dépôt, une photolithographie et une gravure. De même, une seconde solution consiste à intégrer au procédé de fabrication de la figure 1 , une étape intermédiaire après la20 doped semiconductor layer 5 so that it completely covers the mesa formed by the semiconductor level 4 alone. This solution adds to the manufacturing process a deposit, a photolithography and an etching. Similarly, a second solution consists in integrating into the manufacturing process of FIG. 1, an intermediate step after the
25 gravure de la mesa, de dépôt, photolithographie et gravure d'un isolant du type SiO2, SiN ou SiOxNy sur les flancs 41 et 42 de la mesa semiconducteur 4-semiconducteur dopé 5. Cette solution ajoute au procédé une étape supplémentaire complexe du fait de l'alignement critique à observer pour graver l'isolant.25 etching of the mesa, deposition, photolithography and etching of an insulator of the SiO2, SiN or SiOxNy type on the flanks 41 and 42 of the mesa semiconductor 4-doped semiconductor 5. This solution adds to the process an additional complex step because of the critical alignment to be observed for etching the insulation.
30 La présente solution permet d'obtenir un courant de fuite très faible équivalent à ceux obtenus par les procédés de l'art antérieur évoqués plus haut ou du moins suffisamment faible dans la gamme de A The present solution makes it possible to obtain a very low leakage current equivalent to those obtained by the methods of the prior art mentioned above or at least sufficiently low in the range of AT
tension utilisée, grâce à un procédé de fabrication simple et économique ne nécessitant pas d'étapes supplémentaires complexes comme celles que les solutions de l'art connu proposent.voltage used, thanks to a simple and economical manufacturing process which does not require complex additional steps such as those which the solutions of the known art offer.
En effet, la présente invention concerne un procédé de 5 fabrication de composants semiconducteurs en couches minces, comme par exemple, des transistors étages directs ou inverses, ou des diodes, au cours duquel est réalisée une mesa comportant au moins un niveau semiconducteur, et est caractérisé en ce qu'il comporte une étape de passivation des faces gravées du niveau semiconducteur de la mesa 0 avant le retrait d'un masque ayant servi lors de la gravure. Ce masque protège les parties du semiconducteur à ne pas oxyder, et a été créé au cour de la photogravure de la mesa (par exemple, résine qui a servi à graver la mesa).In fact, the present invention relates to a method for manufacturing semiconductor components in thin layers, such as, for example, direct or reverse stage transistors, or diodes, during which a mesa comprising at least one semiconductor level is produced, and is characterized in that it comprises a step of passivation of the etched faces of the semiconductor level of the mesa 0 before the removal of a mask having been used during the etching. This mask protects the parts of the semiconductor not to be oxidized, and was created during the photogravure of the mesa (for example, resin which was used to engrave the mesa).
Une autre caractéristique importante de la présente invention 5 est que la résine ayant servi à la gravure de la mesa peut être retirée au cours de cette même étape de passivation des faces du niveau semiconducteur de la mesa, la technique de passivation oxydant les faces ayant pour autre caractéristique d'attaquer la résine.Another important characteristic of the present invention is that the resin used to etch the mesa can be removed during this same step of passivation of the faces of the semiconductor level of the mesa, the passivation technique oxidizing the faces having another characteristic of attacking the resin.
La présente invention concerne aussi un écran à cristaux 0 liquides dans le procédé de fabrication duquel est intégré une de ces caractéristiques.The present invention also relates to a liquid crystal display in the manufacturing process of which one of these characteristics is integrated.
La présente invention sera mieux comprise et des avantages supplémentaires apparaîtront à la lecture de la description qui va suivre 5 illustrée par les figures suivantes:The present invention will be better understood and additional advantages will appear on reading the description which follows, illustrated by the following figures:
. les figures 1a à 1d déjà décrites, représentent un procédé de fabrication selon l'art connu, d'un transistor TFT étage inverse,. FIGS. 1a to 1d already described, show a method of manufacturing according to the known art, of a reverse stage TFT transistor,
. la figure 2 déjà décrite, représente la courbe du courant Ids source-drain en fonction des valeurs de la tension de grille Vg, dans le 0 cas d'un transistor TFT réalisé selon l'exemple de la figure 1 ,. FIG. 2 already described, represents the curve of the source-drain current Ids as a function of the values of the gate voltage Vg, in the 0 case of a TFT transistor produced according to the example of FIG. 1,
. les figures 3a à 3d représentent une étape du procédé de fabrication d'un transistor TFT étage inverse selon l'invention, -. FIGS. 3a to 3d represent a step in the method for manufacturing a reverse stage TFT transistor according to the invention, -
. la figure 4 représente une étape du procédé de fabrication d'un transistor TFT étage direct réalisé selon l'invention,. FIG. 4 represents a step in the process for manufacturing a direct stage TFT transistor produced according to the invention,
. la figure 5a représente une vue en coupe d'une diode réalisée selon l'art connu, . et la figure 5b représente une vue en coupe d'une diode du même type que celle de la figure précédente réalisée selon l'invention.. FIG. 5a represents a sectional view of a diode produced according to the known art,. and Figure 5b shows a sectional view of a diode of the same type as that of the previous figure made according to the invention.
Par soucis de clareté, sur les différentes figures, les mêmes éléments ont gardé les mêmes référence. La figure 3a représente une vue en coupe d'un transistor TFT étage inverse en début de phase de fabrication, du type de celui réalisé par l'exemple des figures 1a à 1d. Le niveau de grille 2 a été déposé et gravé sur le substrat 1 (figure 3a), le niveau isolant 3 a été déposé et la mesa niveau semiconducteur 4 - niveau semiconducteur dopé 5 gravée sur l'isolant (figure 3b). Avant de retirer la partie 9 de la résine ayant servi à la gravure de la mesa, les flancs 41 et 42 de la mesa sont passives, par exemple, par oxydation, nituration ou oxynitruration, en attaquant la plaque-substrat attaquée par un gaz de type 02, N2 ou N02 dans un appareil à plasma. Ainsi, les flancs du niveau semiconducteur 4 qui ne sont pas protégés par la résine 9 sont passives respectivement en SiOx, SiNx ou SiOxOy sur l'épaisseur désirée, typiquement entre 100 et 500 A. Après cette passivation, la résine 9 (figure 3c) est retirée, et les source 6 et drain 7 en matériau conducteur sont déposés et gravés afin de réaliser totalement le transistor TFT (figure 3d). Ainsi, le courant de fuite loff est très fortement diminué grâce à cette couche isolante sans pour cela rajouter aucune étape coûteuse ou longue au procédé.For the sake of clarity, in the different figures, the same elements have kept the same reference. 3a shows a sectional view of a TFT transistor reverse stage at the start of the manufacturing phase, of the type made by the example of Figures 1a to 1d. The gate level 2 was deposited and etched on the substrate 1 (FIG. 3a), the insulating level 3 was deposited and the mesa semiconductor level 4 - doped semiconductor level 5 etched on the insulator (FIG. 3b). Before removing the part 9 of the resin used to etch the mesa, the flanks 41 and 42 of the mesa are passive, for example, by oxidation, nitriding or oxynitriding, by attacking the substrate plate attacked by a gas of type 02, N2 or N02 in a plasma device. Thus, the flanks of the semiconductor level 4 which are not protected by the resin 9 are passive respectively in SiOx, SiNx or SiOxOy on the desired thickness, typically between 100 and 500 A. After this passivation, the resin 9 (FIG. 3c) is removed, and the source 6 and drain 7 of conductive material are deposited and etched in order to completely produce the TFT transistor (Figure 3d). Thus, the leakage current loff is very greatly reduced thanks to this insulating layer without adding any costly or time-consuming step to the process.
Avantageusement, les étapes de passivation et de retrait de la résine peuvent être faites simultanément, cela permettant de gagner du temps. Dans ce cas, à la fin de la gravure de la résine, la surface supérieure de la résine est oxydée superficiellement et un nettoyage standard du type BHF est nécessaire. Cette opération devant de toutes les façons être faite en fin de procédé pour nettoyer les plaques, il n'y a donc pas d'ajout d'étapes supplémentaires.Advantageously, the steps of passivation and removal of the resin can be carried out simultaneously, this making it possible to save time. In this case, at the end of the etching of the resin, the upper surface of the resin is surface oxidized and a standard cleaning of the BHF type is necessary. This operation in front of all the ways to be done at the end of the process to clean the plates, so there is no addition of additional steps.
De préférence la couche de passivation des flancs du transistor TFT sera une barrière d'oxydes, car le gap d'un oxyde de Silicium est de Tordre de 9eV alors que celui d'un nitrure est de Tordre de 5eV. Cependant, une couche d'oxynitrure peut être intéressante du fait de la très bonne interface avec le semiconducteur et du fait de la qualité de la couche obtenue, comparée à celle obtenue par oxydation du semiconducteur avec du 02. L'article de Atsushi MASUDA et al "Novel oxidation process of hydrogenated amorphous silicon utilizing nitrous oxide plasma" (Appl.Phys.Lett.61 du 17 août 1992) décrit un tel traitement ainsi que ses avantages.Preferably the passivation layer of the sides of the TFT transistor will be an oxide barrier, because the gap of a silicon oxide is of the order of 9eV while that of a nitride is of the order of 5eV. However, an oxynitride layer can be advantageous because of the very good interface with the semiconductor and because of the quality of the layer obtained, compared with that obtained by oxidation of the semiconductor with 02. The article by Atsushi MASUDA and al "Novel oxidation process of hydrogenated amorphous silicon utilizing nitrous oxide plasma" (Appl.Phys.Lett.61 of August 17, 1992) describes such a treatment as well as its advantages.
Pour passiver les flancs du semiconducteur, plusieurs méthodes peuvent être utilisées. Par exemple, un plasma "asher" (en français, "qui réduit en cendre") conventionnel du type de ceux utilisés pour retirer la résine peut être utilisé. De préférence, le gaz utilisé sera du 02 ou N2O avec un débit de 5 sccm pour chaque gaz, la puissance comprise entre 600 et 1200 W, sous une pression comprise entre 700 et 1500 mT, pendant une durée comprise entre 20 et 60 Mn et sous une température comprise entre 80 etr 120°c.Several methods can be used to passivate the sides of the semiconductor. For example, a conventional "asher" plasma (in French, "which reduces to ash") of the type used to remove the resin can be used. Preferably, the gas used will be 02 or N2O with a flow rate of 5 sccm for each gas, the power comprised between 600 and 1200 W, under a pressure comprised between 700 and 1500 mT, for a duration comprised between 20 and 60 Mn and at a temperature between 80 and 120 ° c.
Une autre méthode peut être par gravure par ions réactifs ("RIE" pour "Reactive Ion Etching" en langue anglaise), avec du 02, avec une puissance entre 600 et 800 W correspondant respectivement à 0,2 et 0,3 Wcm"2 , sous une pression de Tordre de 100 mT et pendant une durée comprise entre 5 et 20 mn.Another method can be by reactive ion etching ("RIE" for "Reactive Ion Etching" in English), with 02, with a power between 600 and 800 W corresponding respectively to 0.2 and 0.3 Wcm "2 , under a pressure of the order of 100 mT and for a period of between 5 and 20 min.
La passivatrion des flancs de la mesa peut aussi être effectuée dans un réacteur de gravure sèche par plasma ("Hot Wall Dry Etcher" en langue anglaise), sous une température de plus de 200°c, une pression de Tordre de 100 mT, pendant une durée de Tordre de 600 s et avec un gaz de N2O.The passivation of the flanks of the mesa can also be carried out in a plasma dry etching reactor ("Hot Wall Dry Etcher" in English), at a temperature of more than 200 ° C., a pressure of the order of 100 mT, during a duration of the order of 600 s and with an N2O gas.
Le procédé selon l'invention décrit plus haut peut être aussi appliqué à la fabrication de transistors TFT étages directs, c'est à dire comportant les source et drain entre la plaque-substrat et la grille. La figure 4 représente une vue en coupe d'un transistor TFT étage direct. De tels transistors peuvent être obtenus avec seulement trois niveaux de masquage. Sur la plaque substrat 1 sont déposés et gravés les source 10 et drain 1 1 (premier masque), une mesa est ensuite réalisée comportant un premier niveau semiconducteur 12 et un second niveau isolant 13 (second masque), puis un niveau conducteur-grille 14 est déposé et gravé (troisième masque). Il apparaît des zones critiques qui sont les flancs 15 et 16 du niveau semiconducteur 12 en contact direct avec le niveau conducteur-grille 14. Tous les risques de court-circuits peuvent être annulés en passivant ces zones, par ajout d'une étape supplémentaire après la gravure de la mesa, selon l'invention dans son procédé de fabrication. Cette étape consistant à se servir de la résine utilisée lors de la gravure de la mesa, pour oxyder, nitrurer ou oxynitrurer les flancs du transistor TFT de la figure 4, comme cela est expicité plus haut.The method according to the invention described above can also be applied to the manufacture of direct stage TFT transistors, that is to say comprising the source and drain between the substrate plate and the grid. FIG. 4 represents a sectional view of a direct stage TFT transistor. Such transistors can be obtained with only three masking levels. On the substrate plate 1 are deposited and etched the source 10 and drain 1 1 (first mask), a mesa is then carried out comprising a first semiconductor level 12 and a second insulating level 13 (second mask), then a conductor-grid level 14 is deposited and engraved (third mask). There appear to be critical zones which are the sides 15 and 16 of the semiconductor level 12 in direct contact with the conductor-grid level 14. All risks of short-circuits can be eliminated by passivating these zones, by adding an additional step after etching the mesa according to the invention in its manufacturing process. This step consisting in using the resin used during the etching of the mesa, to oxidize, nitride or oxynitride the sides of the TFT transistor of FIG. 4, as explained above.
Le procédé selon l'invention peut être aussi être appliqué à la fabrication de diodes. La figure 5a représente une vue en coupe d'une diode PIN connue. Sur une plaque-substrat isolante 1 , une mesa est réalisée superposant à une couche semiconductrice dopée n 20, une couche semiconductrice 21 (par exemple en a-Si ou en SiGe) et une couche semiconductrice dopée p 22. Un niveau isolant 23 est ensuite déposé et gravé, puis le contact conducteur 24 est déposé et gravé de manière à former un contact avec le dernier niveau semiconducteur dopé p 22. Un problème de mauvaise isolation entre les flancs de la mesa et le niveau conducteur 24 peut se poser et un courant non désiré s'établir entre les deux électrodes au niveau du flanc du semiconducteur intrinsèque. De la même manière que précédemment, au cours du procédé de fabrication de la diode, la résine utilisée lors de la gravure de la mesa et qui reste sur la partie supérieure de celle-ci va être utilisée pour passiver les flancs 25 et 26 par oxydation, nitruration ou oxynitruration selon l'étape décrite plus haut selon l'invention. Ainsi, une β The method according to the invention can also be applied to the manufacture of diodes. Figure 5a shows a sectional view of a known PIN diode. On an insulating substrate plate 1, a mesa is produced superimposing on a n 20 doped semiconductor layer, a semiconductor layer 21 (for example in a-Si or in SiGe) and a p 22 doped semiconductor layer. An insulating level 23 is then deposited and etched, then the conductive contact 24 is deposited and etched so as to form a contact with the last p-doped semiconductor level 22. A problem of poor insulation between the sides of the mesa and the conductive level 24 can arise and a current unwanted to be established between the two electrodes at the side of the intrinsic semiconductor. In the same way as previously, during the diode manufacturing process, the resin used during the etching of the mesa and which remains on the upper part of it will be used to passivate the sides 25 and 26 by oxidation , nitriding or oxynitriding according to the step described above according to the invention. So a β
double isolation peut être réalisée sans ajouter d'étapes complexes supplémentaires, comme indiqué sur la figure 5b sur laquelle apparaissent les couches de passivation 27 et 28, ou une isolation unique peut aussi être réalisée par passivation des flancs en éliminant Tétape du procédé de fabrication consistant à déposer puis graver le niveau isolant 23.double insulation can be carried out without adding additional complex steps, as shown in FIG. 5b on which appear the passivation layers 27 and 28, or a single insulation can also be carried out by passivation of the sidewalls by eliminating the step of the manufacturing process consisting to deposit then engrave the insulating level 23.
La présente invention s'applique à tous les procédé de fabrication de composants de type semiconducteur en couches minces, et particulièrement aux transistors, étages direct ou inverse, et diodes constituant les dispositifs de commande des électrodes de pixels et des circuits de commande périphériques, intégrés ou non intégrés sur la même plaque substrat, pour les écrans plats utilisant des cristaux liquides. The present invention applies to all methods of manufacturing semiconductor type components in thin layers, and particularly to transistors, direct or reverse stages, and diodes constituting the devices for controlling pixel electrodes and integrated peripheral control circuits. or not integrated on the same substrate plate, for flat screens using liquid crystals.

Claims

0 REVENDICATIONS 0 CLAIMS
1. Procédé de fabrication de composants semiconducteurs en couches minces au cours duquel est réalisée une mesa (4,5,9) comportant au moins un niveau semiconducteur (4), caractérisé en ce qu'il comporte une étape de passivation des faces gravées (41 ,42;15,16;27,28) du niveau semiconducteur (4,12,21 ) de la mesa (4,5,9) avant le retrait d'un masque de résine (9) ayant servi lors de la gravure.1. Method for manufacturing semiconductor components in thin layers during which a mesa (4,5,9) is produced comprising at least one semiconductor level (4), characterized in that it comprises a step of passivation of the etched faces ( 41, 42; 15.16; 27.28) of the semiconductor level (4,12,21) of the mesa (4,5,9) before the removal of a resin mask (9) which was used during the etching .
2. Procédé de fabrication de composants semiconducteurs en couches minces selon la revendication 1 , caractérisé en ce que la résine (9) ayant servi à la gravure de ia mesa (4,5,9) est retirée au cours d'une seconde étape, après Tétape de passivation des faces (41 ,42;15,16;27,28) du niveau semiconducteur (4,12,21 ) de la mesa (4,5,9).2. A method for manufacturing semiconductor components in thin layers according to claim 1, characterized in that the resin (9) used for etching ia mesa (4,5,9) is removed during a second step, after the step of passivation of the faces (41, 42; 15.16; 27.28) of the semiconductor level (4,12,21) of the mesa (4,5,9).
3. Procédé de fabrication de composants semiconducteurs en couches minces selon la revendication 1 , caractérisé en ce que la résine (9) ayant servi à la gravure de ;a mesa (4,5,9) est retirée pendant Tétape de passivation des faces (41 ,42;15,16;27,28) du niveau semiconducteur (4,12,21 ) de la mesa (4,5,9).3. Method for manufacturing semiconductor components in thin layers according to claim 1, characterized in that the resin (9) used for the etching of; a mesa (4,5,9) is removed during the passivation step of the faces ( 41, 42; 15.16; 27.28) of the semiconductor level (4,12,21) of the mesa (4,5,9).
4. Procédé de fabrication de composants semiconducteurs en couches minces selon Tune qualconque des revendications précédentes, caractérisé en ce que la passivation des faces (41 ,42;15,16;27,28) du niveau semiconducteur (4,12,21 ) de la mesa (4,5,9) est réalisée par oxydation, nitruration ou oxynitruration.4. A method of manufacturing semiconductor components in thin layers according to one of the preceding claims, characterized in that the passivation of the faces (41, 42; 15.16; 27.28) of the semiconductor level (4,12,21) the mesa (4,5,9) is carried out by oxidation, nitriding or oxynitriding.
5. Procédé de fabrication de composants semiconducteurs en couches minces selon la revendication 4, caractérisé en ce que la passivation des faces (41 ,42;15,16;27,28) du niveau semiconducteur J0 95/005725. A method of manufacturing semiconductor components in thin layers according to claim 4, characterized in that the passivation of the faces (41, 42; 15.16; 27.28) of the semiconductor level J0 95/00572
(4,12,21 ) de la mesa (4,5,9) est réalisée grâce à un plasma de type "Asher".(4,12,21) of the mesa (4,5,9) is carried out using a plasma of the "Asher" type.
6. Procédé de fabrication de composants semiconducteurs en couches minces selon la revendication 4, caractérisé en ce que la passivation des faces (41 ,42;15,16;27,28) du niveau semiconducteur6. A method of manufacturing semiconductor components in thin layers according to claim 4, characterized in that the passivation of the faces (41, 42; 15.16; 27.28) of the semiconductor level
(4,12,21 ) de la mesa (4,5,9) est réalisée grâce à une méthode de type gravure par ions réactifs.(4,12,21) of the mesa (4,5,9) is carried out using a method of the etching type using reactive ions.
7. Procédé de fabrication de composants semiconducteurs en couches minces selon la revendication 4, caractérisé en ce que la passivation des faces (41 ,42;15,16;27,28) du niveau semiconducteur (4,12,21 ) de la mesa (4,5,9) est réalisée grâce à un réacteur de gravure sèche par plasma.7. A method of manufacturing semiconductor components in thin layers according to claim 4, characterized in that the passivation of the faces (41, 42; 15.16; 27.28) of the semiconductor level (4,12,21) of the mesa (4,5,9) is carried out using a plasma dry etching reactor.
8. Procédé de fabrication de composants semiconducteurs en couches minces selon Tune quelconque des revendications précédentes, caractérisé en ce que le composant semiconducteur est un transistor étage direct ou inverse, ou une diode.8. A method of manufacturing semiconductor components in thin layers according to any one of the preceding claims, characterized in that the semiconductor component is a direct or reverse stage transistor, or a diode.
9. Procédé selon Tune des revendications précédentes, caractérisé en ce qu'il s'intègre à un procédé de fabrication d'un écran plat à cristaux liquide.9. Method according to one of the preceding claims, characterized in that it is integrated into a method of manufacturing a flat liquid crystal screen.
10. Ecran plat à cristaux liquide, caractérisé en ce qu'il est réalisé par un procédé de fabrication dans lequel est intégré le procédé de fabrication de composants semiconducteurs selon Tune quelconque des revendications 1 à 9. 10. Flat liquid crystal screen, characterized in that it is produced by a manufacturing process in which the manufacturing process for semiconductor components is integrated according to any one of claims 1 to 9.
PCT/FR1995/000572 1994-04-29 1995-05-02 Method for passivating the sides of a thin film semiconductor component WO1995030241A1 (en)

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EP95919467A EP0757845A1 (en) 1994-04-29 1995-05-02 Method for passivating the sides of a thin film semiconductor component
KR1019960706045A KR970703043A (en) 1994-04-29 1996-10-28 Method for passivating the sides of a thin film semiconductor component

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JPH09512667A (en) 1997-12-16

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