EP0757845A1 - Method for passivating the sides of a thin film semiconductor component - Google Patents
Method for passivating the sides of a thin film semiconductor componentInfo
- Publication number
- EP0757845A1 EP0757845A1 EP95919467A EP95919467A EP0757845A1 EP 0757845 A1 EP0757845 A1 EP 0757845A1 EP 95919467 A EP95919467 A EP 95919467A EP 95919467 A EP95919467 A EP 95919467A EP 0757845 A1 EP0757845 A1 EP 0757845A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- mesa
- semiconductor
- level
- passivation
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000010409 thin film Substances 0.000 title abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000002161 passivation Methods 0.000 claims description 18
- 239000011347 resin Substances 0.000 claims description 15
- 229920005989 resin Polymers 0.000 claims description 15
- 239000004973 liquid crystal related substance Substances 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000005121 nitriding Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 abstract 2
- 239000007788 liquid Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 13
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009432 framing Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a process for passivation of the sides of a semiconductor component and in particular of a thin film transistor (TFT for Thin Film Transistor in English) making it possible to reduce conduction in the blocking state.
- TFT Thin Film Transistor
- This passivation process is particularly well suited to the TFT manufacturing processes used in liquid crystal flat screens with integrated or non-integrated driver circuits.
- the present invention also relates to a screen obtained by such a manufacturing process.
- a flat liquid crystal screen consists of a number of electro-optical cells (pixels for "picture elements") arranged in rows and columns, each controlled by a switching device and comprising two electrodes framing a liquid crystal whose properties optics are modified according to the value of the field which passes through it.
- the addressing by the peripheral control electronics of these pixels is effected by means of the lines (selection lines) which control the on and off state of the switching devices, and of the columns (data lines). transmitting, when the switching device is on, the voltage to be applied across the electrodes corresponding to the data signal to be displayed.
- the electrodes, the switching devices, the lines and the columns are deposited and etched on the same substrate plate. They constitute the active matrix of the screen.
- the peripheral control circuits are also integrated on the substrate plate comprising the active matrix.
- the manufacture of such screens is generally carried out in the following manner: on a non-conductive or passivated substrate plate (for example in glass in the case of projection screen) are deposited and engraved the active matrix (the electrodes, the electrode control transistors, connection lines to peripheral address circuits) and peripheral address circuits in the case of integrated control circuit technology. Then, calibrated shims are made so as to maintain a fixed and constant thickness over the entire screen, between the substrate plate comprising the active matrix, and the counter plate comprising the counter-electrode (s). The liquid crystal will be introduced under vacuum into the volume thus obtained and the whole sealed with an adhesive joint.
- reverse stage TFT transistors are used as switching devices controlling the pixel electrodes and / or as switching devices for peripheral control circuits, that is to say TFT transistors having the gate directly on the substrate, under the source and drain.
- FIGS. 1 a to 1 d A method of manufacturing one of these types of TFT transistors is shown in FIGS. 1 a to 1 d.
- a metal level 2 is deposited and then etched making the gate of the TFT transistor (FIG. 1a).
- An insulating layer 3 such as for example silicon nitride (SiN), is deposited on the whole of the substrate plate 1 then a semiconductor level 4 of amorphous silicon a-Si and a n + 5 doped semiconductor level (a -If-n +) are deposited and engraved. This produces a semiconductor mesa formed by layers 4 and 5 etched during the same process step ( Figure 1b). A metal layer is then deposited and etched so as to produce the source 6 and drain 7 of the TFT transistor (FIG. 1c). The part of the doped semiconductor level 5 (a-Si-n +) not covered by the source 6 and drain 7 is eliminated (FIG. 1d).
- SiN silicon nitride
- the doped semiconductor layer 5 makes it possible to block the injection of carriers when the TFT transistor is polarized in *
- FIG. 2 representing the curve 8 source-drain current Isd as a function of the gate voltage Vg, illustrates this principle applied to the example of FIG. 1.
- the current Isd (on the ordinate) is of the order 10 "6 A
- part 8 'of the curve represents the values of the current Ids in the case of FIG. 1.d. The values of the current Isd then increase due to the absence of semiconductor
- the part 8 "representing the desired values of the current Isd in the case where there is a doped semiconductor level 5.
- the present invention relates to a method for manufacturing semiconductor components in thin layers, such as, for example, direct or reverse stage transistors, or diodes, during which a mesa comprising at least one semiconductor level is produced, and is characterized in that it comprises a step of passivation of the etched faces of the semiconductor level of the mesa 0 before the removal of a mask having been used during the etching.
- This mask protects the parts of the semiconductor not to be oxidized, and was created during the photogravure of the mesa (for example, resin which was used to engrave the mesa).
- Another important characteristic of the present invention is that the resin used to etch the mesa can be removed during this same step of passivation of the faces of the semiconductor level of the mesa, the passivation technique oxidizing the faces having another characteristic of attacking the resin.
- the present invention also relates to a liquid crystal display in the manufacturing process of which one of these characteristics is integrated.
- FIGS. 1a to 1d already described, show a method of manufacturing according to the known art, of a reverse stage TFT transistor
- FIG. 2 already described, represents the curve of the source-drain current Ids as a function of the values of the gate voltage Vg, in the 0 case of a TFT transistor produced according to the example of FIG. 1,
- FIGS. 3a to 3d represent a step in the method for manufacturing a reverse stage TFT transistor according to the invention, -
- FIG. 4 represents a step in the process for manufacturing a direct stage TFT transistor produced according to the invention
- FIG. 5a represents a sectional view of a diode produced according to the known art
- Figure 5b shows a sectional view of a diode of the same type as that of the previous figure made according to the invention.
- 3a shows a sectional view of a TFT transistor reverse stage at the start of the manufacturing phase, of the type made by the example of Figures 1a to 1d.
- the gate level 2 was deposited and etched on the substrate 1 (FIG. 3a), the insulating level 3 was deposited and the mesa semiconductor level 4 - doped semiconductor level 5 etched on the insulator (FIG. 3b).
- the flanks 41 and 42 of the mesa are passive, for example, by oxidation, nitriding or oxynitriding, by attacking the substrate plate attacked by a gas of type 02, N2 or N02 in a plasma device.
- the flanks of the semiconductor level 4 which are not protected by the resin 9 are passive respectively in SiOx, SiNx or SiOxOy on the desired thickness, typically between 100 and 500 A.
- the resin 9 (FIG. 3c) is removed, and the source 6 and drain 7 of conductive material are deposited and etched in order to completely produce the TFT transistor ( Figure 3d).
- the leakage current loff is very greatly reduced thanks to this insulating layer without adding any costly or time-consuming step to the process.
- the steps of passivation and removal of the resin can be carried out simultaneously, this making it possible to save time.
- the upper surface of the resin is surface oxidized and a standard cleaning of the BHF type is necessary. This operation in front of all the ways to be done at the end of the process to clean the plates, so there is no addition of additional steps.
- the passivation layer of the sides of the TFT transistor will be an oxide barrier, because the gap of a silicon oxide is of the order of 9eV while that of a nitride is of the order of 5eV.
- an oxynitride layer can be advantageous because of the very good interface with the semiconductor and because of the quality of the layer obtained, compared with that obtained by oxidation of the semiconductor with 02.
- a conventional "asher" plasma in French, “which reduces to ash" of the type used to remove the resin can be used.
- the gas used will be 02 or N2O with a flow rate of 5 sccm for each gas, the power comprised between 600 and 1200 W, under a pressure comprised between 700 and 1500 mT, for a duration comprised between 20 and 60 Mn and at a temperature between 80 and 120 ° c.
- Another method can be by reactive ion etching ("RIE” for "Reactive Ion Etching” in English), with 02, with a power between 600 and 800 W corresponding respectively to 0.2 and 0.3 Wcm “2 , under a pressure of the order of 100 mT and for a period of between 5 and 20 min.
- RIE reactive ion etching
- the passivation of the flanks of the mesa can also be carried out in a plasma dry etching reactor ("Hot Wall Dry Etcher” in English), at a temperature of more than 200 ° C., a pressure of the order of 100 mT, during a duration of the order of 600 s and with an N2O gas.
- a plasma dry etching reactor ("Hot Wall Dry Etcher” in English)
- FIG. 4 represents a sectional view of a direct stage TFT transistor.
- Such transistors can be obtained with only three masking levels.
- first mask On the substrate plate 1 are deposited and etched the source 10 and drain 1 1 (first mask), a mesa is then carried out comprising a first semiconductor level 12 and a second insulating level 13 (second mask), then a conductor-grid level 14 is deposited and engraved (third mask).
- second mask second mask
- third mask a conductor-grid level
- Figure 5a shows a sectional view of a known PIN diode.
- a mesa is produced superimposing on a n 20 doped semiconductor layer, a semiconductor layer 21 (for example in a-Si or in SiGe) and a p 22 doped semiconductor layer.
- An insulating level 23 is then deposited and etched, then the conductive contact 24 is deposited and etched so as to form a contact with the last p-doped semiconductor level 22.
- a problem of poor insulation between the sides of the mesa and the conductive level 24 can arise and a current unwanted to be established between the two electrodes at the side of the intrinsic semiconductor.
- the resin used during the etching of the mesa and which remains on the upper part of it will be used to passivate the sides 25 and 26 by oxidation , nitriding or oxynitriding according to the step described above according to the invention. So a ⁇
- double insulation can be carried out without adding additional complex steps, as shown in FIG. 5b on which appear the passivation layers 27 and 28, or a single insulation can also be carried out by passivation of the sidewalls by eliminating the step of the manufacturing process consisting to deposit then engrave the insulating level 23.
- the present invention applies to all methods of manufacturing semiconductor type components in thin layers, and particularly to transistors, direct or reverse stages, and diodes constituting the devices for controlling pixel electrodes and integrated peripheral control circuits. or not integrated on the same substrate plate, for flat screens using liquid crystals.
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9405240A FR2719416B1 (en) | 1994-04-29 | 1994-04-29 | Process for passivation of the sides of a thin-film semiconductor component. |
FR9405240 | 1994-04-29 | ||
PCT/FR1995/000572 WO1995030241A1 (en) | 1994-04-29 | 1995-05-02 | Method for passivating the sides of a thin film semiconductor component |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0757845A1 true EP0757845A1 (en) | 1997-02-12 |
Family
ID=9462685
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP95919467A Pending EP0757845A1 (en) | 1994-04-29 | 1995-05-02 | Method for passivating the sides of a thin film semiconductor component |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0757845A1 (en) |
JP (1) | JPH09512667A (en) |
KR (1) | KR970703043A (en) |
FR (1) | FR2719416B1 (en) |
WO (1) | WO1995030241A1 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5752446B2 (en) * | 2010-03-15 | 2015-07-22 | 株式会社半導体エネルギー研究所 | Semiconductor device |
JP5752447B2 (en) * | 2010-03-15 | 2015-07-22 | 株式会社半導体エネルギー研究所 | Semiconductor device |
US8916425B2 (en) * | 2010-07-26 | 2014-12-23 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming microcrystalline semiconductor film and method for manufacturing semiconductor device |
US9230826B2 (en) | 2010-08-26 | 2016-01-05 | Semiconductor Energy Laboratory Co., Ltd. | Etching method using mixed gas and method for manufacturing semiconductor device |
US8704230B2 (en) | 2010-08-26 | 2014-04-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US8338240B2 (en) * | 2010-10-01 | 2012-12-25 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing transistor |
JP5687133B2 (en) * | 2010-11-05 | 2015-03-18 | 三菱電機株式会社 | Semiconductor device and display device |
JP6006948B2 (en) * | 2011-03-17 | 2016-10-12 | 株式会社半導体エネルギー研究所 | Microcrystalline semiconductor film and method for manufacturing semiconductor device |
JP2014038911A (en) * | 2012-08-13 | 2014-02-27 | Sony Corp | Thin film transistor and manufacturing method of the same, and display device and electronic apparatus |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4740477A (en) * | 1985-10-04 | 1988-04-26 | General Instrument Corporation | Method for fabricating a rectifying P-N junction having improved breakdown voltage characteristics |
FR2590409B1 (en) * | 1985-11-15 | 1987-12-11 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR WITH A SELF-ALIGNED GRID WITH RESPECT TO THE DRAIN AND THE SOURCE THEREOF AND TRANSISTOR OBTAINED BY THE PROCESS |
JPS62252973A (en) * | 1986-04-25 | 1987-11-04 | Nec Corp | Forward staggered type thin film transistor |
GB2238427A (en) * | 1989-11-24 | 1991-05-29 | Philips Electronic Associated | Thin film diode devices and active matrix addressed display devices incorporating such |
US5130263A (en) * | 1990-04-17 | 1992-07-14 | General Electric Company | Method for photolithographically forming a selfaligned mask using back-side exposure and a non-specular reflecting layer |
JPH04171767A (en) * | 1990-11-02 | 1992-06-18 | Sharp Corp | Thin film transistor and manufacture thereof |
SG63578A1 (en) * | 1990-11-16 | 1999-03-30 | Seiko Epson Corp | Thin film semiconductor device process for fabricating the same and silicon film |
JPH04321236A (en) * | 1991-04-19 | 1992-11-11 | Sony Corp | Manufacture of field-effect transistor |
FR2675947A1 (en) * | 1991-04-23 | 1992-10-30 | France Telecom | PROCESS FOR LOCAL PASSIVATION OF A SUBSTRATE BY A HYDROGEN AMORPHOUS CARBON LAYER AND METHOD FOR MANUFACTURING THIN FILM TRANSISTORS ON THE PASSIVE SUBSTRATE. |
US5252849A (en) * | 1992-03-02 | 1993-10-12 | Motorola, Inc. | Transistor useful for further vertical integration and method of formation |
JP3260165B2 (en) * | 1992-07-30 | 2002-02-25 | 松下電器産業株式会社 | Manufacturing method of thin film element |
FR2702882B1 (en) * | 1993-03-16 | 1995-07-28 | Thomson Lcd | Method for manufacturing direct step thin film transistors. |
-
1994
- 1994-04-29 FR FR9405240A patent/FR2719416B1/en not_active Expired - Fee Related
-
1995
- 1995-05-02 JP JP7528040A patent/JPH09512667A/en active Pending
- 1995-05-02 WO PCT/FR1995/000572 patent/WO1995030241A1/en not_active Application Discontinuation
- 1995-05-02 EP EP95919467A patent/EP0757845A1/en active Pending
-
1996
- 1996-10-28 KR KR1019960706045A patent/KR970703043A/en not_active Application Discontinuation
Non-Patent Citations (1)
Title |
---|
See references of WO9530241A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO1995030241A1 (en) | 1995-11-09 |
KR970703043A (en) | 1997-06-10 |
FR2719416A1 (en) | 1995-11-03 |
FR2719416B1 (en) | 1996-07-05 |
JPH09512667A (en) | 1997-12-16 |
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