WO1995025348A1 - Interconnexions logiques tridimensionnelles entre des puces de circuits integres utilisant un boitier bidimensionnnel pour un module multipuce - Google Patents

Interconnexions logiques tridimensionnelles entre des puces de circuits integres utilisant un boitier bidimensionnnel pour un module multipuce Download PDF

Info

Publication number
WO1995025348A1
WO1995025348A1 PCT/US1995/000796 US9500796W WO9525348A1 WO 1995025348 A1 WO1995025348 A1 WO 1995025348A1 US 9500796 W US9500796 W US 9500796W WO 9525348 A1 WO9525348 A1 WO 9525348A1
Authority
WO
WIPO (PCT)
Prior art keywords
functional capacity
substrate
lower functional
interconnect
arrays
Prior art date
Application number
PCT/US1995/000796
Other languages
English (en)
Inventor
James Sutherland
Timothy L. Garverick
Hem P. Takiar
George F. Reyling, Jr.
Original Assignee
National Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corporation filed Critical National Semiconductor Corporation
Priority to EP95908601A priority Critical patent/EP0698294A1/fr
Publication of WO1995025348A1 publication Critical patent/WO1995025348A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention is generally directed to techniques for interconnecting and packaging multiple integrated circuit chips in order to form more complex devices, and more specifically, to a high capacity logic device having an increased interconnect capacity and effectively a three dimensional interconnect network, which is based on a variation of standard two dimensional multi-chip module packaging methods.
  • interconnect and packaging technology becomes of greater importance to the design of such devices. This is because the interconnect and packaging technology used in a device can have a great affect on its functional capacity and utility.
  • Interconnection techniques are used to electrically connect multiple smaller functional units into more complex devices and to connect individual and multiple groups of smaller units to the package in which they will be contained. Interconnection methods are important because they affect the speed at which devices operate, the surface area required for the device, and the reliability of the device over an extended period of time. Packaging methods are also important because they affect the speed, cost and reliability of the device and provide the device with power and input signals. Due to the desire to increase the capacity of devices while maintaining a high level of reliability and minimizing cost, the interconnect and packaging technology used in manufacturing a particular device is an important consideration in the device's design.
  • MCM Multi-Chip Module
  • IC integrated circuit
  • the individual chips are mounted on a common substrate and connected to the substrate (and to each other by virtue of the interconnect network on or within the substrate) and to package contacts by one of several methods, for example, wire bonding or solder bump technology.
  • Wire bonding involves connecting bonding pads or contacts on an IC chip to a lead frame or to pads or contacts on other chips with fine wires. Interconnections between contacts on different IC chips can also be carried out by soldering connecting wires between them or using metal interconnect lines.
  • individual chips can also be mounted on a common substrate by using solder bump or flip-chip technology.
  • solder bumps are placed on the die and the chip is flipped over, placing the solder bumps in contact with conductive pads on the substrate. The solder is then reflowed, establishing a good electrical contact.
  • the individual chips are again interconnected to each other using an interconnect network embedded on or within the substrate.
  • An example of a MCM technology which is suited for applications requiring a large number of interconnections between the individual chips and which uses such an interconnect network is Area Array technology.
  • connections are made from the interior of one chip to another through interconnect lines embedded on or within a multi-layer MCM substrate.
  • the interconnect layers of the substrate are accessed through arrays of conductive pads which are designed to correspond to the positions of the metal bumps on chips used in flip-chip packaging methods.
  • the metal bumps are soldered to the array pads to electrically connect the chips to each other.
  • the need for additional interconnect capacity beyond that obtainable using wire bonding or metal interconnect lines is especially critical when interconnecting arrays of logic cells or chips composed of multiple logic cell arrays into larger and more complex devices. Since logic cell arrays typically require a large number of connections in order for the smaller arrays to be combined into a higher capacity logic device, as the final array becomes larger, a barrier to further expansion is quickly reached. This is because of the need to avoid the inherent problems with wire bonding or metal interconnect lines mentioned above. The result is that the array is constrained to either being small, but limited in complexity, or complex, but larger and more expensive than may be desired for a given application.
  • a method of forming a large scale integrated circuit by stacking two or more layers of chips onto each other and interconnecting them via wire bonding is described in Japanese Patent Application Disclosure No. 1-28856, corresponding to Application No. 62-182307, entitled “Multilayered Integrated Circuit", filed July 23, 1987 and naming Takeuchi as the inventor. While this disclosure describes a means of combining two or more IC chips to provide a larger circuit, the use of wire bonding to interconnect the chips makes the package liable to the space availability, short circuit and capacitive and inductive coupling problems noted above. Thus, the interconnect capacity of such a device is severely limited.
  • the present invention is directed to a high capacity gate array which incorporates an effectively three dimensional interconnect network.
  • the array is formed from multiple smaller arrays which are connected to a common substrate by means of flip-chip bonding.
  • the substrate is typically a multi-layer substrate which has interconnect lines embedded on or within it, thereby allowing a set of desired interconnections between the smaller logic cell arrays to be implemented.
  • the contact points for connecting logic cells or arrays of cells to the substrate result from placing a multitude of solder bumps on the smaller arrays of logic cells at desired interconnect points. Connecting the interconnect point solder bumps to the multi-layer substrate then permits the individual logic cell arrays to be interconnected in a desired manner.
  • the placement of the solder bumps and pattern of the interconnect layers of the substrate are designed to permit equivalent points on different logic cell arrays to be connected together in parallel.
  • This has the effect of producing a three dimensional interconnect network from a two dimensional arrangement of arrays or chips contained in a MCM package.
  • the result is a high gate capacity logic device having an increased degree of gate utilization (the ratio of logic gates used to gates available) and reduced average interconnect distances, thereby enabling the production of complex devices which have a faster operating speed.
  • Figs. 1A-1C illustrate some of the features of a logic cell array or chip composed of such arrays which is suitable for use in accordance with the present invention.
  • Fig. 2 shows a possible layout of interconnect pads to enable the logic cell arrays of Figs. 1A-1C to be interconnected into more complex devices.
  • Fig. 3 shows a second possible layout of interconnect pads to enable the logic cell arrays of Figs. 1A-1C to be interconnected into more complex devices.
  • Fig. 4 shows how the logic cell arrays of Figs. 1A-1C can be interconnected to a substrate in order to provide interconnections between multiple smaller logic cell arrays.
  • Fig. 5 shows a possible interconnect network for an array formed from multiple smaller programmable gate arrays or chips which are placed on a MCM substrate, where the substrate interconnect lines interconnect an equivalent point on each of the smaller arrays or chips.
  • Fig. 6 shows the three dimensional analog of the two dimensional interconnect network shown in Fig. 5.
  • Figs. 1A-1C which illustrate some of the features of a logic cell array or chip composed of such arrays which is suitable for use in accordance with the present invention.
  • the example shown in Figs. 1A-1C has an "extendible" architecture which means that the architecture is scalable so that multiple smaller functional units may be combined to produce a device having a higher capacity, but improved functionality and a similar architecture as its component units.
  • the concept of extendibility means that the chip architecture is such that individual chips or arrays of logic cells can be combined into more complex devices by interconnecting a location on one chip or array to the equivalent or corresponding location on a different chip or array.
  • FIGs. 1A-1C is a configurable logic array (CLA), in particular, the CLAy family of configurable logic array chips produced by National Semiconductor Corporation of Santa Clara, California.
  • CLA configurable logic array
  • the architecture and operation of the CLAy family of devices is described in allowed U.S. Patent Application No. 08/044,921, which is assigned to the Assignee of the present application and is hereby incorporated by reference.
  • the CLAy family of chips are a subset of the larger set of field- programmable-gate-array (FPGA) chips, some of which are also suitable for use in accordance with the present invention.
  • FPGA field- programmable-gate-array
  • Another type of device having an extendible architecture and which can be used in accordance with the present invention is a mask programmable gate array.
  • combinations of some types of chips can be extendible to the degree desired for the present application, for example FPGA and static random-access memory (SRAM) chip combinations.
  • the architecture of a CLAy configurable logic array chip consists of a two-dimensional matrix 30 formed by tiling multiple smaller arrays 31 of interconnected, programmable logic cells 12.
  • matrix 30 is a 7 x 7 array of smaller arrays 31, where each smaller array 31 is an 8 x 8 array of logic cells 12.
  • I/O Input/output
  • the individual logic function and the active inputs and outputs of each logic cell 12 are determined by parameter memory bits and logic gates within the cell, rather than by physically customizing the array during manufacture.
  • the individual cell functions and the interconnections between cells are field programmable which provides a wide variety of possible functions. The greater the number of cells in the array, the greater the functional capacity of the CLAy device.
  • a CLAy may be viewed as an array of programmable logic cells on which a flexible bussing network is superimposed.
  • Fig. IB is a close-up view of one of the 8 x 8 arrays 31 of logic cells 12 contained in matrix 30.
  • logic cells 12 can be used for routing signals, this can result in unacceptably long delays when done over long distances.
  • the interconnections between neighboring cells 12 are augmented with two types of programmable busses: local and express.
  • connections between individual cells 12 in arrays 30 and 31 are accomplished by buses or by direct connections between adjacent cells.
  • local busses 32 provide connections between the array of cells and the bussing network.
  • Each local bus 32 is connected to every cell 12 in its column or row, thus providing every cell in the array with read/ write access to the local bus system.
  • Express buses 36 provide higher speed transmission of signals and are not connected to every cell.
  • Express busses 36 are designed to speed up signal transfers within arrays 30 and 31, and are the fastest way to cover straight-line distances spanning many cells.
  • Connective units called repeaters 38 are spaced every eight cells 12 and divide each bus into segments spanning eight cells 12. Repeaters 38 are aligned into rows and columns, thereby partitioning array 30 into smaller arrays 31 containing 8x8 blocks of cells 12 called "superblocks". Repeaters 38 serve as programmable switches and can be programmed to provide various connecting functions between similar or different bus types.
  • a repeater 38 may be composed of one or more switching units, where each switching unit is composed of a programmable signal transmission gate and a buffer.
  • a device's RAM programmable memory (which is either set or reset during the configuration mode) puts the bi-directional signal transmission gate into an open or closed state.
  • each logic cell 12 receives inputs from and provides outputs to its four adjacent neighbors.
  • each logic cell 12 in array 31, other than those on the periphery of array 30, receives eight inputs from and provides eight outputs to its North (N), East (E), South (S), and West (W) neighbors.
  • These sixteen inputs and outputs are divided into two types, "A" and "B", with an A input, an A output, a B input and a B output for each neighboring cell 12. Between two different cells 12, an A output is always connected to an A input and a B output is always connected to a B input.
  • interconnections between adjacent cells 12 are provided by direct interconnections or by buses, where both types of interconnections are typically implemented by means of metal interconnect lines.
  • Interconnections between adjacent superblocks 31 are provided by the busing network and by interconnections between adjacent cells on the periphery of adjacent superblocks. .An array of interconnected superblocks 31 forms a CLAy chip or die 30. Multiple dice 30 are interconnected into larger more complex arrays by means of interconnect lines on the periphery of each die. Due to limitations on the surface area available for laying out interconnect lines and concerns regarding cross-talk and coupling, the number of interconnection lines available for interconnecting one die 30 to another such die 30 is limited to approximately 108. This acts to limit the achievable degree of gate utilization and the complexity of the final device which can be constructed for a given amount of active device surface area.
  • the degree of gate utilization is an important characteristic of gate array based devices because the vast majority of such devices are "random logic” systems where a logic cell is connected to both neighboring and to more distant cells. This is in contrast to “systolic array” systems in which interconnections are only between neighboring cells.
  • the CLAy architecture allows a gate utilization of 15 to 20% of the available cells on a die. This is a result of the limited amount of interconnect wiring resources on a die. It is difficult to use a greater percentage of the available cells because when the limited number of close by interconnect buses are used up connecting distant cells, other buses must be used to allow additional interconnections. This means that the logic cells near those busses become unavailable for use as active logic cells.
  • the CLAy array 30 has a maximum of 108 possible input/output (I/O) interconnection contacts on its periphery, and with the present architecture, each superblock 31 is connected to its neighboring four superblocks in array 30 by means of 16 local bus 32 and 16 express bus 36 connections per side, for a total of 128 bus connections for internal superblocks with four neighbors.
  • I/O input/output
  • Superblocks on the periphery of array 30 have either 64 or 96 bus connections, depending upon whether there are 2 or 3 neighboring superblocks.
  • the smaller arrays of logic cells 31 can be adapted as shown in Fig. 2, which shows a possible layout of interconnect pads 40 to enable the logic cell arrays of Figs. 1A-1C to be mounted on a substrate which serves to interconnect the arrays, thereby producing more complex devices.
  • each smaller array or superblock 31 is provided with numerous solder bump interconnection pads 40, where the pads are identified as PI through P8 in the figure.
  • pads 40 are electrically connected through the insulating layer to points on .arrays 31. This allows the pads to be interconnected to arrays 31 without increasing the surface area of the arrays and hence the surface area of the die or chip 30 formed from multiple arrays 31.
  • Interconnect pads 40 are then electrically connected to similar pads on a multi-layer substrate which contains interconnect lines, allowing arrays 31 to be interconnected to other similar arrays in a desired manner.
  • interconnect pads 40 and the interconnect network of the substrate to electrically connect the express bus repeaters on one edge of a superblock to the corresponding repeaters on the edge of another superblock. This is shown in Fig. 2, in which interconnect pads 40 are placed above the repeaters to which they are connected, in this case every fourth repeater on the top and side of a superblock 31. If every superblock has interconnect pads distributed on its top and side (the right side in the example), the overall array 30 will have an evenly distributed pattern of interconnect pads superimposed on all of the superblocks in the array. This is desireable because for a random logic based system, such a distribution of interconnect points will yield the shortest average interconnect path between any two elements.
  • Figure 3 shows a second possible layout of interconnect pads to enable logic cell arrays 31 of Figs. 1A-1C to be mounted on a substrate and interconnected into more complex devices.
  • a total of 16 interconnect pads 40 are electrically connected to points on array 31 to enable multiple arrays 31 to be interconnected into a higher capacity logic device.
  • interconnect pads 40 are again connected to the repeaters 38 which are part of the circuitry of array 31.
  • pads 40 be placed on an insulating layer above array 31 and electrically connected through the insulating layer to the desired connection points on array 31 in order to maximize the surface area available for the active circuitry.
  • interconnect pads 40 are connected to every other repeater 38 on the top and side of a superblock 31.
  • Figure 4 shows in greater detail one method of interconnecting the logic cell arrays 31 of Figs. 1A-1C to a substrate in order to provide interconnections between multiple smaller logic cell arrays.
  • a repeater 38 consists of one or more switching units 50, where each switching unit 50 is composed of a programmable transmission gate 52 and a buffer 54.
  • the switching units 50 permit signals to be routed amongst the different express or local buses connected to a repeater 38.
  • the repeaters 38 on array 31 are augmented with an additional set of switching units 51, thereby permitting signals to be routed between the substrate interconnect point or pad 58 and the repeater 38, where the connection between additional switching units 51 and repeater 38 is accomplished by means of interconnect pads 40 described previously.
  • Additional switching units 51 are typically placed on the smaller arrays 31 or on the insulating layer separating the interconnect pads from the array.
  • interconnect pads 40 as shown in Fig. 3, and a die 30 composed of a 7x7 array of superblocks 31, a pair of die 30 mounted on a substrate would gain a total of 784 (16 x 49) possible interconnects in addition to the 108 presently available. This would allow more cells to be used for active logic functions since fewer would be needed to function as interconnect wires, thereby increasing the degree of gate utilization. In addition, since fewer of the existing buses will be needed for interconnections, cells won't be disabled by the need to use their close by buses for interconnections. It is important to note that this added connectivity is achieved with little, if any, increase in die size. The only increase would be that needed for the placement of the added switching units 51 shown in Fig. 4.
  • the interconnect network embedded on or within the substrate determines how the individual arrays 31 are interconnected and how the resulting device operates in terms of functionality and capacity.
  • Figure 5 shows a possible interconnect network for an array 60 formed from multiple smaller programmable gate arrays or chips 30 which are placed on a MCM substrate, where the substrate interconnect lines interconnect corresponding points
  • FIG. 6 shows the three dimensional analog of the two dimensional interconnect network shown in Fig. 5. As indicated in Fig. 6, the result of the interconnect scheme depicted in Fig.
  • the present invention provides a more even distribution of connecting points over the surface area of the component arrays and die. This arrangement acts to minimize the average interconnect length between elements located on two different die.
  • the substrate interconnect network can also be designed to electrically connect points on the same die. This may be especially useful in the case of devices such as field-programmable-gate-arrays which are designed to allow reconfiguration by the user to suit a specific application, because the inter ⁇ chip and intra-chip interconnect scheme is not known at the time the chip is manufactured. For certain applications it may be desirable to increase the intra- chip interconnect capacity so that the existing interconnect capacity can be used primarily for inter-chip connections.
  • This embodiment of the present invention is particularly suited to applications such as routing clock signals to multiple points on the same chip, where the same signal needs to be distributed to a large number of points with the requirement of minimal signal delay between each of the points.
  • This embodiment of the present invention would again involve the addition of solder bumps or contact pads to arrays 31 and then mounting die 30 composed of such arrays onto a substrate.
  • the substrate would contain an interconnect network which electrically connected points on the same die 30. Interconnections between different dice 30 would be implemented by cell-to-cell connections, bus lines, or other parts of the substrate interconnect network.
  • the added interconnect capacity of this embodiment again supplements that available in the die as originally manufactured, thereby increasing the degree of gate utilization and reducing the propagation delay between points on the same die and on different die.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne une matrice de grilles de grande capacité qui comporte un réseau d'interconnexion réellement tridimensionnel. La matrice est formée d'une pluralité de matrices plus petites qui sont connectées à un substrat commun au moyen d'un soudage de puce à protubérances. Le substrat est généralement un substrat à couches multiples qui a des lignes d'interconnexion logées sur ou dans le substrat, ce qui permet de réaliser une série d'interconnexions requises entre les matrices plus petites de cellules logiques. Les points de contact pour connecter les cellules logiques ou les matrices de cellules logiques au substrat, résultent du positionnement d'une pluralité de perles de soudure sur les matrices de cellules logiques plus petites, aux points d'interconnexion souhaités. La connexion des perles de soudure, au niveau des points d'interconnexion, au substrat à couches multiples permet alors d'interconnecter les matrices individuelles de cellules logiques de la manière souhaitée. On réalise un réseau tridimensionnel d'interconnexions en interconnectant les points correspondants de différentes matrices de cellules logiques, afin que les matrices soient connectées en parallèle. Ceci aboutit à un réseau tridimensionnel d'interconnexions à partir d'un système bidimensionnel de matrices ou de puces dans un boîtier pour un module multipuce. On obtient ainsi un dispositif logique à grilles de grande capacité présentant un taux d'utilisation plus élevé des grilles et des distances d'interconnexion moyennes plus courtes, ce qui permet de produire des dispositifs complexes qui ont une vitesse de fonctionnement plus élevée.
PCT/US1995/000796 1994-03-15 1995-01-20 Interconnexions logiques tridimensionnelles entre des puces de circuits integres utilisant un boitier bidimensionnnel pour un module multipuce WO1995025348A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP95908601A EP0698294A1 (fr) 1994-03-15 1995-01-20 Interconnexions logiques tridimensionnelles entre des puces de circuits integres utilisant un boitier bidimensionnnel pour un module multipuce

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US21314694A 1994-03-15 1994-03-15
US08/213,146 1994-03-15

Publications (1)

Publication Number Publication Date
WO1995025348A1 true WO1995025348A1 (fr) 1995-09-21

Family

ID=22793918

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1995/000796 WO1995025348A1 (fr) 1994-03-15 1995-01-20 Interconnexions logiques tridimensionnelles entre des puces de circuits integres utilisant un boitier bidimensionnnel pour un module multipuce

Country Status (3)

Country Link
EP (1) EP0698294A1 (fr)
KR (1) KR100360074B1 (fr)
WO (1) WO1995025348A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0846289A1 (fr) * 1996-05-20 1998-06-10 Atmel Corporation Circuits prediffuses programmables par l'utilisateur avec memoire ram repartie et utilisation accrue des cellules
WO2001093426A1 (fr) * 2000-05-30 2001-12-06 Koninklijke Philips Electronics N.V. Circuit integre a matrice de cellules logiques programmables
EP1667325A1 (fr) * 1999-07-15 2006-06-07 Altera Corporation Dispositif logique programmable utilisant une structure de cellule unifiée présentant des plots d'interface
EP1705798A2 (fr) * 1999-03-04 2006-09-27 Altera Corporation Ressources d'interconnexion destinées à dispositifs logiques programmables à circuit intégré
US7839167B2 (en) 1999-03-04 2010-11-23 Altera Corporation Interconnection and input/output resources for programmable logic integrated circuit devices

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0475269A2 (fr) * 1990-09-10 1992-03-18 Hitachi, Ltd. Dispositif à circuit intégré comprenant un substrat à conducteurs
EP0592111A2 (fr) * 1992-10-08 1994-04-13 Aptix Corporation Module multichip de dispositif à circuit intégré ayant un maximum de capacité d'entrée et sortie

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02161754A (ja) * 1988-12-14 1990-06-21 Nec Corp ビルディングブロック方式の半導体集積回路
DE69004414T2 (de) * 1989-09-22 1994-02-24 Renishaw Plc Modulares klemmsystem für werkzeugmaschinen.

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0475269A2 (fr) * 1990-09-10 1992-03-18 Hitachi, Ltd. Dispositif à circuit intégré comprenant un substrat à conducteurs
EP0592111A2 (fr) * 1992-10-08 1994-04-13 Aptix Corporation Module multichip de dispositif à circuit intégré ayant un maximum de capacité d'entrée et sortie

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
DOBBELAERE I ET AL: "FIELD PROGRAMMABLE MCM SYSTEMS - DESIGN OF AN INTERCONNECTION FRAME", PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE, BOSTON, MAY 3 - 6, 1992, no. 14, 3 May 1992 (1992-05-03), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 461 - 464 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0846289A1 (fr) * 1996-05-20 1998-06-10 Atmel Corporation Circuits prediffuses programmables par l'utilisateur avec memoire ram repartie et utilisation accrue des cellules
EP0846289A4 (fr) * 1996-05-20 2000-11-22 Atmel Corp Circuits prediffuses programmables par l'utilisateur avec memoire ram repartie et utilisation accrue des cellules
EP1143336A1 (fr) * 1996-05-20 2001-10-10 Atmel Corporation FPGA avec utilisation accruée des cellules
EP1705798A2 (fr) * 1999-03-04 2006-09-27 Altera Corporation Ressources d'interconnexion destinées à dispositifs logiques programmables à circuit intégré
EP1705797A2 (fr) * 1999-03-04 2006-09-27 Altera Corporation Ressources d'interconnexion destinées à dispositifs logiques programmables à circuit intégré
EP1705798A3 (fr) * 1999-03-04 2009-03-11 Altera Corporation Ressources d'interconnexion destinées à dispositifs logiques programmables à circuit intégré
EP1705797A3 (fr) * 1999-03-04 2009-03-11 Altera Corporation Ressources d'interconnexion destinées à dispositifs logiques programmables à circuit intégré
US7839167B2 (en) 1999-03-04 2010-11-23 Altera Corporation Interconnection and input/output resources for programmable logic integrated circuit devices
EP1667325A1 (fr) * 1999-07-15 2006-06-07 Altera Corporation Dispositif logique programmable utilisant une structure de cellule unifiée présentant des plots d'interface
WO2001093426A1 (fr) * 2000-05-30 2001-12-06 Koninklijke Philips Electronics N.V. Circuit integre a matrice de cellules logiques programmables

Also Published As

Publication number Publication date
EP0698294A1 (fr) 1996-02-28
KR100360074B1 (ko) 2003-01-24
KR960702943A (ko) 1996-05-23

Similar Documents

Publication Publication Date Title
US5543640A (en) Logical three dimensional interconnections between integrated circuit chips using a two dimensional multi-chip module
US5512765A (en) Extendable circuit architecture
US4161662A (en) Standardized digital logic chip
US5426566A (en) Multichip integrated circuit packages and systems
US4458297A (en) Universal interconnection substrate
US6166560A (en) Basic cell structure having a plurality of transistors for master slice type semiconductor integrated circuit device
US5132571A (en) Programmable interconnect architecture having interconnects disposed above function modules
US8107311B2 (en) Software programmable multiple function integrated circuit module
US7126375B2 (en) Floor plan for scalable multiple level tab oriented interconnect architecture
EP2019427B1 (fr) Paquets de puces retournées à faible bruit et puces retournées correspondantes
US6999332B2 (en) Semiconductor package with a controlled impedance bus and method of forming same
US6462427B2 (en) Semiconductor chip, set of semiconductor chips and multichip module
US20030178228A1 (en) Method for scalable architectures in stackable three-dimentsional integrated circuits and electronics
JPH077128A (ja) 最大入力／出力能力を有するマルチチップモジュール集積回路装置
US7902879B2 (en) Field programmable gate array utilizing dedicated memory stacks in a vertical layer format
JP2001274288A (ja) 集積回路チップ・キャリア構造体
US5895978A (en) High density signal multiplexing interposer
US20030025132A1 (en) Inputs and outputs for embedded field programmable gate array cores in application specific integrated circuits
KR940001394B1 (ko) 초대규모 반도체 집적 칩상에 전기 회로를 설계하는 방법 및 반도체 박막 다중 칩 모듈
KR100360074B1 (ko) 2차원멀티칩모듈패키지를사용하는집적회로칩간의논리적3차원상호연결
US7026718B1 (en) Stacked multi-component integrated circuit microprocessor
WO2011107612A1 (fr) Interconnexions personnalisables entre des circuits électroniques
US4746815A (en) Electronic EC for minimizing EC pads
EP0069762B1 (fr) Substrate d'interconnection universelle
EP0135019B1 (fr) Interconnexion d'éléments sur un substrat à circuit intégré

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

WWE Wipo information: entry into national phase

Ref document number: 1995908601

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1019950705101

Country of ref document: KR

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWP Wipo information: published in national office

Ref document number: 1995908601

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1995908601

Country of ref document: EP