WO1995022782A1

WO1995022782A1 - Active matrix substrate and color liquid crystal display device

Info

Publication number: WO1995022782A1
Application number: PCT/JP1995/000231
Authority: WO
Inventors: Mutsumi Matsuo
Original assignee: Seiko Epson Corporation
Priority date: 1994-02-17
Filing date: 1995-02-17
Publication date: 1995-08-24
Also published as: KR960702117A; JP3298109B2; KR100350333B1

Abstract

Pixel regions (P11, P12, P13) equipped with pixel electrodes (12) corresponding to red, green and blue colors are periodically arranged in the unit of three colors in an X direction, and the cycle of arrangement is deviated by 1/2 cycle between odd-numbered stages and even-numbered stages in a Y direction so as to constitute a delta arrangement. When only the pixel electrodes (12) of the pixel regions (P12, P22, P32) corresponding to the same color are connected to the same source line (S2), the pixel regions (P12, P22, P32) are alternately arranged on the right and left sides of the source line (S2). In each of the pixel regions (P11, P12, P13, ...) arranged in the X direction, the relative formation positions of TFT (11), the pixel electrode (12) and first and second electrode portions (C1, C2) of a capacitance retaining capacitor (CS) are the same. The relative formation positions of the TFT (11) and the pixel electrode (12) are reversed to the right and left for each stage between the pixel regions (P12, P22, P32, ...) aligned in the Y direction, but the relative positional relation between the first and second electrode portions (C1, C2) of the capacitance retaining capacitor (CS) remains the same.

Description

Documentary matrix substrate and color liquid crystal display [Technical field]

The present invention relates to an element structure of an active matrix substrate used for a liquid crystal display device, and particularly to a structure of a storage capacitor. Also, the present invention relates to a structure of a color liquid crystal display device using the active matrix substrate.

(Background technology)

Figure 1 shows the basic structure of a color liquid crystal display device using an active matrix substrate. In FIG. 1, gate lines GO, Gl, G2 '*' extending in the X direction and source lines S1, S2, S3 extending in the Y direction are provided on the surface of the substrate 10. , And a plurality of pixels arranged at positions corresponding to intersections of these source lines Sl, S2, S3, and the gate lines Gl, G2, ΰ3, An electrode 12 and a thin film transistor (hereinafter, referred to as “TFT”) 11 connected to each pixel electrode are formed.

During the selection period, that is, the period when the TFT 11 is turned on by the signal from the gate lines Gl, G2, and G3-'', the counter substrate 20 is turned on. The source lines S 1, S 2, and S 3 are connected to a liquid crystal capacitor CLC composed of the common electrode 26, the pixel electrode 12, and the liquid crystal 30 sealed in the gap between them. · Image signals supplied from and are written. On the other hand, during the non-selection period, that is, during the period when TFT 11 is in the off state, the image signal written to the liquid crystal capacitor CLC during the selection period is held.

Here, in order to perform high-quality display, it is necessary to keep the display characteristics during the non-selection period. Good performance is required. To achieve this, it is effective to provide a storage capacitor capacitor CS electrically in parallel with the liquid crystal capacitor CLC.

Regarding the storage capacitor CS, a configuration in which the storage capacitor CS is provided between the previous gate line and the pixel electrodes 12 and 1 ', or a separately formed storage capacitor line (Fig. 1 A configuration in which a storage capacitor CS is provided between the pixel electrode 12 and the pixel electrode 12 has been proposed.

The storage capacitor C S configured in this manner, the pixel electrodes 12,

Pixel area PI1, PI2, P with TFT11, other accompanying wiring, etc.

1 3 · · · are configured. Here, a pixel region is not formed between the pixel region P11 and the pixel region P31, but a pixel region for blue is formed in that region. In some cases, dummy pixel areas are formed.

On the opposite substrate 20, a color filter 21 is formed. The color filter 21 generally includes a red filter R, a green filter G, and a blue filter B. These red filter R, green filter G, and blue filter B are repeatedly arranged in the display screen as one unit. The array of color filters 21 includes a stripe array, a mosaic array, or a delta array. Here, FIG. 12 shows a color array pattern of a delta array, and FIG. 13 shows an example of a color array pattern of a mosaic array. Such a delta array or a mosaic array has the advantage that a smoother image can be displayed as compared to a stripe array because each color element is evenly distributed in the display screen. You.

A liquid crystal display device using the delta arrangement is disclosed in

A liquid crystal display device using a mosaic arrangement is disclosed in, for example, FIG. 3A, FIG. 3A, and FIG. 8C, FIG. and so on. Among the liquid crystal display devices described in this publication, those using the delta arrangement are shown in FIG. 14, as shown in red filter R, green filter G, and blue filter. Three pixel regions P 21, P 22, and P 23 corresponding to B are periodically arranged in the X direction with each of them as one unit. However, the pixel regions P 21, P 22, and P 23 in the even-numbered pixel rows are the pixel areas P ll, P 12, P 13, and the pixels in the odd-numbered pixel rows. The regions P31, P32, and P33 are arranged apart from each other by a distance corresponding to a half cycle of the unit. Therefore, between the odd-numbered pixel row and the even-numbered pixel row, the pixel regions P ll, P 12,? 13 The center position of '*' is shifted alternately left and right by a distance equivalent to 1.5 pixel pitch.

Since all pixel regions have the same basic configuration, the pixel region P 21 will be described as an example. In the pixel region P 21, the source region 111 of the TFT 11 is connected to the source line S 1, the gate electrode 113 is connected to the gate line G 2, and the drain region 1 1 2 is connected to the pixel electrode 1 2. Further, the pixel region P 21 has a first electrode portion C 1 electrically connected to the drain region 112 of the TFT 11 and the pixel electrode 12, and a gate in the preceding stage. A second electrode portion C 2 having a structure extending from the line G 1 in the Y direction is formed. As a material for the first electrode portion C 1, usually, a doped silicon film is used. The first electrode portion C 1 and the second electrode portion C 2 are arranged to face each other via a dielectric film, as described later. In this way, the storage capacitor CS is formed between the pixel electrode 12 and the preceding gate line G1.

Each of the source lines S1, S2, S3, ... extends in a Y-direction while bending in the form of a crank, and a plurality of color signals are supplied to the same source. Since a complicated color switching circuit for supplying a line with appropriate timing is not required, the pixel electrode of the pixel region corresponding to the same color for the same source line is not required. Done ^ 弒 OSi ^ D Only is connected via TFT11. Accordingly, in the same source line, pixel regions corresponding to the same color are alternately arranged on both sides of the source line for each stage. For example, in the case of the source line S 2, the pixel regions P 12, P 22, and P 32 • ′ corresponding to the green color are alternately arranged on both sides of the source line S 2. Inevitably, the positional relationship between the TFT 11 and the source line is reversed for each stage.

As a result, between each pixel area PI1, P12, P13, ... arranged in the X direction along the gate lines Gl, G2G3, ..., TFT11, pixel electrode 12 and the storage capacitor CS (the first electrode portion C 1 and the second electrode portion C 2) have the same relative formation position, while the pixels arranged in the Y direction along the source line S 2. Between the regions P12 and P22 232, the relative formation positions of the TFT 11, the pixel electrode 12 and the storage capacitor CS are bilaterally symmetrical for each stage. ing. For example, pixel regions P ll, PI 2, Ρ1 3 · 'connected to the gate line G 1 and pixel regions 領域 2 1, Ρ 2 2, 2 2 3 接続 connected to the gate line G 2 · The relative positional relationship between TF Τ 11, pixel electrode 12, and storage capacitor CS is symmetrical between the left and right.

A method of manufacturing an active matrix substrate having such a configuration will be briefly described with reference to FIGS. FIGS. 15 (A), (B) and (C) are sectional views taken along lines I-I ', II-II' and III-III 'of FIG. 14, respectively. ), First, after forming a polycrystalline silicon thin film on the substrate 10, the TFT 11 is formed by patterning by photolithography technology. A polycrystalline silicon thin film 110 constituting the active region and the first electrode portion C1 of the storage capacitor CS is formed.

Next, a gate oxide film 114 and a dielectric film C 3 of the storage capacitor CS are formed by thermal oxidation of the polycrystalline silicon film 110. Then hold The impurity is selectively doped only into the polycrystalline silicon film 110 for forming the capacitance capacitor CS, and the first electrode portion C 1 of the storage capacitance capacitor CS is formed. To form

Subsequently, the gate electrode 113 and the second electrode part C 2 of the storage capacitor CS are connected to each other by a photolithography technique to form a polycrystalline doped silicon film. It is formed by In this state, in the pixel region P 21, the gate electrode 113 is electrically connected to the gate line G 2, and the second electrode portion C 2 is connected to the gate line G 1 in the preceding stage. Are electrically connected.

Next, a source region 111 and a drain region 112 are formed by implanting ions with the gate electrode 113 serving as a mask. Next, after an interlayer insulating film 115 is formed, a through hole is formed therein.

Thereafter, the source terminal 111 and the drain terminal 119 are electrically connected to the source region 111 and the drain region 112, respectively. Here, the source terminal 118 is electrically connected to the source line S 1, and the drain terminal 119 is electrically connected to the pixel electrode 12.

In this way, the TFT 11 and the storage capacitor CS are formed in the pixel area P 21, and the pixel area is changed as shown in FIGS. 15 (B) and (C). The storage capacitor CS is also formed in the regions Pll, PI2, and P22.

However, when the pattern shown in FIG. 14 is used, it is necessary to form each component on the substrate 10 by photolithography technology. When an alignment shift occurs in the left-right direction (X direction), for example, each pixel region P 12, P 22, P 3 2... Arranged in the Y direction along the source line S 2. · In, the structural parameters are different for each stage.

That is, in FIG. 16, the lower polycrystalline silicon film forming pattern A1 for forming the TFT 11 and the first electrode portion C1 of the storage capacitor CS is connected to the gate A1. G line Gl, G2, G3--, Gate electrode 1 1 3 And an upper polycrystalline silicon film forming pattern A2 for forming the second electrode portion C2 of the storage capacitor capacitor CS, and an overlapping portion of the storage capacitor capacitor CS. When a diagonal line is given as the opposing portion C 0 of the polycrystalline silicon film on the lower side, a pattern A1 for forming the polycrystalline silicon film on the lower side and a pattern on the upper side of the polycrystalline silicon film are formed. When the alignment is shifted left and right with respect to A 2, the odd-numbered pixel areas P ll, P 1 2... P 3 selected by the gate lines G l and G 3- 1, P3 2 ··· 'storage capacitor CS (ODD) (these storage capacitors are connected to the gate lines GO, G2-···) and the gate line G 2, (G 4) ', the storage capacitor capacitors CS (EVEN) of the pixel areas P 21, P 22, ... (these storage capacitor capacitors are G G l, G 3 -. · · In that is connected) between at, it changes the area of the opposed portion C 0 that hatched.

Figure 16 shows an ideal case where there is no deviation in the horizontal direction.Therefore, the capacitance value of the storage capacitor CS (ODD) and the capacitance of the storage capacitor CS (EVE ) Are equal.

However, if there is a misalignment in the horizontal direction, the capacitance value of the storage capacitor CS (ODD) and the capacitance value of the storage capacitor CS (EVEN) Have different values. For example, the formation pattern A 1 of the lower polycrystalline silicon thin film is shifted in the direction of arrow R with respect to the formation pattern A 2 of the upper polycrystalline silicon thin film. Then, the capacitance value of the storage capacitor CS (ODD) increases, whereas the capacitance value of the storage capacitor CS (EVEN) decreases.

As a result, when an N-type TFT is used, the optimal LC common voltage of the odd-numbered gate lines Gl, G3 'Is higher than the optimum LC common voltage, and a difference occurs in the optimum LC common voltage, which causes a problem that a frit force is generated for each gate line. In order to solve such a problem, an object of the present invention is to improve the formation pattern of each electrode part constituting a storage capacitor, thereby improving the same source line. However, even if the pixel electrodes in each pixel area are connected alternately from the left and right sides of each stage, the active matrix substrate without flickers It is to provide.

Another object of the present invention is to provide a high quality color liquid crystal display device using the active matrix substrate configured as described above.

[Disclosure of the Invention]

In order to solve such a problem, according to a first embodiment of the present invention, first, a plurality of gate lines extending in the X direction are provided on an active matrix substrate. A plurality of source lines extending in the Y direction perpendicular to the direction, a plurality of pixel electrodes arranged corresponding to intersections of the gate lines and the source lines, and an electrical connection to the gate lines. A gate electrode electrically connected to the pixel electrode, a source region electrically connected to the source line, and a drain region electrically connected to the pixel electrode. A plurality of thin-film transistors arranged, a first electrode portion electrically connected to the pixel electrode and a second electrode portion electrically connected to a gate line in the preceding stage. And a plurality of storage capacitor capacitors arranged corresponding to the pixel electrodes.

Then, of a plurality of pixel electrodes electrically connected to the same source line via the thin-film transistor, pixel electrodes adjacent to each other in the Y direction have the same source line. And between the storage capacitor capacitors electrically connected to the adjacent gate lines, with respect to the second electrode portion. It is characterized in that the relative formation positions of the first electrode portions are the same. According to the second embodiment of the present invention, first, a plurality of gate lines extending in the X direction and a plurality of storage capacitance lines extending in the X direction are provided on the active matrix substrate. A plurality of source lines extending in the Y direction orthogonal to the X direction; a plurality of pixel electrodes arranged corresponding to intersections of the gate lines and the source lines; A gate electrode electrically connected to the pixel electrode, a source region electrically connected to the source line, and a drain region electrically connected to the pixel electrode. A plurality of thin-film transistors arranged; a first electrode portion electrically connected to the pixel electrode; and a second electrode portion electrically connected to the storage capacitor line. And a storage capacitor provided corresponding to the pixel electrode.

Then, among a plurality of pixel electrodes electrically connected to the same source line via the thin film transistor, pixel electrodes adjacent to each other in the Y direction have the same shape. It is arranged so as to be located on the opposite side with the source line interposed therebetween, and between the storage capacitor capacitors electrically connected to the adjacent storage capacitor lines, with respect to the second electrode portion. Wherein the relative formation positions of the first electrode portions are the same.

In the active matrix substrate configured as described above, between the storage capacitor capacitors adjacent in the Y direction, the relative position of the first electrode portion with respect to the second electrode portion is set. When the components are formed using the photolithography technology, even if alignment deviations occur, they are retained because the same formation positions are the same. There is no difference in the opposing areas of the first electrode portion and the second electrode portion between the capacitor capacitors, and the capacitance values of the storage capacitor capacitors can be made uniform. .

Therefore, by using the active matrix substrate having such a configuration in the liquid crystal display device, the storage capacitance value differs between the adjacent storage capacitance capacitors. This prevents the occurrence of flicker on a gate line basis. I can do it.

In the present invention, when a color liquid crystal display device having a delta array is formed using the active matrix substrate, first, the liquid crystal display device is formed corresponding to a pixel electrode. A first color filter row in which three color filters of red, green, and blue are periodically arranged in the X direction using the three colors as one unit; and A second color filter row adjacent to the color filter row in the Y direction and periodically arranged in the X direction using the above three colors as one unit is provided. Then, the first color filter row and the second color filter row are alternately displaced in the X direction by a distance corresponding to 1Z2 cycle of the unit cycle. At the same time, for the same source line, only the pixel electrodes corresponding to the same color filter are connected.

Further, in the present invention, when a color liquid crystal display device having a mosaic arrangement is constructed by using the active matrix substrate, unlike the case of the delta arrangement, The first color filter row and the second color filter row are alternately displaced in the X direction by a distance corresponding to 1Z3 period of the unit period. Then, for the same source line, only the pixel electrode corresponding to the color filter of the same color is connected.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a color liquid crystal display device using an active matrix substrate.

FIG. 2 is a plan view showing a pattern of forming each component of the active matrix substrate used in the liquid crystal display device according to the first embodiment.

FIG. 3 is a schematic diagram of the formation pattern shown in FIG.

FIG. 4 (A) is a cross-sectional view taken along line IV—IV ′ in FIG. 2, FIG. 4 (B) is a cross-sectional view taken along line V—V ′ in FIG. 2, and FIG. 4 (C) is a drawing. VI of 2—VI 'line FIG.

Fig. 5 schematically shows the pattern of formation of each silicon film forming two electrodes of the storage capacitor on the surface of the active matrix substrate shown in Fig. 2. FIG.

FIG. 6 is a plan view showing the formation pattern of each component of the active matrix substrate used in the liquid crystal display device according to the second embodiment.

Fig. 7 schematically shows the formation pattern of each silicon film that forms two electrodes of the storage capacitor on the surface of the active matrix substrate shown in Fig. 6. FIG.

FIG. 8 is a cross-sectional view of an inverted staggered TFT used as the TFT of the active matrix substrate used in the liquid crystal display device according to the third embodiment. FIG. 9 is a plan view showing the formation pattern of each component of the active matrix substrate used in the liquid crystal display device according to the third embodiment.

Figure 10 shows the pattern of the tantalum film and the IT0 film that form the two electrodes of the storage capacitor on the surface of the active matrix substrate shown in Figure 9. FIG.

FIG. 11 is a plan view showing the formation pattern of each component of the active matrix substrate used in the liquid crystal display device according to the fourth embodiment.

FIG. 12 is a diagram showing a color array pattern of a delta array.

FIG. 13 is a diagram illustrating an example of a color arrangement pattern of a mosaic arrangement. FIG. 14 is a plan view showing a pattern of forming each component of an active matrix substrate used in a conventional liquid crystal display device.

FIG. 15 (A) is a cross-sectional view taken along the line I-I 'of FIG. 14, FIG. 15 (B) is a cross-sectional view taken along the line II-II' of FIG. 14, and FIG. ) Is a cross-sectional view taken along the line III-III 'in FIG.

Fig. 16 shows the active matrix substrate shown in Fig. 14 FIG. 6 is a plan view schematically showing a pattern of forming each silicon film forming two electrode portions of the storage capacitor on the surface.

[Best mode for carrying out the invention]

First embodiment

FIG. 1 is a diagram showing a basic configuration of a color liquid crystal display device using an active matrix substrate. FIG. 2 is a plan view showing a pattern of forming each component of the active matrix substrate used in the liquid crystal display device of the present embodiment. The active matrix substrate of this embodiment is different from the conventional active matrix substrate only in the pattern of forming each component in the pixel region. Since the components are the same, the components having the common functions are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, in the color liquid crystal display device of the present embodiment, the gate lines G0, G extending in the X direction are formed on the surface of a transparent substrate 10 constituting an active matrix substrate. Pixel areas Ρ11, Ρ12, Ρ13, corresponding to the intersections of l, G2-and the solid lines SI, S2, S3 Are formed. Then, in each pixel area Ρ11, Ρ12, 313,..., The source lines S1, S2, S3,. Pixel electrodes 12 are connected. During a period in which the TFT 11 is turned on (selection period) by signals from the gate lines G1, G2, G3,. The image signals supplied from the source lines S1, S2, S3 are written. On the other hand, while TFT 11 is off (non-selection period), the image signal written to the liquid crystal capacitance portion CLC during the selection period is held.

Here, in order to perform high-quality display, good retention characteristics in the non-selection period are required. Then, the gate lines GO, Gl, G2 A storage capacitor CS is formed between the gate line in the preceding stage and the pixel electrode 12. Of the gate lines GO, Gl, G2, ', the gate electrode of the TFT 11 is not connected to the gate line G0, so that the gate line GO is substantially Dedicated capacity line.

Polarizing plates 41 and 42 are arranged outside the substrate 10 and the counter substrate 20.

The opposite substrate 20 has a color filter 21 formed thereon. The color filter 21 generally includes a red filter R, a green filter G, and a blue filter B. The pixel electrodes 12 of each of the pixel regions Pll, P12, P13,... Are arranged corresponding to these three color filters 21, respectively. The arrangement of the color filters 21 in this embodiment is a delta arrangement (FIG. 12). That is, in the counter substrate 20, three color filters of red (R), green (G), and blue (B) are periodically formed in the X direction with these three colors as one unit. The first color filter row F 1 (odd-numbered color filter row) arranged in a row is adjacent to this color filter row in the Y direction. As a unit, a second color filter row F 2 (even-numbered color filter row) which is periodically arranged in the X direction is formed, and the first color filter row is formed. The filter row F1 and the second color filter row: F2 are alternately displaced in the X direction by a distance corresponding to a half cycle of the one unit cycle. The delta array configured in this way is particularly suitable for video display where smooth image quality is required because each color element is uniformly distributed in the screen.

In response to the arrangement of the color filters configured in this manner, the active matrix substrate has a red filter R and a green filter as shown in FIGS. 2 and 3. The first pixel in which three pixel areas PI1, PI2, and P13 corresponding to the filter G and the blue filter B are periodically arranged in the X direction using them as one unit. Columns (odd-numbered pixel columns) are formed. In the second pixel row (even-numbered pixel row) adjacent to the first pixel row in the Y direction, pixel regions P 21, P 22, and P 2 corresponding to the same one unit 3 is arranged so as to be shifted in the X direction by a distance corresponding to one period and two periods with respect to the first pixel row. In a pixel row adjacent to the second pixel row in the Y direction (an odd-numbered pixel row), pixel areas P31, P32, and P33 corresponding to the same one unit are pixel areas. They are arranged in the opposite direction to P21, P22, and P23 so as to be shifted by a distance equivalent to 12 periods. For this reason, the pixel row including the pixel areas P31, P32, and P33 is in a state in which the pixel row including the pixel areas Pll, P12, and P13 is translated in the Y direction as it is. It is in. Therefore, the center positions of the pixel regions Pll, PI2, Ρ13,... Are shifted by 1.5 pixel pitches in the Y direction alternately left and right at every step.

Each of the source lines S1, S2, S3,... Extends in the Y direction while bending in a crank shape. Then, only pixels corresponding to the same color are connected to the same source line. Therefore, only the signal for displaying one of red, green, and blue colors needs to be supplied from the same source line. In this embodiment, a source line extending in the Y direction while being bent in a crank shape is used. Instead, a zonal line extending in the Y direction while meandering in a curved shape is used instead. You can also use a line.

Since the basic configuration is the same in all pixel regions, the pixel region P 21 will be described as an example. As can be seen from FIG. 2, the gate electrode 113 of the TFT 11 is connected to the gate line G2, the source region 111 is connected to the source line S1, and The region 112 is connected to the pixel electrode 12. In the pixel region P 21, a first electrode portion C 1 electrically connected to the drain region 112 and the pixel electrode 12 is formed, and the first electrode portion C 1 is It is formed of a doped silicon film. In addition, it extends in the Y direction from the previous gate line G1. The second electrode part CI is formed.

The first electrode portion C 1 and the second electrode portion C 2 face each other with a dielectric film interposed therebetween, and a storage capacitor C is provided between the preceding gate line G 2 and the pixel electrode 12. The capacitor CS has been formed.

In the active matrix substrate configured in this manner, the pixel regions P ll and P 1 2 are arranged with respect to the crank-shaped source lines S l, S 2, S 3 ··· '. , P 13... ′, Only the pixel electrode 12 of the pixel region corresponding to the same color of each of the color filters 21 arranged in the delta arrangement is connected. Therefore, in the same source line S 2, the pixel electrodes 12 of the pixel areas P 12, P 22, P 32 2 ′ corresponding to the green color (G) are opposite to each other in the Y direction. They are connected alternately from the side. Other source line S l, a similar der Ru _t here in S 3 · · ·, each of the pixel regions P 1 1 arranged in the X direction along the gate lines G 1, P 1 2, P 1 3 · The relative formation positions of the TFT 11, the pixel electrode 12 and the storage capacitor CS (the first electrode portion C 1 and the second electrode portion C 2) are the same between 'and'. Also, between the pixel regions Ρ 21, Ρ 22, Ρ 23 ··· arranged in the X direction along the gate line G 2, the TFT 11, the pixel electrode 12, and the storage capacitor The relative formation positions of the sensors CS (the first electrode portion C1 and the second electrode portion C2) are the same.

On the other hand, the relative positions of the TFT 11 and the pixel electrode 12 are located between the pixel regions P 12, P 22, · 32 ··· arranged in the Y direction along the source line S 2. Is a pattern that is reversed left and right for each stage. That is, the odd-numbered pixel regions P ll, P 12, P 13 ··· connected to the gate line G 1, and the even-numbered pixel regions P 2 1 connected to the gate line G 2 , P22, P23,... ′, The pattern of forming the TFT 11 and the pixel electrode 12 is symmetrical.

However, the storage capacitance capacitor CS has a finer β paper in any pixel area (£ 1301). They are always formed at the same relative position. In other words, the relative positions of the storage capacitor capacitors CS in the pixel area are the same between the storage capacitor capacitors adjacent in the Y direction.

Also, between the first electrode portion C 1 of the storage capacitor CS and the second electrode portion C 2 extending from the previous gate lines G 0, G l, G 2 ***. The relative positional relationship is the same in each of the X direction and the Y direction between the pixel regions P 12, P 22, P 32,.

For example, in the pixel region P 12 connected to the gate line G 1, a storage capacitor C S is formed in a region where the source line S 1 in the preceding stage passes. Similarly, also in the pixel region P32 connected to the gate line G3, the storage capacitor Cs is formed in a region where the source line S1 in the preceding stage passes. Therefore, in any of the pixel areas PI1, 212, Ρ31, 132, Ρ 'connected to the gate lines Gl, G3, the first electrode of the storage capacitor CS is connected. The portion CI extends from the connection position of the TFT 11 with the drain region 112 to the left region of the pixel electrode 12, and in the left region, the gate line G of the preceding stage is formed. 0, overlaps with the second electrode portion C 2 extending from G 2.

On the other hand, in the pixel region P 22 connected to the gate line G 2, a storage capacitor CS is formed in a region where the source line S 2 connected to the pixel region P 22 itself passes. ing. Therefore, in any of the pixel regions P 21, P 22 ··· 'connected to the gate line G 2, the first electrode portion C 1 of the storage capacitor CS is connected to the drain of the TFT 11. From the connection position with the region 1 1 2, it is turned back toward the source region 1 1 1, and from the vicinity of the source region 1 1 1 1, the odd-numbered pixel regions P ll and P 1 2 Like Ρ 31, Ρ 32 ··· ′, it extends to the left region of the pixel electrode 12. Then, in this left area, it overlaps with the second electrode portion C2 extending from the gate line G1 in the previous stage (FIG. 3). A method of manufacturing the active matrix substrate having such a configuration will be described with reference to FIG. 4 (A), (B), and (C) are a IV-IV cross-sectional view, a V-V 'cross-sectional view, and a VI-VI' cross-sectional view of FIG. 2, respectively.

In FIG. 4 (A), first, the active area of the TFT 11 and the first capacitor CS are formed on the substrate 10 made of quartz glass by the photolithography technology. A polycrystalline silicon thin film 110 for forming the first electrode portion C 1 is formed.

Next, the gate oxide film 114 and the insulating film C3 of the storage capacitor CsS are formed by thermal oxidation of the polycrystalline silicon film 110. Next, only by selectively doping impurities into the polycrystalline silicon film 110 for forming the storage capacitor CS, the storage capacity is maintained. The first electrode section C 1 of the capacitor CS is formed.

Subsequently, the gate electrode 113 and the second electrode portion C 2 of the storage capacitor CS are connected to each other by a photolithographic technique using a polycrystalline silicon thin film. Formed. In this state, in the pixel area P 21, the gate electrode 113 is electrically connected to the gate line G 2, and the second electrode part C 2 is electrically connected to the preceding gate line G 1. It is in the state of being connected to.

Next, ion is implanted using the gate electrode 113 as a mask to form a source region 111 and a drain region 112. Next, after an interlayer insulating film 115 is formed, a through hole is formed therein.

Thereafter, the source terminal 118 and the drain terminal 119 are electrically connected to the source region 111 and the drain region 112, respectively. Here, the source terminal 118 is electrically connected to the source line S 1, and the drain terminal 119 is electrically connected to the pixel electrode 12.

In this way, the TFT 11 and the storage capacitor CS are formed in the pixel area P 21, and the pixel area is formed as shown in FIGS. 4 (B) and 4 (C). The storage capacitor CS is also formed in the regions Pll, PI2, and P22. In such a manufacturing method, when each component is formed on the substrate 10 by the photolithography technique, the pattern is formed in a horizontal direction (X direction). In this embodiment, even if the mask alignment shifts, the structural parameters in the pixel regions Pll, PI2, Ρ13,. There is no end to it. That is, in FIG. 5, a pattern A3 for forming a lower polycrystalline silicon film for forming the first electrode portion C1 of the TFT 11 and the storage capacitor CS, and a gate , G 2, G 3,... Of the upper polycrystalline silicon film for forming the gate electrode 113 and the second electrode portion C 2 of the storage capacitor CS. When the overlapping portion with the formation pattern A 4 is indicated by hatching as the opposing portion C 0 of the storage capacitor CS, the formation pattern of the polycrystalline silicon film A 3 Even if the alignment is shifted in the X direction between the pattern A4 and the polycrystalline silicon film formation pattern, the pixel region connected to the gate lines Gl and G3 ''' P ll, P 1 2--P 3 1, P 3 2 ... (Odd-numbered pixel area) storage capacitor capacitor CS (ODD) (These storage capacitor capacitors are gated. Line GO, G 2, G3-· ') and pixel areas P21, P22 · · · (even-numbered pixel areas) connected to gate line G2 ·' Of the storage capacitor CS (EVEN) (these storage capacitors are connected to the gate lines Gl, G3, G5-···). The area of partial CO does not change.

For example, even if the formation pattern A3 of the polycrystalline silicon thin film is slightly displaced in the direction of arrow R with respect to the formation pattern A4 of the polycrystalline silicon thin film, , 奇 11, Ρ12, Ρ31, Ρ32, '' and the even-numbered pixel area Ρ21, Ρ22, '' The first electrode section C 1 and the second electrode section C 2 of the capacitance capacitor CS The only difference is that the area of the opposing portion C 0 becomes smaller. Conversely, the pattern A 3 for forming the polycrystalline silicon thin film is formed in a state slightly shifted in the direction of arrow L with respect to the pattern A 4 for forming the polycrystalline silicon thin film. In the odd-numbered pixel areas P ll, P 12, Ρ 1, Ρ 2 2 及び and the even-numbered pixel areas Ρ 21, Ρ 22 · Only the area of the facing portion C 0 between the first electrode portion C 1 and the second electrode portion C 2 in the storage capacitor CS is increased.

Also, even if the alignment is slightly shifted in the vertical direction (（direction), the pair of the first electrode section C1 and the second electrode section C2 in each holding capacitance capacitor CS is not affected. The area of the direction CO does not change.

As described above, in the active matrix substrate of this embodiment, the pattern A3 for forming the polycrystalline silicon film and the pattern for forming the polycrystalline silicon film were used. Even if the alignment with A4 is shifted in the horizontal direction (X direction) or the vertical direction (Y direction), each pixel area Pll, P12, ..., Ρ21, Ρ22, Since the capacitance value of each storage capacitor CS is always the same between Ρ 31 and Ρ 32 2 ·, the optimal LC capacitor of the odd-numbered gate lines G l and G 3- The mon- um voltage is always the same as the optimal LC common voltage of the even-numbered gate lines G2, ···. Therefore, it is possible to set the overall optimum LC common voltage, and it is possible to prevent flickering on a gate line basis.

Further, in the present embodiment, the TFT 11 and the pixel region Ρ 11, Ρ 12, Ρ 13 ··· arranged in the Y direction along the source lines S 1, S 2, S 3 By simply inverting the relative formation position of the pixel electrode 12 step by step, the formation position and shape of the first electrode portion C 1 for forming the storage capacitor CS are changed. Only different. Therefore, when the first electrode section C 1 and the second electrode section C 2 are formed only by optimizing the relative positional relationship between the first electrode section C 1 and the second electrode section C 2. Due to misalignment Prevents frizzing force. Therefore, the present invention can be applied to the case where the formation area and size of each component are limited, which is particularly advantageous when realizing a high-definition and high-density liquid crystal display device.

The pixel areas P 11, P 12, corresponding to the odd-numbered gate lines G l, G 3, and the even-numbered gate lines G 2, G 2,. Between the pixel regions P 21, P 22,..., The patterns of the components other than the first electrode portion C 1 are substantially the same. Therefore, the deviation of the alignment between the counter substrate 20 and the active matrix substrate, or the deviation of the alignment on the active matrix substrate , The pixel areas P ll, P 1 2, 'corresponding to the odd-numbered gate lines G 1, G 3-, and the even-numbered gate lines G 2' The difference in aperture ratio between the pixel regions Ρ21 and Ρ22 · · corresponding to 'is also reduced, and horizontal line unevenness due to the difference can be prevented. Second embodiment

FIG. 6 is a plan view showing the pattern of forming each component of the active matrix substrate of the liquid crystal display device of the present embodiment. The active matrix substrate of the present embodiment is different from the active matrix substrate of the first embodiment only in the portion of the storage capacitor. Since the other parts are the same, the components having the corresponding functions are denoted by the same reference numerals.

In the first embodiment, the gate electrode in the preceding stage is used to form the second electrode portion C 2 of each storage capacitor CS. However, in the present embodiment, the constant potential Are formed in parallel with the gate lines Gl, G2, G3 in the X direction, and the storage capacitor capacitors CM1, CM2, CM3 CS constitutes the second electrode section C 2 using the storage capacitance lines CM 1, CM 2, CM 3,. In the liquid crystal display device of this embodiment, similarly to the first embodiment, each of the three pixel regions P 21, P 22, and P 23 corresponding to red, green, and blue has one pixel. The units are arranged periodically in the X direction. Similarly, in the pixel rows adjacent in the Y direction, the pixel areas P 11, P 12,? 13, and the pixel areas U 31, P 32, P 33 corresponding to one unit are also the same. Are alternately arranged one after the other on the left and right.

Here, each of the source lines S1, S2, S3,..., 'Is formed in a crank shape. Also, for the same source line, only the pixel electrode in the pixel area corresponding to the same color is connected. Therefore, the configuration is such that only a signal for displaying any one of red, green, and blue colors needs to be supplied from the same source line.

In addition, since the basic configuration is the same for all the pixel regions, the pixel region P 21 is described as an example, and the pixel region P 21 has the drain region 1 12 and the pixel region P 21. A first electrode portion C 1 made of a doped silicon film electrically connected to the pixel electrode 12 and the pixel electrode 12 is formed, and a first electrode portion C 1 extending in the Y direction is formed from the storage capacitor line CM 2. The second electrode portion C 2 is formed. The first electrode portion C 1 and the second electrode portion C 2 are opposed via a dielectric film. In the pixel region P 21, the pixel electrode 12 and the storage capacitor line CM 2 The storage capacitor CS is configured between and.

In the active matrix substrate configured in this manner, the same color of each color filter 21 in a delta arrangement is applied to the crank-shaped source line. The pixel regions P ll and PI 2 corresponding to the pixel regions P 1 and P 2 are connected to the same source line S 2. 22 and P32 pixel electrodes 12 are connected from opposite sides. The same applies to other source lines S l and S 3.

Therefore, as in the first embodiment, each pixel area P 11, P 1 The relative shapes of the TFT 11, the pixel electrode 12, and the storage capacitor CS (the first electrode portion C 1 and the second electrode portion C 2) are between 2, 13 While the formation positions are the same, in the Y direction, the relative formation positions of the TFT 11 and the pixel electrode 12 in the pixel regions P 12, P 22, P 32,. It is flipped left and right every time.

However, the storage capacitor Cs is formed at the same relative position in any pixel region. In other words, the relative position of the storage capacitor C S in the pixel region is the same between storage capacitors adjacent in the Y direction.

Further, the relative position between the first electrode portion C1 of the storage capacitor capacitor CS and the second electrode portion C2 extending from the storage capacitor lines CM1, CM2,. The positional relationship is the same between the storage capacitor capacitors adjacent in the Y direction. That is, it is the same between each pixel region.

The manufacturing method of the active matrix substrate having such a configuration is almost the same as that of the first embodiment, and the gate electrodes 113, the gate lines Gl, G 2, G 3 •-·, when the storage capacitor lines CM 1, CM 2, CM 3 · 'are formed at the same time as the second electrode portion C 2 protruding from them. Only the difference.

Therefore, in FIG. 7, a pattern A 3 for forming a lower polycrystalline silicon film for forming the first electrode portion C 1 of the TFT 11 and the storage capacitor CS and a gate A 3 are formed. , G 2, G 3,, gate electrode 113, storage capacitance lines CM 1, CM 2, CM 3, and 'and the second electrode section C of storage capacitance capacitor CS The portion overlapping the pattern A5 of the upper polycrystalline silicon film for forming layer 2 is shaded as the opposite portion CO of the storage capacitor capacitor CS. When expressed, the alignment between the pattern A3 of the polycrystalline silicon film and the pattern A5 of the polycrystalline silicon film is in the horizontal direction. (X direction), each pixel area is shaded between Ρ11, Ρ12, Ρ21, Ρ22, Ρ31, Ρ32, ·. The area of the opposing portion C 0 (the capacitance value of the storage capacitor CS) is always equal. Therefore, according to the present embodiment, the same effects as in the first embodiment can be obtained, for example, it is possible to prevent flickering in units of gate lines.

Third embodiment

In each of the first and second embodiments, a coplanar TFT is used as the switching element. However, in this embodiment, an inverted staggered TFT is used instead. Yes.

FIG. 8 is a cross-sectional view of a TFT using an amorphous silicon film as an active layer and a storage capacitor. In FIG. 8, on the front side of a glass substrate 1OA, a gate electrode 113A made of a tantalum film is formed on a base film 110A. In addition, a tantalum oxide 114 A as a gate insulating film is formed. On the surface of the tantalum oxide 114 A, silicon nitride 114 B is formed, and the tantalum oxide 114 A and the silicon nitride 111 B are formed. Function as a gate insulating film. On the surface side of the silicon nitride 114B, an intrinsic amorphous silicon film 117A for forming a channel is formed. On the surface side of the intrinsic amorphous silicon film 117A, a high-concentration N-type amorphous silicon film 116A is formed. In the N-type amorphous silicon film 1 16 A, a portion facing the gate electrode 1 13 A is etched, and the source region 1 1 1 A and the drain region 1 It is divided into 12 A and. In the source region 111A, an aluminum electrode layer 118B is formed via a molybdenum layer 118A, and the aluminum electrode layer 118B is formed. B is connected to source lines S1, S2, S3, and so on. A pixel electrode 12A made of an ITO film is connected to the drain region 112A. As shown in FIG. 9, the pixel electrode 12 A (IT0 film) is formed up to the edge of the pixel regions Pll, PI.2, P13,. The end of the pixel electrode 12A is the first electrode C1 of the storage capacitor CS.

On the lower layer side of the first electrode part C 1, a storage capacitor composed of tantalum oxide 114 A and silicon nitride 114 B formed simultaneously with the gate insulating film. The dielectric film C 3 of the capacitor CS is formed. On the lower layer side of the dielectric film C3, a tantalum film formed simultaneously with the gate electrode 113A is formed, and this tantalum film is the second of the storage capacitor capacitor CS. The electrode part C 2 is connected.

The other configuration is almost the same as that of the first embodiment, and a detailed description thereof will be omitted. Also in the present embodiment, as shown in FIG. 9, the pixel regions P 11, Ρ 12, Ρ 13,... Are arranged corresponding to the color filters 21 of the delta arrangement. . Here, for the same source lines S1, S2, S3, and so on, the pixel regions 領域 11, Ρ12, Ρ13, and so on corresponding to the same color Only the primary electrodes 12 A are connected. For this reason, the same source line S 2 has pixel regions P 12, Ρ 22, Ρ 32... Corresponding to green (G) from the right and left opposite sides of the source line S 2. Connected alternately.

In this case, as in the first embodiment, for example, in the pixel regions P12, Ρ22, Ρ32,... Arranged in the Y direction along the source line S2, the storage capacitor The capacitor CS is formed at the same position in the pixel area. That is, the first electrode portion C 1 of the storage capacitor capacitor CS differs from that of the first embodiment in that the first electrode portion C 1 is constituted by the end portion of the pixel electrode 12 A. The relative positional relationship between C 1 and the second electrode portion C 2 extending from the preceding gate lines GO, Gl, G 2 '*' is determined by the pixel regions PI 1, 1 Set up so that they match in both the X and Y directions between 2, 13, ...

き £ wasteful paper (¾Iil9l) It is specified. Therefore, in FIG. 10, in FIG. 10, a pattern A7 for forming an IT0 film for forming the pixel electrode 12A and the first electrode portion C1 of the storage capacitor CS, and a gate line G l, G2, G3-..., a gate electrode 113A and a pattern A6 for forming an aluminum film for forming the second electrode part C2 of the storage capacitor CS. When the overlapped portion is indicated by hatching as the opposed portion CO of the storage capacitor CS, the pattern A7 for forming the ITO film and the pattern A6 for forming the tantalum film are shown. When forming, even if an alignment shift occurs in the horizontal direction (X direction), the pixel regions P ll and P ll connected to the odd-numbered gate lines Gl, G3 1 2 · 保持 3 1, Ρ 3 2 · '保持保持保持保持保持保持保持保持画素画素画素保持画素画素画素画素画素画素画素画素Capacitor CS The area of the hatched portion CO (capacitance value of the storage capacitor CS) is equal to that between the two. Therefore, according to the present embodiment, the occurrence of flicker in each gate line is reduced. This has the same effect as that of the first embodiment, such as prevention.

In this embodiment, when forming the second electrode portion C 2, the gate lines GO, Gl, G 2, G 3- However, as in the second embodiment, dedicated storage capacitance lines CM1, CM2, CM3,... May be formed and used to form the storage capacitance capacitor CS. No. Fourth embodiment

The first to third embodiments are directed to a liquid crystal display device using a delta-arranged color filter, but the present embodiment is directed to a mosaic-arranged power filter. This is an example of a liquid crystal display device using the same. In this embodiment, since the color filters are arranged in a mosaic arrangement, the pixels are arranged in a lattice, but the other parts are the same as in the first embodiment. Therefore, corresponding parts are denoted by the same reference numerals and their detailed description is omitted.

FIG. 11 is a diagram showing a pattern of each component of the active matrix substrate of the present embodiment. The surface of the transparent substrate corresponds to the intersection between the gate lines Gl, G2, G3-'extending in the X direction and the source lines SI, S2, S3 Pixel areas PI1, PI2, Ρ13 · · · · are formed. In these pixel areas Ρ 11, Ρ 12, · 13 ···, the TFT 1 as a switching element for the source lines SI, S 2, S 3 ··· ' The transparent pixel electrode 12 is connected via 1. In addition, in order to improve the holding characteristics of the liquid crystal capacitor CLC, a holding capacitor is placed between the previous gate lines GO, Gl, G2, G3- Capacitor CS is formed.

Such a configuration is the same as the case where the color filters 21 are arranged in a delta array as in the first to third embodiments, but in this embodiment, the red color is used. Since the color filters 21 of R, green G, and blue B are formed in a mosaic arrangement, they correspond to the color filters 21 of red R, green G, and blue B. Thus, the pixel regions Pll, PI2, 、 13,... Are arranged.

In Fig. 11, for each pixel area Pll, P12, P13, ..., the color type of the corresponding color filter is indicated by (R), (G), and (B). It is shown. Here, the color filters of three colors of red, green, and blue are periodically arranged in the X direction with these three colors as one unit, as shown in FIG. ing. Here, the first color filter sequence F 1 (odd-level color filter sequence) and the second color filter sequence: F 2 ′ (even-numbered color sequence) (A filter row) is in a state of being alternately shifted in the X direction by a distance corresponding to 13 periods of the above-mentioned one unit period.

Connected to the gate line G1 corresponding to such an arrangement of color filters The three pixel areas PI1, PI2, and P1 corresponding to the color filters 21 of red R, green G, and blue B in the pixel areas Pll, P12, and P13 The first pixel row (the odd-numbered pixel row) is formed by linearly repeating and arranging 3 as one unit in the X direction. Also, in the second pixel column (even-numbered pixel column) composed of the pixel regions Ρ21, Ρ22, Ρ23... Connected to the gate line G2, the red R The three pixel areas P 21, P 22, and P 23 corresponding to green, green G, and blue B are arranged as a unit in a linearly repeated manner in the X direction. Here, between the first pixel row (the odd-numbered pixel row) and the second pixel row (the even-numbered pixel row), the red R, green G, and blue B color buffers are arranged. Filters 21 Arranged so that pixel areas of three colors corresponding to 1 are periodically arranged as one unit, and are shifted in the X direction by a distance equivalent to 1/3 cycle and alternately. It is. As a result, the center position of each pixel area Pll, PI2, PI3 'is shifted left and right by one pixel pitch per stage.

In the active matrix substrate thus configured, unlike the delta arrangement, each of the source lines S1, S2, S3,. Therefore, even when only the pixel electrodes of the pixel regions corresponding to the same color are connected, the source lines S l, S 2, S 3 ′ ′ linearly extend between the pixel regions in the Y direction. It is formed so as to extend.

Here, the same source line, for example, the source S 2, the pixel electrodes 12 of the pixel regions P 12, P 22, P 32, are alternately connected from the left and right opposite sides This is the same as in the first to third embodiments. Therefore, between each of the pixel regions P ll, P 12, P 13,... Arranged in the X direction, the TFT 11, the pixel electrode 12, and the storage capacitor Cs (the first electrode C Although the relative formation positions of the first and second electrode portions C 2) are the same, the pixel regions 並 12, Ρ 22, Ρ 3 2... Arranged in the Y direction along the source line S 2 · Between TFT The relative formation positions of 11 and the pixel electrodes 12 are reversed left and right for each step. .

However, the storage capacitor CS is formed at the same relative position in any pixel region. In other words, the relative position of the storage capacitor Cs in the pixel region is the same between the storage capacitors adjacent in the Y direction.

Also, between the first electrode portion C 1 of the storage capacitor CS and the second electrode portion C 2 extending from the previous gate lines G 0, G l, G 2 ′ * ′. The relative positional relationship is the same in each of the X direction and the Y direction between the respective pixel regions P 12, Ρ 22, Ρ 32.

Therefore, when forming the first electrode portion C 1 and the second electrode portion C 2 of the storage capacitor CS, the alignment is performed in the left-right direction (X direction) or the up-down direction (Y direction). In the event of a misalignment, the odd-numbered gate lines Gl, G3

Pixel regions P ll, PI 2, P 1 3 corresponding to-and pixel regions P 21, P 22, P 2 corresponding to even-numbered gate lines G 2 ' 3 · ·

Since the capacitance value of the storage capacitor CS is equal between-and, the same effect as that of the first embodiment can be obtained, such as preventing occurrence of flicker in a gate line unit. .

Note that, similarly to the first embodiment, a part of the previous gate lines GO, Gl, G2, G3,... Is used for the second electrode section C2 of the storage capacitor capacitor CS. However, as in the second embodiment, dedicated storage capacitance lines CM1, CM2, CM3 are formed, and a part of the storage capacitance lines CM1, CM2, CM3 is formed. It may be used for

Further, the TFT 11 is not limited to a coplanar TFT, and an inverted staggered TFT may be used as in the third embodiment. Other embodiments

When the active matrix substrate of the present invention is used for a monochromatic liquid crystal display device, the active matrix substrate is not affected by misalignment as in the case of a color liquid crystal display device. This can prevent flicker caused by this.

In each of the embodiments, a transparent IT0 electrode was used. However, the present invention can be similarly applied to a reflective liquid crystal display device using an aluminum electrode or the like as a pixel electrode. Wear.

In addition, instead of a TFT, an active matrix substrate using a diode having a MIM (Metal-Insulator-Metal 1) structure as a switching element is also used. The present invention can be applied. That is, when the relative formation positions of the first electrode portion and the second electrode portion of the storage capacitor are the same between the storage capacitor capacitors adjacent to each other in the Y direction, the first embodiment is performed. Has the same effect as No.4.

[Industrial applicability]

As described above, in the present invention, the structures of the first electrode portion and the second electrode portion constituting the storage capacitor of the active matrix substrate are parallel between the pixel regions. A pattern that can be superimposed by moving it, that is, the relative positional relationship between the first electrode section and the second electrode section is the same in each pixel area. Having. Therefore, according to the present invention, the capacitance values of the storage capacitor capacitors are not equal even if the first electrode portion and the second electrode portion are misaligned when forming the first electrode portion and the second electrode portion. You. Therefore, the difference in capacitance value of the storage capacitor between the odd-numbered gate stage and the even-numbered gate stage can be eliminated, and flicker can be reduced. You.

Further, in the pixel region, the formation positions and occupied areas of the first electrode portion and the second electrode portion are limited, but according to the present invention, the first electrode portion and the second electrode portion By merely optimizing the relative positional relationship with the part, it is possible to prevent flicker caused by misalignment when forming the first electrode part and the second electrode part. You. Therefore, it is particularly advantageous when realizing a high-definition and high-density liquid crystal display device.

Further, only the formation pattern of the first electrode portion is different between the pixel region corresponding to the odd-numbered gate stage and the pixel region corresponding to the even-numbered gate stage. The patterns of the parts are substantially equal. Therefore, there is a misalignment between the opposing substrate with the color filter and the active matrix substrate, or an alignment error on the active matrix substrate. Even if a gap occurs, there is no difference in aperture ratio between the pixel areas connected to the odd-numbered gate stages and the pixel areas connected to the even-numbered gate stages, and the horizontal line The unevenness can be effectively prevented. -

Claims

The scope of the claims

1. A plurality of gate lines extending in the X direction, a plurality of source lines extending in the Y direction orthogonal to the X direction, and boats arranged corresponding to intersections of the gate lines and the source lines. A plurality of pixel electrodes, a gate electrode electrically connected to the gate line, a source region electrically connected to the source line, and a drain electrically connected to the pixel electrode. And a plurality of thin-film transistors arranged corresponding to the pixel electrodes, and a first electrode portion electrically connected to the pixel electrodes and a gate line at a preceding stage. A plurality of storage capacitor capacitors, each of which has a second electrode portion and a plurality of storage capacitors, which are arranged corresponding to the pixel electrodes, and

Among a plurality of pixel electrodes electrically connected to the same source line via the thin film transistor, pixel electrodes adjacent to each other in the Y direction sandwich the same source line. At the opposite side with

Between the storage capacitor capacitors electrically connected to adjacent gate lines, the relative formation position of the first electrode portion with respect to the second electrode portion is the same. And an active matrix substrate.

2. A plurality of gate lines extending in the X direction, a plurality of storage capacitor lines extending in the X direction, a plurality of source lines extending in the Y direction orthogonal to the X direction, the gate lines and A plurality of pixel electrodes arranged corresponding to intersections with the source lines; a gate electrode electrically connected to the gate lines; and a source region electrically connected to the source lines. A plurality of thin film transistors having a drain area electrically connected to the pixel electrode and arranged corresponding to the pixel electrode; and electrically connected to the pixel electrode. A first electrode portion and a second electrode portion electrically connected to the storage capacitor line, and arranged corresponding to the pixel electrode. Having a storage capacitor and

Among a plurality of pixel electrodes electrically connected to the same source line via the thin film transistor, pixel electrodes adjacent in the Y direction sandwich the same source line. At the opposite side with

'The relative formation position of the first electrode portion with respect to the second electrode portion is the same between storage capacitor capacitors electrically connected to adjacent storage capacitor lines. An active matrix substrate characterized by this.

3. A color liquid crystal display device using the active matrix substrate described in claim 1 or claim 2,

A first color filter in which three color filters of red, green, and blue formed corresponding to the pixel electrodes are periodically arranged in the X direction using the three colors as one unit. A second color filter that is adjacent to the first color filter row in the Y direction and that is periodically arranged in the X direction using the above three colors as one unit. With columns and

The first color filter row and the second color filter row are alternately displaced in the X direction by a distance corresponding to 12 periods of the one unit period. And

For the same source line, only a pixel electrode corresponding to a color filter of the same color is connected via the thin-film transistor. One liquid crystal display.

4. A color liquid crystal display device using the active matrix substrate described in claim 1 or 2, wherein:

A first color filter in which three color filters of red, green, and blue formed corresponding to the pixel electrodes are periodically arranged in the X direction using the three colors as one unit. A second color filter row adjacent to the first color filter row in the Y direction and periodically arranged in the X direction using the three colors as one unit; With one filter sequence and

The first color filter row and the second color filter row are arranged so as to be alternately shifted in the X direction by a distance corresponding to 1Z3 cycle of the above-described one unit cycle. And

For the same source line, only the pixel electrode corresponding to the color filter of the same color is contacted with the gun through the thin-film transistor. One liquid crystal display.