JP2541446B2 - Active matrix panel - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching element arrangement side panel used in an active matrix liquid crystal display element.

[0002]

2. Description of the Related Art An active matrix liquid crystal display device using thin film transistors (TFTs) as active devices is provided with a group of pixel electrodes, a plurality of gate lines and data lines, and a plurality of thin film transistors corresponding to the respective pixel electrodes on a transparent substrate. A liquid crystal display device for displaying a multicolor image such as a full color image, in which liquid crystal is enclosed between a TFT panel and a counter panel provided with a counter electrode facing the pixel electrode group on a transparent substrate, Red, green, and blue color filters are provided on the opposing panel or the TFT panel so as to correspond to the respective pixel electrodes.

By the way, there are various methods for arraying pixels in the active matrix liquid crystal display element, and one method is to display pixels in a mosaic array pattern.

This system is mainly used in liquid crystal display devices for displaying multicolor or full-color images. Liquid crystal display devices for displaying red, green and blue pixels in a mosaic array pattern are , It has the advantage of being able to express colors with a good mixture of colors.

A TFT panel used in an active matrix liquid crystal display device of the type in which the red, green and blue pixels are displayed in a mosaic pattern is conventionally constructed as follows. FIG. 4 is a plan view of a part of a conventional TFT panel. This TFT panel is used for a liquid crystal display element in which red, green, and blue color filters are provided on a counter panel.

This TFT panel is a pixel in which a plurality of pixel electrodes 2R, 2G, 2B are arranged in a row direction (horizontal direction in the drawing) and a column direction (vertical direction in the drawing) on a transparent substrate 1 made of glass or the like. An electrode group and a plurality of thin film transistors 3 connected to each pixel electrode of this pixel electrode group
And a plurality of gate lines Lg that are wired corresponding to the respective pixel electrode rows of the pixel electrode group and supply a gate signal to the thin film transistor 3, and are wired corresponding to the respective pixel electrode columns of the pixel electrode group. A plurality of data lines L for supplying a data signal to the thin film transistor 3
d is formed.

First, the pixel electrode group will be described. Each pixel electrode 2R, 2G, 2B of this pixel electrode group is formed of a transparent conductive film such as ITO. These pixel electrodes 2R,
Of 2G and 2B, 2R is a pixel electrode for displaying a red pixel (an electrode corresponding to the red color filter on the counter panel side), and 2G is a pixel electrode for displaying a green pixel (a green color filter on the counter panel side). Corresponds to the electrode), 2
B is a pixel electrode (an electrode corresponding to the blue color filter on the opposite panel side) for displaying a blue pixel, and these pixel electrodes 2R, 2G, and 2B are alternately arranged in the row direction (horizontal direction in the drawing). They are arranged in a straight line, and in the column direction,
Pixel electrodes for displaying pixels of the same color, that is, pixel electrodes corresponding to the same data line Ld are arranged in one direction and the other direction (left direction and right direction in the figure) by about 1.5 pitches for each row. They are arranged alternately in a zigzag pattern.

In addition, each pixel electrode 2R of the pixel electrode group,
The thin film transistors 3 corresponding to 2G and 2B are
The gate electrode g formed on the substrate 1 and the gate electrode g
A gate insulating film 4 made of Si N (silicon nitride) or the like for covering the gate insulating film 4 and a-Si (amorphous silicon) formed on the gate insulating film 4 so as to face the gate electrode g.
And a source electrode s and a drain electrode formed on the i-type semiconductor film 5 via an n-type semiconductor film (not shown) made of a-Si doped with an n-type impurity. d and.

On the other hand, the gate line Lg corresponding to each pixel electrode row of the pixel electrode group is wired on the substrate 1 along the pixel electrode row, and the gate electrode g of each thin film transistor 3 is The gate line Lg is formed integrally with the gate line Lg so as to project to one side thereof, and the source electrode s and the drain electrode d are arranged in the direction along the gate line Lg.

The gate insulating film 4 of the thin film transistor 3 is formed on almost the entire surface of the substrate 1 so as to cover the gate line Lg, and the pixel electrodes 2R, 2G and 2B are formed on the gate insulating film 4. And is connected to the source electrode s of the thin film transistor 3 at the edge thereof.

On the other hand, the data line Ld corresponding to each pixel electrode column for displaying pixels of the same color of the pixel electrode group is formed by an interlayer insulating film (SiN, etc.) formed on the gate insulating film 4 ( (Not shown) is arranged in a zigzag pattern so as to correspond to the pixel electrode columns, and the data line Ld is connected to the drain electrode d of the thin film transistor 3 in a contact hole provided in the interlayer insulating film. It is connected to the.

Explaining the wiring state of the data line Ld with respect to the data line corresponding to the pixel electrode column for displaying the red pixel, the data line Ld among the pixel electrodes 2R arranged in zigzag. The meandering wiring is arranged along the right side edge of the pixel electrode 2R which is displaced to the left and the left side edge of the pixel electrode 2R which is displaced to the right. That is, the data line Ld is wired such that the vertical line portion Ldy along the column direction and the horizontal line portion Ldx bent from the vertical line portion Ldy along the row direction are alternately continuous.

The data line Ld is arranged along the right side edge of the pixel electrode 2R displaced leftward and the left side edge of the pixel electrode 2R displaced rightward in the row direction. This is for shortening the length of the transverse line portion Ldx along the line Ldx and simplifying the routing of the data line Ld.

However, when the data line Ld is wired as described above, the position of the data line Ld with respect to the thin film transistor 3 corresponding to the pixel electrode 2R displaced leftward and the position of the pixel electrode 2R displaced rightward are corresponded. The position of the data line Ld with respect to the thin film transistor 3 is opposite to each other.

Therefore, in this TFT panel, the thin film transistor 3 corresponding to the pixel electrode 2R displaced to the left is provided.
And the source and drain electrodes s and d with respect to the thin film transistor 3 corresponding to the pixel electrode 2R displaced to the right, the positional relationship is reversed, and the pixel electrode 2R is connected to the source electrode s of these thin film transistors 3. The data line Ld is connected to d.

The wiring state of the data line Ld is the same for the data line corresponding to the pixel electrode column for displaying the green pixel and the data line corresponding to the pixel electrode column for displaying the blue pixel. , The thin film transistor 3 corresponding to the pixel electrode 2G for displaying the green pixel and the thin film transistor 3 corresponding to the pixel electrode 2B for displaying the blue pixel both correspond to the pixel electrode displaced to the left and the right direction. The source and drain electrodes s and d have a positional relationship opposite to that of the pixel electrode corresponding to the pixel electrode 2G,
2B is connected, and the data line Ld is connected to the drain electrode d.

Further, the transverse line portion Ldx of the data line Ld is arranged on the side of the gate line Lg while avoiding the gate line Lg, and the pixel electrodes 2R, 2G, 2B are
A wiring space for the vertical line portion Ldy of the data line Ld is secured between the columns, and two wiring spaces for the horizontal line portion Ldx and the gate line Lg of the data line Ld are secured between the rows.

Further, in FIG. 4, Lc is a capacitor line forming a compensation capacitance (storage capacitor) for holding the potential of each pixel electrode 2R, 2G, 2B, and this capacitor line Lc is each pixel electrode. Wiring is made to correspond to each row.

The capacitor line Lc is arranged on the substrate 1 so as to oppose one end edge portion (edge portion on the side opposite to the wiring side of the gate line Lg) of the pixel electrodes 2R, 2G, 2B in each row. , The above-mentioned compensation capacitance is the pixel electrodes 2R, 2
G, 2B, the capacitor line Lc, and the gate insulating film 4 between them.

In the TFT panel shown in FIG. 4, in order to form a compensation capacitance having a sufficient capacitance value, the capacitor line Lc is formed with protrusions facing both side edges of the pixel electrodes 2R, 2G and 2B. The facing area between the capacitor line Lc and the pixel electrodes 2R, 2G, 2B is increased.

The capacitor line Lc is generally formed of the same opaque metal film as the gate electrode g and the gate line Lg of the thin film transistor 3, but the capacitor line Lc is formed of a transparent conductive film such as ITO. There is also.

[0022]

However, in the above-mentioned conventional TFT panel, since the traverse line portion Ldx of the data line Ld to be meandering is arranged on the side of the gate line Lg while avoiding the top of the gate line Lg. Pixel electrodes 2R, 2G,
2B, the horizontal line portion L of the data line Ld between the rows
Two wiring spaces for the dx and the gate line Lg must be secured and arranged, and for that purpose, the pixel electrode 2
Since the area of R, 2G, 2B (the area excluding the portion facing the capacitor line Lc when the capacitor line Lc is formed of an opaque metal film) must be reduced,
There is a problem that the aperture ratio of the liquid crystal display device is reduced.

According to the present invention, the pixel electrodes corresponding to the same data line are arranged in a zigzag pattern, and the data lines are arranged in a zigzag pattern in a meandering manner. It is an object of the present invention to provide a TFT panel capable of increasing the area and improving the aperture ratio of a liquid crystal display element.

[0024]

An active matrix panel according to the present invention includes a pixel electrode group in which a plurality of pixel electrodes are arranged in a row direction and a column direction on a transparent substrate, and each pixel electrode of the pixel electrode group. A plurality of connected switching elements, a plurality of scanning lines wired corresponding to each pixel electrode row of the pixel electrode group to supply a scanning signal to the switching element, and a plurality of pixel electrode columns of the pixel electrode group. A plurality of data lines, which are wired in correspondence with each other and supply a data signal to the switching element, are formed, and the pixel electrodes corresponding to the same data line are alternately arranged in each row in one direction and the other direction. The data lines are arranged in a zigzag pattern, and the data lines are arranged in a zigzag pattern so as to correspond to the pixel electrode columns. It is characterized in that the emission of the row direction and transverse line portion extending along the said scan line either in one region so as to face up and down arrangements included the other wire.

[0025]

In the TFT panel of the present invention, since the transverse line portion of the data line to be meandered is vertically opposed to the gate line, the wiring space secured between the rows of the pixel electrodes is one wiring. And therefore,
The area of the pixel electrode can be increased to improve the aperture ratio of the liquid crystal display element.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A TFT panel used in an active matrix liquid crystal display device of a system in which red, green and blue pixels are displayed in a mosaic array pattern will be described below with reference to FIGS. I will explain.

FIG. 1 is a plan view of a part of the TFT panel, FIG. 2 is an enlarged sectional view taken along line II-II of FIG. 1, and FIG. 3 is I of FIG.
It is an expanded sectional view which follows the II-III line. In the figure, those corresponding to the conventional TFT panel shown in FIG. 4 are denoted by the same reference numerals, and the description of the same parts as those of the conventional TFT panel is omitted.

This TFT panel includes a pixel electrode group in which a plurality of pixel electrodes 2R, 2G, 2B are arranged in a row direction and a column direction on a substrate 1, and each pixel electrode 2R,
2G, 2B, a plurality of thin film transistors 3 connected respectively, a plurality of gate lines Lg wired corresponding to each pixel electrode row of the pixel electrode group and supplying a gate signal to the thin film transistor 3, and the pixel electrode group. A plurality of data lines Ld wired corresponding to the respective pixel electrode columns to supply a data signal to the thin film transistor 3, and a capacitor line Lc forming a compensation capacitance between the respective pixel electrodes 2R, 2G, 2B. The pixel electrodes 2R, 2G, and 2B are arranged in a zigzag pattern by alternately shifting each row by 1.5 pitches in one direction and the other direction, similarly to the conventional TFT panel, and the gate lines. Lg and the capacitor line Lc are also wired as in the conventional TFT panel.

On the other hand, in this TFT panel, the thin film transistor 3 corresponding to each pixel electrode 2R, 2G, 2B of the above pixel electrode group has the following structure.
The data line Ld, which is meanderingly wired in correspondence with the pixel electrode columns arranged in a zigzag manner, is wired with its traverse line portion Ldx vertically facing the gate line Lg.

First, the structure of the thin film transistor 3 will be described.
As shown in FIG. 4, the gate electrode g formed integrally with the gate line Lg so as to project to one side thereof, the gate insulating film 4 made of Si 3 N or the like for covering the gate electrode g, and the gate insulating film 4 An i-type semiconductor film 5 made of a-Si formed facing the gate electrode g, and an n-type semiconductor film made of a-Si doped with an n-type impurity on the i-type semiconductor film 5. It is composed of a source electrode s and a drain electrode d which are formed via the electrode 6.

In this TFT panel, the thin film transistor 3 is the source electrode s and the drain electrode d, and the thin film transistor of the conventional TFT panel is 9
The structure is formed in different directions by 0 °. That is,
In the conventional TFT panel shown in FIG. 4, the thin film transistor 3 has a structure in which the source electrode s and the drain electrode d are arranged in the direction along the gate line Lg. In the TFT panel of this embodiment, the source of the thin film transistor 3 is used. The electrode s and the drain electrode d are arranged in the direction orthogonal to the gate line Lg.

Although the gate electrode g of the thin film transistor 3 is formed slightly larger than the area of the i-type semiconductor film 5 in FIGS. 1 and 3, the area of the gate electrode g is the same as that of the i-type semiconductor film 5. Or the i-type semiconductor film 5
It may be smaller than the i-type semiconductor film 5 as long as it is not smaller than the channel region.

Further, the gate insulating film 4 of the thin film transistor 3 is formed on almost the entire surface of the substrate 1 so as to cover the gate line Lg as in the conventional TFT panel, and the pixel electrodes 2R, 2G and 2B are formed as described above. It is formed on the gate insulating film 4 and is connected to the source electrode s of the thin film transistor 3 at the edge thereof.

Next, the wiring state of the data line Ld will be described with respect to the data line corresponding to the pixel electrode column for displaying the red pixel.
In order to shorten the length of the horizontal line portion Ldx and simplify the routing of the data line Ld, among the pixel electrodes 2R arranged in zigzag, the right side of the pixel electrode 2R that is displaced to the left The meandering wiring is provided along the edge and the left side edge of the pixel electrode 2R which is displaced to the right. That is, the data line Ld is wired such that the vertical line portion Ldy along the column direction and the horizontal line portion Ldx bent from the vertical line portion Ldy along the row direction are alternately continuous.

When the data line Ld is wired in this way, the position of the data line Ld with respect to the thin film transistor 3 corresponding to the pixel electrode 2R displaced to the left,
Although the position of the data line Ld with respect to the thin film transistor 3 corresponding to the pixel electrode 2R which is shifted to the right is opposite to each other, in this TFT panel, the thin film transistor 3 is provided with the source electrode s and the drain electrode d as gates. Since the structure is arranged in the direction orthogonal to the line Lg, it is not necessary to reverse the positional relationship between the source and drain electrodes s and d of the thin film transistors 3 in each column as in the conventional TFT panel.

The wiring state of the data line Ld is the same for the data line corresponding to the pixel electrode column for displaying the green pixel and the data line corresponding to the pixel electrode column for displaying the blue pixel.

The data line Ld is integrally formed with a protrusion Lda corresponding to each thin film transistor 3, and the data line Ld is connected to the drain electrode d of the thin film transistor 3 at the protrusion Lda. Has been done.

As shown in FIG. 2, the data line Ld is arranged on the interlayer insulating film 7 (not shown in FIG. 1) made of SiN or the like formed on the gate insulating film 4. ing. The interlayer insulating film 7 is formed so as to cover not only the wiring portion of the data line Ld but also the thin film transistor 3 as shown in FIG. 3, and the protruding portion Lda of the data line Ld is provided in the interlayer insulating film 7. Contact hole 8
At the drain electrode d of the thin film transistor 3.

The transverse line portion Ldx bent along the row direction of the data line Ld has a gate line L.
The gate line Lg is provided right above the gate line Lg, and between the transverse line portion Ldx of the data line Ld and the gate line Lg, there are two layers of the gate insulating film 4 and the interlayer insulating film 7. It is insulated by the insulating film.

That is, the TFT panel has pixel electrodes 2R, 2G, 2B corresponding to the same data line Ld.
Are arranged alternately in one direction and the other direction in each row and arranged in a zigzag manner, and the data lines Ld are arranged in a zigzag manner in a meandering manner, and the data lines Ld are arranged in zigzag. The transverse line portion Ldx is wired so as to face the gate line Lg vertically.

In this TFT panel, since the transverse line portion Ldx of the data line Ld to be meandered is vertically opposed to the gate line Lg, the wiring is secured between the pixel electrodes 2R, 2G, 2B. Space is 1
One wiring line is enough. In addition, each pixel electrode 2R, 2G, 2B
Between the columns, the wiring space of the vertical line portion Ldy of the data line Ld may be secured as in the conventional TFT panel.

Therefore, according to the above TFT panel,
Each pixel electrode 2R, 2 corresponding to the same data line Ld
G and 2B are arranged in a zigzag pattern, and the data lines Ld are arranged in a zigzag pattern in a meandering manner, but the area of the pixel electrodes 2R, 2G, and 2B is increased to increase the liquid crystal. The aperture ratio of the display element can be improved.

However, in this TFT panel, since the transverse line portion Ldx of the data line Ld and the gate line Lg are vertically opposed to each other via the gate insulating film 4 and the interlayer insulating film 7, the data line Ld of the data line Ld. Traverse line part Ldx
And a gate line Lg form a parasitic capacitance between the gate line Lg and the data line Ld.
Will cause a voltage drop at.

In the conventional TFT panel shown in FIG. 4, the parasitic capacitance is formed at the intersection of the vertical line portion Ldy of the data line Ld and the gate line Lg. Then, the data line Ld
Since the traverse line portion Ldx of the gate line Lg faces the gate line Lg, the value of the parasitic capacitance formed therebetween is the same as that of the conventional TF.
Larger than T-panel.

Since the voltage of the gate signal applied to the gate line Lg is sufficiently high, the voltage drop in the gate line Lg does not pose a problem, but the data line Lg.
Since the data signal applied to d is a voltage signal corresponding to the image data, when the voltage of the data signal drops on the data line Ld, the end side of the data line Ld (the opposite side to the data signal application side). The closer to, the lower the voltage of the data signal supplied from the data line Ld to the pixel electrodes 2R, 2G, 2B via the thin film transistor 3, and the display unevenness occurs on the liquid crystal display element.

However, also in the TFT panel of the above embodiment, the data line Ld is set to Al (aluminum) or Al.
If it is made of a low resistance metal such as a series alloy, the data line Ld
It is possible to make the liquid crystal display element perform good display with no display unevenness by reducing the voltage drop at.

That is, the amount of voltage drop over the entire length of the data line Ld is determined by the product of the resistance value of the data line Ld and the total value of the parasitic capacitances scattered on the data line Ld. Is formed of a low resistance metal such as Al or an Al-based alloy, the amount of voltage drop in the data line Ld can be reduced even if the value of the parasitic capacitance is large to some extent (theoretically, If the resistance value is 0, the voltage drop amount on the data line Ld becomes 0 regardless of the value of the parasitic capacitance).

The above TFT panel is particularly suitable for a liquid crystal display element of a medium screen or a small screen. In the case of a liquid crystal display element of a medium screen or a small screen, the length of the data line Ld is short, Even if the data line Ld is formed of a metal other than Al or an Al-based alloy, its resistance value is small, and since the number of pixels is small, the number of the parasitic capacitances scattered on the data line Ld is also small. Since the voltage drop in the data line Ld is small, display unevenness does not occur in the liquid crystal display element.

In the above embodiment, the thin film transistor 3 has the structure in which the source electrode s and the drain electrode d are arranged in the direction orthogonal to the gate line Lg. However, this thin film transistor 3 has the structure shown in FIG. Similar to the thin film transistor 3 of the TFT panel, the source electrode s and the drain electrode d may be arranged in the direction along the gate line Lg.

In addition, the TFT panel of the above embodiment is red,
The present invention is used for an active matrix liquid crystal display device of a type that displays green and blue pixels in a mosaic array pattern. However, the present invention provides that each pixel electrode corresponding to the same data line is arranged in one direction in each row and in another direction. It is used in an active matrix liquid crystal display device of another method as long as the data lines are arranged in zigzag alternately with respect to the direction, and the data lines are arranged in a zigzag pattern in a meandering manner. It can also be applied to a TFT panel.

[0051]

According to the active matrix panel of the present invention, the traverse line portions of the data lines to be meandered and the scanning lines are arranged so as to vertically oppose each other in an arrangement in which one region includes the other. Therefore, the wiring space secured between the rows of the pixel electrodes may be one wiring, and therefore, the pixel electrodes corresponding to the same data line may be arranged in a zigzag pattern so as to meander. However, the area of the pixel electrode can be increased to improve the aperture ratio of the liquid crystal display element.

[Brief description of drawings]

FIG. 1 is a plan view of a part of a TFT panel showing an embodiment of the present invention.

FIG. 2 is an enlarged sectional view taken along line II-II of FIG.

FIG. 3 is an enlarged sectional view taken along line III-III in FIG.

FIG. 4 is a plan view of a part of a conventional TFT panel.

[Explanation of symbols]

 1 ... Substrate 2R, 2G, 2B ... Pixel electrode 3 ... Thin film transistor g ... Gate electrode 4 ... Gate insulating film 5 ... i-type semiconductor layer 6 ... N-type semiconductor layer s ... Source electrode d ... Drain electrode Lg ... Gate line Lc ... Capacitor Line 7 ... Interlayer insulating film Ld ... Data line Ldx ... Transverse line part

Claims (1)

(57) [Claims] 1. A pixel electrode group in which a plurality of pixel electrodes are arranged in a row direction and a column direction on a transparent substrate, and a plurality of switching elements connected to each pixel electrode of the pixel electrode group.
And children, and the pixel electrode group of the plurality of scanning lines for supplying scanning signals to the switching elements are wired respectively corresponding to each pixel electrode row, respectively are wired to correspond to each pixel electrode row of said pixel electrodes A plurality of data lines for supplying a data signal to the switching element are formed, and each pixel electrode corresponding to the same data line is arranged in a zigzag pattern by staggering each row in one direction and the other direction. and, said data lines, together with the meandering lines to correspond to the pixel electrode columns are arranged in zigzag, either with said transverse line portion and the scanning line extending in the row direction of the data lines on the other hand In the area of
The active matrix panel is characterized in that the wirings are arranged so as to face each other vertically in the included arrangement .