JPH11344724A - Active matrix type liquid crystal display device and substrate used for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device of a high display grade which can be decreased in the number of data lines and is further lessened in the occurrence of flickering. SOLUTION: The surface of a substrate is provided with plural data lines Dia, Dib,... and plural gate lines Gja, Gjb,... in a matrix foot. The respective data lines are respectively provided with TFTs 1 on the same line and all the TFTs 1 on the substrate are provided with drain electrodes on the same side with respect to gate electrodes. The adjacent data lines Dia, Dib are electrically connected in a plurality each at both ends thereof. The respective gate lines are so disposed as to control the TFTs 1 connected to the respective data lines by the respectively different gate lines Gja, Gjb,....

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device and a matrix substrate used for the liquid crystal display device.

[0002]

2. Description of the Related Art As is well known, in an active matrix type liquid crystal display device, two glass substrates are fixed to face each other.
Liquid crystal is sealed in the gap, and a transparent common electrode is formed on one glass substrate, and a large number of transparent pixel electrodes are formed in a matrix on the other glass substrate, and each pixel electrode is Circuits for individually applying voltages are formed. FIG. 12 shows a general configuration of an active matrix type liquid crystal display device. More specifically, FIG. 12 shows a plan view of a substrate on the side where the pixel electrodes are formed, of the device. This active matrix type liquid crystal display device has m rows and n columns of dots PX (i, j) (i
= 1 to m, j = 1 to n), some of which are shown in FIG.
2 is shown. In the figure, rectangles arranged vertically and horizontally are indicated by broken lines, and these represent respective dots.

Each dot is regularly arranged in the horizontal direction (column direction) and the vertical direction (row direction), and n data lines Dj (j = 1) correspond to each column of these dots.
To n) are formed, and m gate lines Gi (i = 1 to m) are formed corresponding to each row of the dots. Here, each data line Dj (j = 1 to n) corresponds to each dot PX.
This is a line for supplying a signal voltage to (i, j) (i = 1 to m, j = 1 to n). Also, the gate line Gi (i = 1 to m)
Indicates the gate voltage for writing the signal voltage for each dot P
X (i, j) (i = 1 to m, j = 1 to n).

Each dot PX (i, j) has a thin film transistor (hereinafter abbreviated as TFT) 11 in addition to the above-mentioned pixel electrode. This TFT
Reference numeral 11 denotes a source electrode connected to the data line Dj, a gate electrode connected to the gate line Gi, and a drain electrode connected to the pixel electrode. Liquid crystal is interposed between the pixel electrode and the above-described common electrode, and the capacitance 12 in FIG. 12 represents a liquid crystal capacitance interposed between the pixel electrode and the common electrode. The TFT 11 functions as a switching element for switching whether or not to perform writing to the pixel, that is, whether or not to apply a signal voltage supplied via the data line Dj to the liquid crystal capacitor 12.

[0005]

Incidentally, the above-mentioned conventional active matrix type liquid crystal display device has a data line for each column of the dot arrangement, so that when the number of pixels per row is large, Accordingly, it is necessary to use a large number of data drivers accordingly. However, since the data driver is a relatively expensive component, the use of a large number of the data driver makes the entire device expensive. For example, a VGA-compatible liquid crystal display panel in which the number of dots in the column direction is 1920 and the number of dots in the row direction is 480,
It has data lines and 480 gate lines. 24
When this liquid crystal display panel is configured by the above-described conventional technique using a data driver and a gate driver having zero output terminals, eight data drivers are provided along the column direction.
It is necessary to provide two gate drivers along the row direction. With as many as eight data drivers,
The liquid crystal display panel becomes expensive.

In addition, the above-described conventional technology has a problem that it is difficult to form a liquid crystal display panel having a small display area. In other words, a data wiring terminal portion, which is a frame portion of the liquid crystal display panel, is provided with a large number of terminals for supplying signal voltages to the above-described data lines. It is necessary to reduce the size of the data wiring terminal. And
In order to reduce the size of the data wiring terminals, it is necessary to narrow the pitch of the terminals corresponding to the data lines. However, the liquid crystal display panel according to the prior art has a large number of data lines, so The demands for conversion will be extremely severe. For this reason, it is difficult to manufacture the data wiring terminal portion, which causes a problem such as a decrease in yield.

The present invention has been made in view of the above circumstances, and provides an active matrix type liquid crystal display device in which each dot can be driven by a smaller number of data lines as compared with the related art, and a substrate used therefor. It is intended to be.

[0008]

In order to achieve the above object, an active matrix type liquid crystal display substrate according to the present invention is provided with a plurality of data lines and a plurality of gate lines in a matrix on a substrate. TF on the same side for each data line
T and a pixel electrode connected to the TFT are provided, respectively, a drain electrode forming the TFT is provided on the same side as the TFT extending from the gate line, and a predetermined number of the data lines are electrically connected. The plurality of gate lines are provided so that TFTs connected to each of the predetermined data lines are controlled by different gate lines.

A substrate for an active matrix type liquid crystal display device (hereinafter, simply referred to as an active matrix substrate) capable of driving each dot by a smaller number of data lines than before can be of several types. ,
Among them, an object of the present invention is to provide a liquid crystal display device with high display quality in which generation of flicker is reduced. This will be described below. FIG. 13 shows an example of a substrate for an active matrix type liquid crystal display device in which the number of data lines is reduced to half that of a conventional substrate. This is because, for example, two rows of dots PX (i, j) and PX (i, j) arranged with one data line Dj + 1 interposed therebetween.
j + 1) (both i = 1 to m) and the data line Dj + 1
With this configuration, the number of data lines can be reduced by half, and the number of data drivers can be reduced. In each row, two dots sandwiching the data line Dj + 1, for example, dots PX (i, j) and PX (i, j +
1) is driven by separate gate lines GAi, GBi. As a result of this configuration, the two dots PX (i,
j) and PX (i, j + 1) TFTs 21a and 21b are arranged point-symmetrically with respect to the center point of these two dots.
In these two TFTs 21a and 21b, the positions of the drain and the source are reversed (in the horizontal direction in the drawing) with respect to the gate.

FIGS. 14A and 14B show TFTs 21 of the two dots PX (i, j) and PX (i, j + 1).
It is a figure which shows the part of 21a and 21b. For convenience of explanation, the dot PX (i, j) on the left side of the data line is represented by dot a,
The right dot PX (i, j + 1) will be referred to as dot b. Generally, the overlapping portion between the gate electrode and the drain electrode of the TFT becomes the gate-drain parasitic capacitance Cgd (actually, the overlapping portion between the island and the gate electrode also affects Cgd), and the area of this overlapping portion depends on the process accuracy in the manufacturing process. (Specifically, the alignment accuracy of the exposure machine), and the gate-drain parasitic capacitance C
gd will vary.

Each of the TFTs 21a and 2a for the dot a and the dot b
If the positions of the drain layer with respect to the gate layer are as designed in the case where 1b are point-symmetric with respect to each other, FIG.
As shown in FIG.
1b each gate electrode 22a, 22b and drain electrode 2
The dimensions La and Lb (including the dimension from the center of the island to the end of the drain electrode) of the overlapping portion with 3a and 23b are equal, the gate-drain parasitic capacitance of dot a is Cgda, and the gate-drain of dot b is Parasitic capacitance is Cgd
Assuming b, Cgda = Cgdb. However, FIG.
As shown in (B), for example, when the drain layer is shifted to the left with respect to the gate layer, the gate electrode 22b of dot b is larger than the dimension L'a of the overlapping portion of the gate electrode 22a of dot a and the drain electrode 23a. The dimension L'b of the overlapping portion between the gate electrode and the drain electrode 23b increases. As a result, the relationship between the gate-drain parasitic capacitance of the dot a and the dot b is C'gda <C'gdb (accurately, the parasitic capacitance includes the overlapping portion of the island and the gate electrode). That is, when the TFT is located at a point-symmetric position in the substrate, the gate-drain parasitic capacitance varies within the same substrate due to the alignment accuracy of the exposure apparatus.

The feed-through voltage ΔVp when the gate voltage Vg is applied to the TFT is expressed by the following equation. ΔVp = {(Cgd) / (Clc + Cs + Cgd)}
Vg (however, Clc: liquid crystal capacitance, Cs: storage capacitance) Therefore, if the gate-drain parasitic capacitance Cgd differs, the feedthrough voltage ΔVp changes. In addition, if the feedthrough voltage changes due to the relationship between the feedthrough voltage and the offset voltage, the offset voltage also changes. Therefore, if the gate-drain parasitic capacitance changes, the offset voltage changes. Therefore, the TF having the above configuration
In the case of the T substrate, the offset voltage differs for each dot within the same substrate, and the offset cannot be adjusted for all the dots. Therefore, flicker occurs.

The active matrix substrate of the present invention is intended to suppress the occurrence of flicker due to process accuracy while inheriting the idea of sharing a data line with a plurality of dots in the same row. Therefore, in order to realize this, as described above, the TFT is provided on the same side for each data line, and the drain electrode of each TFT is provided on the same side with respect to the gate electrode. That is, the TFTs are not point-symmetrically arranged, but the positional relationship between the source electrode and the drain electrode in one TFT is the same for all TFTs on the substrate. With this configuration, even if the alignment of the drain layer with respect to the gate layer is deviated, all TFTs on the substrate are deviated in the same direction, so that the gate-drain parasitic capacitance is equal between the TFTs, and the offset voltage is reduced. Be uniform within the substrate. Thereby, generation of flicker can be suppressed.

Further, even if a data line is provided for each column, the number of data lines at a connection portion with a data driver can be reduced by electrically connecting a plurality of data lines at predetermined intervals. Therefore, the number of data drivers can be reduced as compared with the conventional case. Therefore, the same data signal is supplied to the predetermined number of data lines. However, it is difficult to control the TFTs connected to each data line of the electrically connected data lines by different gate lines. Drive can be performed without the need.

Preferably, the electrically connected data lines are connected to each other at least at both ends of the data lines. When electrically connecting a predetermined number of data lines, functionally, only one point on the side connected to the data driver needs to be connected to each other.
In a case where the data lines are connected to each other at least at both ends, even if one of the data lines is disconnected, the supply of the data signal is not interrupted, so that a line defect can be prevented. That is, according to this structure, a redundant structure can be provided for disconnection defects, and the yield can be improved.

It is preferable that the plurality of data lines are electrically connected to each other by a predetermined number every odd number. In order to improve the display quality, particularly to reduce the crosstalk, a so-called data line inversion drive in which data signals having different polarities are supplied to even-numbered data lines and odd-numbered data lines is generally employed. However, in the present invention, when adjacent data lines are electrically connected, the dots corresponding to the electrically connected data lines may have the same polarity, and the pixel potential may be reduced due to the coupling due to the parasitic capacitance. , The data line inversion drive does not function effectively. On the other hand, when the data lines are electrically connected every other odd number, if a signal of opposite polarity is supplied to each pair of connected data lines, the polarity is always reversed between two adjacent data lines. Thus, the data line inversion drive functions effectively for an arbitrary dot. As a result, crosstalk is reduced, and display quality can be improved.

Further, it is preferable that one or more and a predetermined number or less of gate lines crossing the pixel electrode are stacked on each of the pixel electrodes. In that case, the pixel electrode and one or more and the predetermined or less gate lines cooperate to form a storage capacitor. That is, in the present invention, since the TFTs connected to each data line of the electrically connected data lines are controlled by different gate lines, when focusing on one dot, other TFTs are controlled in the dot. The gate line for the operation will cross. However, since the region crossed by the gate line can be used as a storage capacitor, the aperture ratio does not decrease even if the structure crosses the gate line.

By interposing a liquid crystal between the active matrix substrate and the substrate provided with the common electrode, the active matrix type liquid crystal display device of the present invention can be constituted. ADVANTAGE OF THE INVENTION According to the active matrix type liquid crystal display device of this invention, cost reduction can be achieved by reducing the number of data drivers compared with the conventional device, and a high display quality liquid crystal display device with reduced flicker is realized. be able to.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram showing an equivalent circuit of an active matrix substrate in the liquid crystal display device of the present embodiment.
Is an actual design layout diagram. As shown in FIGS. 1 and 2, a plurality of data lines Di are arranged in a matrix on a substrate.
, and a plurality of gate lines Gja, Gjb,..., and a TFT 1 is provided on the same side (the right side in the figure) for each data line Dia, Dib,.
Therefore, each TFT 1 is in a parallel positional relationship,
In any of the TFTs 1 in the substrate, the data lines Dia,
Are arranged on the left side, and the drain electrode 4 connected to the pixel electrode 3 is located on the right side. The pixel electrode 3 and a common electrode opposed to the pixel electrode 3 with the liquid crystal interposed therebetween constitute a liquid crystal capacitor Clc.

In this embodiment, as shown in FIG. 1, adjacent data lines Dia, Dib, Di + 1a, Di + 1
b are connected at both ends at two ends, and one end connected to the data driver is one data line Di, Di +
It extends as 1, ... And two connected to each other
The gate electrode 5 of each TFT 1 corresponding to the set of data lines Di is connected to different gate lines Gja, Gjb,. Similarly, the gate electrodes of the respective TFTs 1 corresponding to the pair of adjacent data lines Di + 1 are repeatedly connected to different gate lines Gja, Gjb,. Each gate line is arranged at equal intervals, and as shown in FIG. 2, any one dot, for example, a data line Dia,
Dib, the gate line Gjb connected to the TFT 1 of the adjacent dot crosses the center of the pixel electrode 3 of the dot surrounded by the gate lines Gja and Gj + 1a. In this portion, the pixel electrode 3 and the gate line Gjb It has a structure in which the dots are stacked via an insulating film, and constitutes the storage capacitance Cs of the dot.

When driving the liquid crystal display device having the above configuration, interlaced driving of one frame in two fields is employed. That is, two adjacent data lines Dia and D
Since the two data lines Dia and Dib are electrically connected to each other, the same image signal is supplied to these two data lines Dia and Dib.
Then, in the first field, the gate line Gj with the subscript a
a, Gj + 1a,... are supplied with a scanning signal to activate these gate lines. In the second field, a scanning signal is supplied to gate lines Gjb, Gj + 1b,. Therefore, in the first field, the gate lines Gja, Gj
+ 1a,..., And an image signal is supplied from each data line to the dots connected thereto.
The image signals are supplied from the respective data lines to the dots connected to the gate lines Gjb, Gj + 1b,.

In this embodiment, although the number of gate lines is doubled as compared with the structure of a conventional general active matrix substrate, the number of data lines at a portion connected to a data driver is reduced by half, resulting in high cost. Since the number of data drivers can be reduced, the cost of the entire device can be reduced. In addition, since the TFTs 1 on the active matrix substrate are arranged in parallel rather than in point symmetry, even if the alignment of the drain layer with respect to the gate layer is shifted, all TFTs in the substrate are displaced.
It shifts in the same direction at T1. As a result, the gate-drain parasitic capacitance becomes equal between the TFTs, and the offset voltage becomes uniform in the substrate, so that the occurrence of flicker that degrades the display quality can be suppressed.

As for the connection between the data lines Dia and Dib, only one point on the side connected to the data driver may be functionally connected for the purpose of reducing the number of data lines connected to the data driver. However, in the case of the present embodiment, two adjacent data lines Dia, D
ib were interconnected at both ends of these data lines. With this configuration, even if one of the two data lines Dia and Dib is disconnected, the image signal is supplied to the disconnected data line through the normal data line. That is, even if one of the data lines is disconnected, the supply of the image signal is not interrupted, and the data line can be prevented from becoming a line defect. That is, according to this structure, a redundant structure can be provided for disconnection defects, and the yield can be improved.

Further, in the configuration of this embodiment, the gate lines Gja, Gjb,... For controlling the TFT 1 of the adjacent dot cross the center of one dot, but the region where the gate line crosses is the accumulation area. Since it can be used as the capacitor Cs, the structure does not lower the aperture ratio even when the structure crosses the gate line.

[Second Embodiment] Hereinafter, a second embodiment of the present invention will be described.
Will be described with reference to FIGS. 3 and 4. FIG. FIG. 3 is a diagram showing an equivalent circuit of the active matrix substrate in the liquid crystal display device of the present embodiment, and FIG. 4 is a design layout diagram. In FIG. 3, the illustration of the storage capacitance Cs is omitted for convenience of illustration. As shown in FIGS. 3 and 4, the active matrix substrate of the present embodiment is different from the first embodiment in that three data lines are electrically connected.

Also in this embodiment, each data line Dia, Dib, Dic, Di + 1a, Di + 1 on the substrate is provided.
b, Di + 1c,... on the same side (right side in the figure)
TFT1 is provided on any of the TFTs in the substrate.
1, the positional relationship between the source electrode 2 and the drain electrode 4 is the same. Then, the adjacent data line Di
a, Dib, Dic, Di + 1a, Di + 1b, Di +
1c,... Are connected at both ends by three. Further, the gate electrodes 5 of the respective TFTs 1 corresponding to the three data lines Dia, Dib, Dic connected to each other are connected to different gate lines Gja, Gjb, Gjc,.
As shown in FIG. 4, a pixel electrode of one dot is traversed by two gate lines, that is, a gate line connected to the TFT of the next dot and a gate line connected to the TFT of the next dot. This portion constitutes the storage capacitance Cs.

In this embodiment, the driving is performed by interlacing, but unlike the first embodiment, one frame is constituted by three fields. That is, in the first field, the gate lines Gja, Gj + 1a,.
Becomes active, and an image signal is supplied from each data line to a dot corresponding to the gate line. In the second field, similarly, the gate lines Gjb, Gj + 1 of the subscript b
The image signal is supplied to the dots corresponding to b,..., and in the third field, the gate lines Gjc, Gj + 1 of the suffix c
An image signal is supplied to dots corresponding to c,.

In this embodiment, the number of data lines Di, Di + 1,... At the connection portion with the data driver is 1 / compared to the structure of a conventional general active matrix substrate.
3 and the number of expensive data drivers can be reduced. Then, similarly to the first embodiment, it is possible to suppress the occurrence of flicker due to the alignment accuracy during the manufacturing process. In addition, this structure also has a redundant structure against disconnection defects, and can improve the yield. Further, a region where two gate lines cross the center of one dot becomes the storage capacitor Cs, and the aperture ratio does not decrease.

[Third Embodiment] Hereinafter, a third embodiment of the present invention will be described.
The embodiment will be described with reference to FIG. FIG. 5 is a diagram showing an equivalent circuit of the active matrix substrate in the liquid crystal display device of the present embodiment. In FIG. 5,
For convenience of illustration, the description of the storage capacity Cs is omitted. As shown in FIG. 5, in the active matrix substrate of the present embodiment, each data line Dia, Di + 1a,
The TFT 1 is provided on the same side (right side in the figure) with respect to Dib, Di + 1b,.
In FT1, the positional relationship between the source electrode and the drain electrode is the same. Every other data line Dia and Dib, Di + 1a and Di + 1b,... Are connected at both ends.

For example, in the case of the first embodiment, since two adjacent data lines are connected, when data line inversion driving is adopted for a pair of data lines at the time of driving, Although the polarity is certainly different between the adjacent data lines of different sets, the same polarity is obtained between the dots corresponding to the mutually connected data lines even though the data line inversion drive is performed. On the other hand, in the case of the present embodiment, every other data line is connected. Therefore, if driving is performed for each pair of data lines Di, Di + 1,. The polarity is inverted between all adjacent dots. As a result, the data line inversion effectively functions, and the crosstalk reduction effect is improved as compared with the first embodiment.

[Fourth Embodiment] Hereinafter, a fourth embodiment of the present invention will be described.
Will be described with reference to FIGS. 6 and 7. FIG. FIG. 6 is a diagram showing an equivalent circuit of the active matrix substrate in the liquid crystal display device of the present embodiment, and FIG. 7 is a design layout diagram. In FIG. 6, for convenience of illustration, the description of the storage capacity Cs is omitted. As shown in FIGS. 6 and 7, in the active matrix substrate of the present embodiment, each data line Dia, Dib, Di on the substrate is provided.
+ 1a, Di + 1b,..., A TFT 1 is provided on the same side (right side in the figure), and two adjacent data lines D
ia and Dib, Di + 1a and Di + 1b,... are mutually connected. The gate electrodes 5 of the respective TFTs 1 corresponding to the pair of data lines Di connected to each other are connected to different gate lines Gja, Gjb,. However, as in the first embodiment, the gate line Gj
are not arranged at equal intervals, and the gate line with the subscript b, for example, the gate line Gjb is the gate line Gj + 1 of the next stage.
a. As a result, for example, when attention is paid to the upper left dot A and the right adjacent dot B in FIG.
In the figure, the dot B is on a line symmetrical position such as above dot A in the figure and below dot B in the figure for dot B on the right.

That is, in the case of the present embodiment, the TFTs 1 of each dot are not in the positional relationship of parallel movement as in the first to third embodiments, but are alternately arranged by the adjacent dots along the gate line. In a line-symmetric position. However, even in the case of this embodiment, one TFT
In 1, the positional relationship between the source electrode 2 and the drain electrode 4 with respect to the gate electrode 5 is the same for all the TFTs 1 on the substrate. With this configuration, even if the alignment of the drain layer with respect to the gate layer is shifted, all the TFTs on the substrate are shifted in the same direction, so that the gate-drain parasitic capacitance becomes equal between the TFTs 1 and the offset voltage is reduced within the substrate. Become uniform. As a result, the occurrence of flicker can be suppressed as in the case of the first to third embodiments.

In the first to third embodiments,
The dots adjacent to each other along the gate line are arranged so as to be shifted by half of the dots, so that a so-called delta arrangement is obtained. On the other hand, in the present embodiment, a stripe type arrangement can be used. Further, in the case of the present embodiment, the gate line for controlling the adjacent TFT does not cross the center of the dot, and the storage capacitor Cs is connected to the pixel electrode at the end of the pixel electrode of the next or previous stage which overlaps the edge of the pixel electrode. It will be composed of lines.

[Fifth Embodiment] The first to fourth embodiments will be described.
In this embodiment, the active matrix substrate has been described, but in this embodiment, the configuration of the entire liquid crystal display device including these active matrix substrates will be described. FIGS. 8A and 8B show a structure of an active matrix liquid crystal display device of the present embodiment.
FIG. 8A is a plan view of the device, and FIG.
FIG. 2 is a sectional view taken along line II of FIG. In each of these figures, 1
Reference numeral 0 denotes an active matrix substrate, which includes a pixel electrode, TF
TFT consisting of T, storage capacitor, data line and gate line
A matrix section 13 is formed. Note that this TFT
The matrix section 13 may have the same configuration as that described in the first to fourth embodiments. Therefore, the description here is omitted. Reference numeral 20 denotes a counter substrate on which a common electrode facing each pixel electrode is formed. The active matrix substrate 10 and the counter substrate 20 face each other with a certain gap therebetween, and a liquid crystal is sealed in the gap. Also, 3
Reference numerals 0 and 30 denote gate drivers, reference numerals 40, 40,... Denote data drivers, each having 240 output terminals.

This active matrix type liquid crystal display device has 1920 pixels in the column direction and 48 pixels in the row direction.
This is a VGA-compatible liquid crystal display panel which is 0. Therefore, when the active matrix substrate according to the first embodiment is employed, the TFT matrix section 13 has 1920 data lines and 960 gate lines. However,
Since the data lines are connected two by two at the end of the TFT matrix section 13, the number of connections to the data drivers 40, 40,... Is 960. To connect with these 960 data lines, four data drivers 40 are externally attached to the TFT substrate 10. On the other hand, the gate line is 96
Since there are 0 gate drivers, four gate drivers 30 would normally be required.
By providing the demultiplexer unit 14 on the substrate 10, the number of the gate drivers 30 is reduced to half, that is, two. The demultiplexer unit 14 has a TFT
And signal wiring.

FIG. 9 shows a circuit configuration of the demultiplexer section 14. As shown in FIG. 9, the demultiplexer unit 14 includes an inverter 120 and 480 demultiplexers DMPX1 to DMPX480. Each demultiplexer has four transfer gates 121 to 124 each formed by a TFT. Each gate of the transfer gates 121 and 124 has
A switching signal Vselect is supplied from a control circuit (not shown). Also, transfer gates 122 and 12
A signal obtained by inverting the switching signal Vselect by the inverter 120 is supplied to each of the gates 3.

Next, the operation of this embodiment will be described. In each field period, the demultiplexer DMPX1
8 (A) to each input terminal of the DMPX480.
480 output signals SR1 to SR480 obtained from the two gate drivers 30 in (B) are sequentially supplied. Each time the field cycle switches, the switching signal V
The level of select is inverted. As a result, the following operation is performed in the demultiplexer unit 14. In the following example, each of the transfer gates 121 to 124 is n
It is assumed that the TFT is constituted by a channel TFT.

First, for example, assuming that the switching signal Vselect goes high in the odd field period, the transfer gates 121 and 124 are turned on and the transfer gates 122 and 123 are turned off in each of the demultiplexers DMPX1 to DMPX480. Therefore, output signals SR1 to SR1 sequentially output from the gate driver in the odd field period are set.
SR480 includes demultiplexers DMPX1 to DMPX.
480 via each transfer gate 121 of 480
It is sequentially applied to the first gate lines G1a to G480a. During this time, the low-level reference voltage Vg-low is applied to the second gate lines G1b to G480b via the transfer gates 124 of the demultiplexers DMPX1 to DMPX480. Accordingly, during this time, all TFTs connected to the second gate line in the TFT matrix section 13 are turned off.

Next, the period is switched to the even field period,
Assuming that each switching signal Vselect is at a low level, in each of the demultiplexers DMPX1 to DMPX480, the transfer gates 122 and 123 are turned on, and the transfer gates 121 and 124 are turned off. Therefore, output signals SR1 to SR1 sequentially output from the gate driver in this even field period are set.
SR480 includes demultiplexers DMPX1 to DMPX.
480 are sequentially applied to the second gate lines G1b to G480b through the transfer gates 123. During this time, the low-level reference voltage V is applied to the first gate lines G1a to G480a via the transfer gates 122 of the demultiplexers DMPX1 to DMPX480.
g-low is applied.

As described above, when the demultiplexer unit 14 is provided, the supply destination of the output signal of the gate driver is, for example, the first gate line in the odd field period and the second gate line in the even field period. Since interlaced driving is performed to switch between each field period, the number of gate drivers can be reduced by half.

Sixth Embodiment FIGS. 10A and 10B show a configuration of an active matrix type liquid crystal display device of the present embodiment, and FIG. 10A shows a plan view of the device. FIG. 10B is a sectional view taken along line II-II of FIG. In the fifth embodiment, the number of the gate drivers 30 is reduced by half by forming the demultiplexer unit 14 on the TFT substrate 10. In the present embodiment, a shift register unit 15 is formed on the TFT substrate 10 instead of the demultiplexer unit 14,
No external gate driver 30 is required.

The circuit configuration of the shift register section 15 is shown in FIG.
Shown in As shown in FIG.
Is formed by cascading 480 register units REG1 to REG480. These register units each include a first flip-flop including a transfer gate 131A, an inverter 132A, a transfer gate 133A, and an inverter 134A, and a second flip-flop including a transfer gate 131B, an inverter 132B, a transfer gate 133B, and an inverter 134B. It consists of.
The output terminal of the first flip-flop of each of the register units REG1 to REG480 (that is, the output terminal of the inverter 134A) is connected to the first gate line G of the TFT matrix unit 13.
1a to G480a. On the other hand, the output terminal of the second flip-flop of each of the register units REG1 to REG480 (that is, the output terminal of the inverter 134B)
Are the second gate lines G1b to
G480b.

Next, the operation of this embodiment will be described. The shift register unit 15 is supplied with two-phase clocks CK1 and CK2. Of these, the first phase clock CK1 is supplied to the transfer gate 13 of each register section.
1A and 131B and the second phase clock CK
2 is supplied to the transfer gates 133A and 133B of each register section.

In the odd-numbered field period, the start pulse SPA is supplied to the first flip-flop of the first-stage register unit REG1 at the start time.
Therefore, in the odd-numbered field period, the start pulse SPA sequentially shifts between the first flip-flops of the cascade-connected register units. As a result, a gate voltage corresponding to the start pulse SPA is sequentially output from the output terminal of the first flip-flop of each register unit (that is, the output terminal of the inverter 134A of each register unit), and the first gate lines G1a to G480a are output. Are sequentially applied. Note that in the odd field period, a shift operation is performed between the second flip-flops of each register unit, but a low-level signal is supplied to the second flip-flop of the first-stage register unit REG1. Therefore, in the odd field period, the second gate lines G1b to G1b
G480b is fixed at a low level.

Next, in the even field period, the start pulse SPB is supplied to the second flip-flop of the register unit REG1 of the first stage at the start time.
For this reason, in the even field period, the start pulse SPB is sequentially shifted between the second flip-flops of each register section. As a result, a gate voltage corresponding to the start pulse SPB is sequentially output from the output terminal of the second flip-flop of each register unit (that is, the output terminal of the inverter 134B of each register unit), and the second gate line G
1b to G480b. Note that in the even-numbered field period, a shift operation is performed between the first flip-flops of the respective register units. However, since a low-level signal is supplied to the first flip-flop of the first-stage register unit REG1, First gate lines G1a to G480
a is fixed to a low level.

As described above, according to the present embodiment, TF
By the shift register unit 15 formed on the T substrate 10,
Since the first and second gate lines of the TFT matrix section 13 are interlaced, there is no need to provide an external gate driver, the number of components can be reduced, and the device can be reduced in size and cost.

It should be noted that instead of providing the shift register unit 15 having the above configuration, a 480-stage shift register and the demultiplexer unit 14 in the fifth embodiment are used.
May be formed on the TFT substrate 10. In this case, the same effect as in the sixth embodiment can be obtained.

The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, in the above embodiment, the driving method has been described as the interlace driving, but the subscript a is added to a half of the 1H period.
The non-interlace drive in which the gate line of the subscript "b" is scanned and the gate line of the subscript "b" is scanned in the remaining half period can be adopted. Further, in the first embodiment, the storage capacitance is constituted only by the pixel electrode and the gate line crossing the center thereof. However, the pixel electrode is further extended so as to overlap the next-stage gate line, and this portion is further extended. It may be added as a storage capacity. In the above embodiment, an example in which two or three data lines are electrically connected has been described, but the number of data lines to be connected is not limited to this. However, it is desirable that the number of data lines to be connected is limited to about three from the relation with display quality and the like.

[0049]

As described in detail above, according to the present invention, the number of data drivers can be reduced by connecting a plurality of data lines by a predetermined number, as compared with the prior art.
As a result, costs can be reduced by reducing the number of data drivers, and at the same time, by devising the arrangement of TFTs in each dot, it is possible to suppress the occurrence of flicker due to process accuracy, particularly alignment accuracy of the exposure machine.

[Brief description of the drawings]

FIG. 1 is a diagram showing an equivalent circuit of a matrix substrate according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a layout of a matrix substrate.

FIG. 3 is a diagram showing an equivalent circuit of a matrix substrate according to a second embodiment of the present invention.

FIG. 4 is a plan view showing a layout of the matrix substrate.

FIG. 5 is a diagram showing an equivalent circuit of a matrix substrate according to a third embodiment of the present invention.

FIG. 6 is a diagram illustrating an equivalent circuit of a matrix substrate according to a fourth embodiment of the present invention.

FIG. 7 is a plan view showing a layout of the matrix substrate.

FIG. 8 is a diagram showing a configuration of an active matrix liquid crystal display device according to a fifth embodiment of the present invention.
FIG. 8A is a plan view of the same device, and FIG.
FIG. 2 is a sectional view taken along line I.

FIG. 9 is a circuit diagram showing a configuration of a demultiplexer unit according to the embodiment.

FIGS. 10A and 10B are diagrams showing a configuration of an active matrix type liquid crystal display device according to a sixth embodiment of the present invention. FIG. 10A is a plan view of the device, and FIG.
FIG. 2A is a sectional view taken along line II-II of FIG.

FIG. 11 is a circuit diagram illustrating a configuration of a shift register unit according to the embodiment.

FIG. 12 is a diagram showing an equivalent circuit of a conventional general matrix substrate.

FIG. 13 is a diagram showing an equivalent circuit of a double-scanning-line type matrix substrate.

FIG. 14 is a diagram for explaining a problem of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 TFT 2 Source electrode 3 Pixel electrode 4 Drain electrode 5 Gate electrode Di, Dia, Dib, Dic, ... Data line Gja, Gjb, Gjc, ... Gate line

Claims (5)

[Claims] A plurality of data lines and a plurality of gate lines provided in a matrix on a substrate; a thin film transistor and a pixel electrode connected to the thin film transistor are provided on the same side for each of the data lines; A drain electrode forming the thin film transistor connected to an electrode extends from the gate line and is provided on the same side as the gate electrode forming the thin film transistor, and the data lines are electrically connected to each other by predetermined numbers. A substrate for an active matrix type liquid crystal display device, wherein the plurality of gate lines are provided so that the thin film transistors connected to each data line are controlled by different gate lines. 2. The active matrix type liquid crystal display device according to claim 1, wherein the predetermined number of electrically connected data lines are connected to each other at least at both ends of the data lines. substrate. 3. The substrate for an active matrix type liquid crystal display device according to claim 1, wherein said plurality of data lines are electrically connected to said predetermined number every odd number. 4. The method according to claim 1, wherein one or more and a predetermined number or less of gate lines are formed on each of the pixel electrodes so as to traverse the pixel electrodes and form storage capacitors in cooperation with the pixel electrodes. The substrate for an active matrix type liquid crystal display device according to claim 1. 5. An active matrix type liquid crystal display device in which liquid crystal is sandwiched between a pair of substrates arranged opposite to each other, wherein one substrate of the pair of substrates is the substrate according to any one of claims 1 to 4. An active matrix liquid crystal display device, comprising: