KR100350333B1 - Active Matrix Board and Color Liquid Crystal Display - Google Patents

Abstract

Pixel regions P11, P12, and P13 having pixel electrodes 12 corresponding to red, green, and blue are arranged periodically in the X direction with these three colors as one unit, and are paired with the hole means in the Y direction. The delta arrays are constructed by placing them half a cycle away from the vehicle. When only the pixel electrodes 12 of the pixel regions P12, P22, and P32 corresponding to the same color are connected to the same source line S2, the pixel regions P12, P22, and P32 are connected to the pixel electrode 12 source line S2. ) Is arranged left and right alternately. Between the pixel regions P11, P12, P13, ... in the X direction, the TFT 11, the pixel electrode 12, the first electrode portion C1 and the second electrode portion (of the storage capacitor CS) ( The relative formation position of C2) is the same. The relative formation of the TFT 11 and the pixel electrode 12 between each pixel region P12, P22, P32, ... parallel to the Y direction along the source lines S1, S2, S3, ... The positions are reversed left and right for each stage, but the relative positional relationship between the first electrode portion C1 and the second electrode portion C2 of the storage capacitor CS is the same.

Description

Active Matrix Substrate and Color Liquid Crystal Display

The basic structure of the color liquid crystal display device using the said active matrix substrate is shown in FIG. 1, gate lines G0, G1, G2, ... extending in the X direction, and source lines S0, S1, S2, ... extending in the Y direction, on the surface of the substrate 10. In FIG. And the plurality of pixel electrodes 12 arranged at positions corresponding to the intersections of these source lines S1, S2, S3, ..., and gate lines G1, G2, G3, ... A thin film transistor (hereinafter referred to as TFT) 11 connected to each pixel electrode is formed.

In the selection period, i.e., the period in which the TFT 11 is ON due to signals from the gate lines G1, G2, G3, ..., the source lines S1, S2, S3, ...) The image signal supplied from the recording medium is recorded in the liquid crystal capacitor portion (CLC) composed of the common electrode 26 formed on the opposing substrate 20, the pixel electrode 12, and the liquid crystal 30 enclosed in the gaps in the selection period. do. On the other hand, in the non-selection period, that is, the period in which the TFT 11 is in the OFF state, the image signals recorded in the liquid crystal capacitor CLC in the selection period are held.

Here, in order to perform high quality display, it is required that the accumulation characteristic in the non-selection period is good. To this end, it is effective to place the storage capacitor CS electrically in parallel with the liquid crystal capacitor portion CLC. The storage capacitor CS has a structure in which the storage capacitor CS is disposed between the gate line and the pixel electrode 12 at the front end, or between the storage capacitor line (not shown in FIG. 1) and the pixel electrode 12 formed separately. The structure etc. which have accumulate | stored capacitance CS are proposed.

The pixel regions P11, P12, P13, ... are constituted by the storage capacitor CS, the pixel electrode 12, the TFT 11, and other additional wirings configured in this way. Here, no pixel region is formed between the pixel region P11 and the pixel region P31, but a blue pixel region is formed in the region or a dummy pixel region is formed. There is also.

The color filter 21 is formed in the counter substrate 20. The color filter 21 generally consists of a red filter R, a green filter C, and a blue filter B. FIG. These red filter R, green filter G, and blue filter B are arrange | positioned repeatedly in a display screen by making them one unit. The arrangement of the color filters 21 includes a stripe arrangement, a mosaic arrangement, or a delta arrangement. 12 shows an example of the color arrangement pattern of the delta arrangement, and FIG. 13 shows an example of the color arrangement pattern of the mosaic arrangement. In such a delta array or a mosaic array, since each color element is uniformly distributed in the display screen, there is an advantage that a smoother image can be displayed than the stripe array.

As the liquid crystal display device using the delta arrangement, there is disclosed in the Japanese Patent Application Laid-Open No. 3-64046, and the liquid crystal display device using the mosaic arrangement is disclosed in the above-mentioned publications 8C-8F. .

As shown in FIG. 14, three pixel regions P21, P22, and P23 corresponding to the red filter R, the green filter G, and the blue filter B are used for the liquid crystal display device described in this publication. It is arrange | positioned periodically in the X direction by 1 unit. However, the pixel areas P21, P22 and P23 in the even-numbered pixel columns are the same as the pixel areas P11, P12 and P13 or the pixel areas P31, P32 and P33 in the pixel columns of the hole means. It is arrange | positioned by the distance corresponded to 1/2 period of a unit. Therefore, the center positions of the pixel areas P11, P12, P13, ... are moved left and right between the odd-numbered pixel columns and the even-numbered pixel columns by a distance corresponding to 1.5 pixel pitches.

Since all the pixel regions have the same basic configuration, the pixel region P21 will be described as an example. In the pixel region P21, the source region 111 of the TFT 11 is connected to the source line S1, the gate electrode 113 is connected to the gate line G2, and the drain region 112 is the pixel electrode 12. )

The pixel region P21 extends in the Y direction from the first electrode portion C1 electrically connected to the drain region 112 and the pixel electrode 12 of the TFT 11 and the front gate line G1. The second electrode portion C2 having a structure is formed. As the material of the first electrode portion C1, a doped silicon film is usually used. As described later, the first electrode portion C1 and the second electrode portion C2 are disposed to face each other with a dielectric film interposed therebetween. In this way, the storage capacitor CS is formed between the pixel electrode 12 and the gate line G1 at the front end.

In addition, each source line S1, S2, S3, ... is bent in a crank shape in the Y direction, and a complicated color switching circuit for supplying a plurality of color signals to the same source line at an appropriate timing is not required. Therefore, only the pixel electrode 12 in the pixel region corresponding to the same color is connected to the same source line via the TFT 11. Therefore, pixel regions corresponding to the same color are arranged alternately on both sides of the source line in the same source line. For example, in the case of the source line S2, pixel regions P12, P22, P32, ... corresponding to green are alternately arranged on both sides of the source line S2. Inevitably, the positional relationship between the TFT 11 and the source line is also reversed for each stage.

As a result, the TFTs 11, the pixel electrodes 12, and the storage capacitors for the pixel regions P11, P12, P13, ... in the X direction along the gate lines G1, G2, G3, ... While the relative positions of the CS (the first electrode portion C1 and the second electrode portion C2) are the same, the pixel regions P12, P22, P32, ... in the Y direction along the source line C2 The relative formation positions of the TFT 11 and the pixel electrode 12 with respect to each other have a symmetrical relationship for each stage. For example, when the pixel areas P11, P12, P13, ... connected to the gate line G1 and the pixel areas P21, P22, P23, ... connected to the gate line G2 are compared, the TFT ( 111, the relative positional relationship between the pixel electrode 12 and the storage capacitor CS is horizontally symmetrical.

A method of manufacturing an active matrix substrate having such a configuration will be briefly described with reference to FIG. 15A to 15C are sectional views taken along line II ′ and II-II ′ of FIG. 14, respectively.

In FIG. 15A, first, a polycrystalline silicon thin film is formed on the substrate 10, and then patterned according to photolithography technology, thereby forming the active region of the TFT 11 and the first electrode portion C1 of the storage capacitor CS. The polycrystalline silicon thin film 110 is formed.

Next, the gate oxide film 114 and the dielectric film C3 of the storage capacitor CS are formed by thermal oxidation of the polycrystalline silicon film 110. Next, in order to form the storage capacitor CS, impurities are selectively doped only with respect to the polycrystalline silicon film 110 to form the first electrode portion C1 of the storage capacitor CS.

Subsequently, the gate electrode 113 and the second electrode C2 of the storage capacitor CS are formed of a polycrystalline silicon thin film doped by photolithography technique. In this step, the gate electrode 113 and the gate line G2 are electrically connected to each other in the pixel region P21, and the second electrode part C2 and the gate line G1 of the previous stage are electrically connected.

Next, the source region 111 and the drain region 112 are formed by implanting ions using the gate electrode 113 as a mask. Next, after the interlayer insulating film 115 is formed, a through-hole is formed therein.

Thereafter, the source terminal 118 and the drain terminal 119 are electrically connected to the source region 111 and the drain region 112, respectively. Here, the source terminal 118 is electrically connected to the source line S1 and the drain terminal 119 is electrically connected to the pixel electrode 12.

In this manner, the TFT 11 and the storage capacitor CS are formed in the pixel region P21, and the storage capacitor CS is formed in the pixel regions P11, P12, and P22 as shown in Figs. 15B and 15C.

However, in the case of using the pattern shown in FIG. 14, when forming each component part on the board | substrate 10 by photolithography technique, if it is not aligned along a horizontal direction (X direction), for example, a source line S2. ), The structural parameters change once in each pixel area P12, P22, P32, ... in the Y direction.

That is, in FIG. 16, the formation pattern A1 and gate lines G1, G2, G3,. Of the polycrystalline silicon film on the lower layer side for forming the TFT 11 and the first electrode portion C1 of the storage capacitor CS. ..), the overlapped portion of the formation pattern A2 of the polycrystalline silicon film on the upper side for forming the gate electrode 113 and the second electrode portion C2 of the CS of the storage capacitor is used as the opposing portion C0 of the storage capacitor CS. When patterned diagonally, if not aligned between the formation pattern A1 of the polycrystalline silicon film on the lower side and the formation pattern A2 of the polycrystalline silicon film on the upper side, by the gate lines G1, G3, ... Accumulation capacity CS (odd) of selected odd-numbered pixel areas P11, P12, ..., P31, P32, ... (these storage capacitors are connected to gate lines G0, G2, ...) Storage capacitors CS (even) of the pixel regions P21, P22, ... selected by the gate lines G2, G4, ... (the capacitors of these holding capacitors are the gate lines G1, Contacting G3, ...) This may be) the area of the facing portions in a diagonal pattern C0 between the fluctuates.

In Fig. 16, since the ideal case aligned in the left-right direction is shown, the capacitance value of the storage capacitance CS (ODD (odd)) and the capacitance value of the storage capacitance CS (EVEN (even)) are the same.

However, when not aligned in the left-right direction, the capacitance value of the storage capacitance CS (odd) and the capacitance value of the storage capacitance CS (even) have different values. For example, when the formation pattern A1 of the polycrystalline silicon thin film on the lower side is shifted from the formation pattern A2 of the polycrystalline silicon thin film on the upper side in the direction of the arrow R, the capacitance value of the storage capacitance CS (odd) increases while The value of the dose CS (even) decreases.

As a result, when the N type TFT is used, the optimum LC common voltage of the odd-numbered gate lines G1, G3, ... is higher than the optimal LC common voltage of the even-numbered gate lines G2, ... As a result, a difference occurs in the optimum LC common voltage and flicker occurs at each gate line.

In order to solve such a problem, an object of the present invention is to improve the formation pattern of each electrode portion constituting the storage capacitor, so that the flicker even when the pixel electrodes of each pixel region are alternately connected to the same source line on the left and right sides at each stage. An active matrix substrate is provided.

Further, another object of the present invention is to provide a high quality color liquid crystal display device using the active matrix substrate configured as described above.

<Start of invention>

In order to solve such a problem, according to the first aspect of the present invention,

A plurality of gate lines extending in the first direction,

A plurality of source lines extending in a second direction crossing the first direction,

A plurality of thin film transistors including a source region electrically connected to one of the source lines;

A plurality of pixel electrodes electrically connected to one drain region of the thin film transistors, respectively;

A plurality of storage capacitors disposed along a second direction, the first electrode electrically connected to one of the pixel electrodes and a second electrode electrically connected to the other of the gate lines adjacent to one of the gate lines. Including them,

The storage capacitors adjacent to each other in a second direction are located along the same side of the pixel electrodes, and the storage capacitors are provided so as to overlap the source line.

According to a second aspect of the invention,

A plurality of gate lines extending in the first direction,

A plurality of source lines extending in a second direction crossing the first direction,

A plurality of thin film transistors including a source region electrically connected to one of the source lines;

A plurality of pixel electrodes electrically connected to drains of one of the thin film transistors, respectively;

A first electrode electrically connected to one of the pixel electrodes and a second electrode electrically connected to the other of the gate lines adjacent to one of the gate lines, the second electrode being disposed in a second direction or the source; A plurality of accumulation capacities arranged along the lines,

A second set of color filters having a unit period periodically arranged in a first direction, the second set of color filters adjacent to the first color filter string in a second direction, and periodically arranged in a first direction And a first color filter string coupled to a corresponding electrode of the pixel electrodes and having one of three colors, the first color filter string including one unit period set of a color filter string that determines a unit period.

Storage capacitors adjacent to each other in a second direction are located along the same side of the pixel electrodes, and the storage capacitors are disposed to overlap the source line.

The first color filter string and the second filter string are separated from each other in the first direction by a distance corresponding to a half unit period,

Each of the source lines is provided with a color liquid crystal display device connected to one of the thin film transistors having only pixel electrodes corresponding to a color filter having a selected one of the three colors.

Among the plurality of pixel electrodes electrically connected to the same source line via the thin film transistor, pixel electrodes adjacent to each other in the Y direction are disposed opposite to each other along the same source line, and electrically connected to adjacent storage capacitor lines. The connected storage capacitor has the same relative forming position of the first electrode portion with respect to the second electrode portion.

In the active matrix substrate configured as described above, the relative formation positions of the first electrode portions with respect to the second electrode portions are the same between the storage capacitors adjacent to each other in the Y direction, so that each component portion is formed by using photolithography technology. Even when not aligned, a difference does not occur in the opposing area between the first electrode portion and the second electrode portion of the storage capacitors, and the capacitance value of the storage capacitances can be made uniform.

Therefore, by using the active matrix substrate configured as described above in the liquid crystal display device, it is possible to prevent the occurrence of flicker in each of the gate lines caused by the difference in the storage capacitance value between adjacent storage capacitors.

According to the present invention, in order to configure a color liquid crystal display device in a delta array using the active matrix substrate, three color filters of red, green, and blue colors formed corresponding to the pixel electrodes are used to convert the three colors into one unit. The first color filter string periodically arranged in the X direction and the second color filter string adjacent to the Y direction in the Y direction, and the second color filter train periodically arranged in the X direction with the above three colors as one unit are placed. . Then, only pixel electrodes corresponding to the same color in which the first color filter string and the second color filter string are disposed apart from each other in the X direction by a distance corresponding to one-half cycle of the one unit period are connected to the same source line. .

According to the present invention, in order to configure a color liquid crystal display device according to a mosaic arrangement using the active matrix substrate, the first color filter string and the second color filter string different from those in the delta arrangement are one of the above one unit period. Only pixel electrodes that are disposed apart from each other in the X direction by a distance corresponding to a / 3 period, and simultaneously correspond to the color filters of the same color, are connected to the same source line.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element structure of an active matrix substrate used in a liquid crystal display device, in particular, a structure of a storage capacitor.

The present invention also relates to a structure of a color liquid crystal display device using the active matrix substrate.

1 is a diagram showing a basic structure of a color liquid crystal display device using an active matrix substrate.

FIG. 2 is a plan view showing a formation pattern of respective component parts of an active matrix substrate used in the liquid crystal display device according to the first embodiment. FIG.

3 is a schematic view of the formation pattern shown in FIG.

4A is a cross-sectional view of FIG. 2 taken along the line IV-IV ', FIG. 4B is a cross-sectional view of FIG. 2 taken along the line V-V', and FIG. 4C is a cross-sectional view of FIG. 2 taken along the line VI-VI '.

FIG. 5 is a plan view schematically showing a formation pattern of each silicon film in the active matrix substrate shown in FIG. 2 forming two electrode portions of the storage capacitor on the substrate surface.

6 is a plan view showing a formation pattern of respective constituent parts of an active matrix substrate used in the liquid crystal display device according to the second embodiment.

7 is a plan view schematically showing a formation pattern of each silicon film constituting two electrode portions of a storage capacitor on the substrate surface in the active matrix substrate shown in FIG.

8 is a cross-sectional view of a reverse-stagger-type TFT used as a TFT of an active matrix substrate used in the liquid crystal display device according to the third embodiment.

9 is a plan view showing a formation pattern of respective constituent parts of an active matrix substrate used in the liquid crystal display device according to the third embodiment.

FIG. 10 is a plan view schematically showing a formation pattern of a tantalum film and an ITO film forming two electrode portions of a storage capacitor on the substrate surface in the active matrix substrate shown in FIG.

11 is a plan view showing a formation pattern of respective constituent parts of an active matrix substrate used in the liquid crystal display device according to the fourth embodiment.

12 illustrates a color arrangement pattern according to a delta arrangement.

13 is a diagram showing an example of a color arrangement pattern according to a mosaic arrangement.

Fig. 14 is a plan view showing a formation pattern of each component part of an active matrix substrate used in a conventional liquid crystal display device.

FIG. 15A is a cross sectional view of FIG. 14 taken along line II ′, FIG. 15B is a cross sectional view of FIG. 14 taken along line II-II ′, FIG. 15C is a cross sectional view of FIG. 14 taken along line III-III ′.

FIG. 16 is a plan view schematically showing a formation pattern of each silicon film in the active matrix substrate shown in FIG. 14, forming two electrode portions of the storage capacitance on the substrate surface.

Best Mode for Carrying Out the Invention

First embodiment

1 shows the basic structure of a color liquid crystal display device using an active matrix substrate. 2 is a plan view showing a formation pattern of respective constituent parts of an active matrix substrate used in the liquid crystal display of this embodiment. Since the active matrix substrate of this embodiment is similar to the conventional active matrix substrate except for the formation pattern of each component in the pixel region, the other parts are similar, so that the detailed description of the components having the common functions is the same for each of the components. Omitted by adding a sign.

In FIG. 1, the color liquid crystal display of this embodiment extends in the X direction and gate lines G0, G1, G2, ... extending in the X direction on the surface of the transparent substrate 10 constituting the active matrix substrate. The pixel regions P11, P12, P13, ... correspond to the intersections with the source lines S1, S2, S3, .... In each pixel region P11, P12, P13, ..., the transparent pixel electrode 12 is connected to the source lines S1, S2, S3, ... via the TFT 11. The source lines S1, S2, S3, ... are provided during the period (selection period) in which the TFT 11 is turned on by signals from the gate lines G1, G2, G3, .... The resulting image signals are recorded in the liquid crystal capacitor section CLC. On the other hand, in the period in which the TFT 11 is in an off state (non-selection period), image signals recorded in the liquid crystal capacitor CLC are held in the selection period.

Here, in order to perform high quality display, it is required that the accumulation characteristic in the non-selection period is good. Therefore, the storage capacitor CS is provided between the front gate line and the pixel electrode 12 among the gate lines G0, G1, G2, .... Of the gate lines G0, G1, G2, ..., the gate line G0 is substantially a dedicated capacitance line. This is because the gate electrode of the TFT 11 is not connected to the gate line G0.

In addition, polarizing plates 41 and 42 are disposed outside the substrate 10 and the counter substrate 20.

The color filter 21 is formed in the counter substrate 20. The color filter 21 generally consists of a red filter R, a green filter G, and a blue filter B. The pixel electrodes 12 of the pixel areas P11, P12, P13, ... are arranged corresponding to the color filters 21 constituting these three colors, respectively. The arrangement of the color filters 21 in this embodiment is a delta arrangement (Fig. 12). That is, in the opposing substrate 20, the first color filter array F1 in which three color filters of red (R), green (G), and blue (B) are periodically arranged in the X direction using these three colors as one unit (Color filter string of the hole means) and a second color filter string F2 (column color filter string) adjacent to the color filter string in the Y direction and periodically arranged in the X direction with the above three colors as one unit. The first color filter string F1 and the second color filter string F2 are spaced apart in the X direction by a distance corresponding to one-half cycle of the one unit cycle. In the delta arrangement configured as described above, each color element is uniformly distributed in the screen, and therefore, it is particularly suitable for displaying an image requiring fine image quality.

Corresponding to the arrangement of the color filters thus configured, three pixel regions P11, P12, corresponding to the red filter R, the green filter G, and the blue filter B, as shown in FIGS. 2 and 3, on the active matrix substrate. P13) is periodically arranged in the X direction using it as a unit, whereby a first pixel column (pixel column of hole means) is formed.

Further, in the Y direction, pixel regions P21, P22, and P23 corresponding to the same unit in the second pixel column (the pair of pixel columns) adjacent to the first pixel column are 1 from the first pixel column in the X direction. It is placed at a distance equivalent to a period of / 2. Further, in the pixel column (the pixel column of the hole means) adjacent to the second pixel column in the Y direction, the pixel areas P31, P32, and P33 corresponding to the same unit are opposite to the pixel areas P21, P22, and P23. It is arranged at a distance corresponding to a half cycle in the direction. Therefore, the pixel column including the pixel areas P31, P32, and P33 is in a state in which the pixel column including the pixel areas P11, P12, and P13 is moved in the Y direction as it is. As a result, the center position of each pixel area P11, P12, P13, ... is shifted left and right by one step by 1.5 pixel pitch in a Y direction.

Each source line S1, S2, S3, ... is bent to extend in the Y direction. Only pixels corresponding to the same color are connected to the same source line. Therefore, it is sufficient for the same source line to supply only signals for displaying any one of red, green, and blue. In addition, in the present embodiment, a source line extending in the Y direction and being bent may be used, and a source line extending in the Y direction and being curved in the Y direction may be used.

Since all the pixel areas have the same basic structure, the pixel area P21 will be described as an example. As can be seen in FIG. 2, the gate electrode 113 of the TFT 11 is connected to the gate line G2, the source region 111 is connected to the source line S1, and the drain region 112 is a pixel. It is connected to the electrode 12. The pixel region P21 has a first electrode portion C1 to which the drain region 112 and the pixel region 12 are electrically connected, and the first electrode portion C1 is formed of a doped silicon film. Further, the pixel region P21 has a second electrode portion C2 extending in the Y direction from the gate line G1 of the front end.

The first electrode portion C1 and the second electrode portion C2 are opposed to each other via the dielectric film, and the storage capacitor CS is formed between the gate line G2 of the front end and the pixel electrode 12.

On the active matrix substrate configured as described above, only the pixel electrodes 12 of the pixel region corresponding to the same color of each color filter 21 according to the delta arrangement among the pixel regions P11, P12, P13,... (S1, S2, S3, ...). Therefore, the pixel electrodes 12 of the pixel regions P12, P22, P32, ... corresponding to the green G are alternately connected to the same source line S2 in the Y direction. The same applies to the other source lines S1, S3, ....

Here, between the pixel regions P11, P12, P13, ... in the X direction along the gate line G1, the TFT 11, the pixel electrode 12, and the storage capacitor CS (first electrode portion) The relative formation positions of C1 and the second electrode portion C2 are the same. The TFT 11, the pixel electrode 12, and the storage capacitor CS (first electrode portion C1 and also) between the pixel regions P21, P22, P23, ... in the X direction along the gate line G2. The relative formation position of the 2nd electrode part C2) is the same.

Between the pixel regions P12, P22, P32, ... along the source line S2 in the Y direction, the relative formation positions of the TFTs 11 and the pixel electrodes 12 become patterns inverted left and right for each step. have. That is, odd-numbered pixel regions P11, P12, P13, ... connected to the gate line G1, and even-numbered pixel regions P21, P22, P23, ... connected to the gate line G2. ), The formation pattern of the TFT 11 and the pixel electrode 12 is symmetrical.

However, the storage capacitor CS is formed at the same relative position in any pixel region. That is, the relative positions of the storage capacitors CS in the pixel region are the same between the storage capacitors CS adjacent to each other in the Y direction.

Further, the relative positional relationship between the first electrode portion C1 of the storage capacitor CS and the second electrode portion C2 protruding from the gate lines G0, C1, G2, ... at the front end is determined in each pixel region. It is the same as X direction or Y direction among (P12, P22, P32, ...).

For example, the storage capacitor capacitor CS is formed in the region where the adjacent source line S1 passes in the pixel region P12 connected to the gate line G1. Similarly, in the pixel region P32 connected to the gate line G3, the storage capacitor CS is formed in the region through which the adjacent source lines S1 pass. Therefore, in any of the pixel regions P11, P12, ..., P31, P32, ... connected to the gate lines G1, G3, the first electrode portion C1 of the storage capacitor CS drains the TFTs 11. It extends as it is to the left region of the pixel electrode 12 from the connection position with the region 112, and overlaps the second electrode portion C2 protruding from the adjacent gate lines G0 and G2 in the left region. .

In contrast, the storage capacitor CS is formed in the region where the source line S2 to which the pixel region P22 itself is connected passes in the pixel region P22 connected to the gate line 42. Therefore, in any of the pixel regions P21, P22, ... connected to the gate line G2, the first electrode portion C1 of the storage capacitor CS is connected at the connection position with the drain region 112 of the TFT 11. It returns to the source region 111 once, and from the source region 111 to the left region of the pixel electrode 12 similarly to the pixel regions P11, P12, ..., P31, P32, ... of odd stages. It is extending. And it overlaps with the 2nd electrode part G2 which protruded from the adjacent gate line G1 in this left area | region (FIG. 3).

An active matrix substrate manufacturing method having such a configuration will be described with reference to FIG. 4A, B, and C are sectional views taken on line IV-IV ', V-V', and VI-VI ', respectively, in FIG.

In FIG. 4A, first, a polycrystalline silicon thin film 10 for forming the active region of the TFT 11 and the first electrode portion C1 of the storage capacitor CS on the substrate 10 made of quartz glass by photolithography technique. ).

Next, the gate oxide film 114 and the insulating film C3 of the storage capacitor CS are formed by thermal oxidation of the polycrystalline silicon film 110.

Next, the first electrode portion C1 of the storage capacitor CS is formed by selectively doping impurities with only the polycrystalline silicon film 110 for forming the storage capacitor CS.

Subsequently, the gate electrode 113 and the second electrode portion C2 of the storage capacitor CS are formed of a polycrystalline doped silicon thin film by photolithography technique. In this state, the gate electrode 113 is connected to the gate line G2 and the second electrode portion C2 is electrically connected to the adjacent gate line G1 in the pixel region P21.

Next, the source region 111 and the drain region 112 are formed by implanting ions using the gate electrode 113 as a mask. Next, after the interlayer insulating film 115 is formed, a through hole is formed therein.

Thereafter, the source terminal 118 and the drain terminal 119 are electrically connected to the source region 111 and the drain region 112, respectively. Here, the source terminal 118 is electrically connected to the source line S1, and the drain terminal 119 is electrically connected to the pixel electrode 12.

In this manner, the TFT 11 and the storage capacitor CS are formed in the pixel region P21, and the storage capacitor CS is formed in the pixel regions P11, P12, and P22 as shown in Figs.

In such a manufacturing method, even if each component portion is formed on the substrate 10 by photolithography technology, and the pattern mask is not aligned in the left-right direction (X direction), in the present embodiment, each pixel region P11, P12, P13 , ...), the structural parameters do not change from stage to stage. That is, in Fig. 5, the formation pattern A3 and gate lines G1, G2, G3,... Of the polycrystalline silicon film on the lower layer side for forming the TFT 11 and the first electrode portion C1 of the storage capacitor CS are shown. .) The overlapping portion of the gate electrode 113 and the formation pattern A4 of the polycrystalline silicon film on the upper side for forming the second electrode portion C2 of the storage capacitor CS is diagonally opposite to the storage portion CS. As shown, the pixel regions P11, which are connected to the gate lines G1, G3, ... even if they are not aligned in the X direction between the formation pattern A3 of the polycrystalline silicon film and the formation pattern A4 of the polycrystalline silicon film. P12, ..., P31, P32, ...) (capacity in odd-numbered pixel areas) CS (odd) (these storage capacitors are connected to gate lines G0, G2, G3, ...) ) And the storage capacitance CS (even) of the pixel regions P21, P22, ... (the paired pixel regions) connected to the gate lines G2, ... (these storage capacitances are the gate lines G1, G3). , G5, ...) Connected to), the area of the opposing part C0 does not change.

For example, even if the formation pattern A3 of the polycrystalline silicon thin film is slightly separated from the formation pattern A4 of the polycrystalline silicon thin film in the direction of the arrow R, the pixel regions P11, P12, P31, P32, ... In both of the pixel regions P21, P22, ... of the means, the area of the opposing portion C0 between the first electrode portion C1 and the second electrode portion C2 in each storage capacitor CS becomes large. It is only.

That is, if the formation pattern A3 of the polycrystalline silicon thin film is slightly shifted from the formation pattern A4 of the polycrystalline silicon thin film in the direction of the arrow L, the result is the opposite portion C0 of the first electrode C1 and the second electrode C2. ) Only increases the respective storage capacitances CS in both the pixel regions P11, P12, ... P13, P32 at odd-numbered stages and the pixel regions P21, P22, ... at even-numbered stages.

Even if perfect alignment is not made in the up-down direction (Y direction), the area of the opposing portion C0 between the first electrode portion C1 and the second electrode portion C2 in each storage capacitor CS does not change.

Thus, in the active matrix substrate of this embodiment, even if the alignment pattern A3 of the polycrystalline silicon film and the formation pattern A4 of the polycrystalline silicon film is not aligned in the left-right direction (X direction) or the vertical direction (Y direction), Since the capacitance value of each storage capacitor CS is always the same among the pixel regions P11, P12, ..., P21, P22, ..., P31, P32, ..., the odd-numbered gate lines G1, G3 , The optimum LC common voltage of the gate lines G2, ... of even-numbered stages is always the same. Therefore, since the optimum LC common voltage can be set as a whole, flicker in the gate line unit can be prevented.

Further, in the present embodiment, between the pixel regions P11, P12, P13, ... in the Y direction along the source lines S1, S2, S3, the relative of the TFT 11 and the pixel electrode 12 The formation position and shape of the first electrode portion C1 for forming the storage capacitor CS only by inverting the formation position left and right at one end are different. Therefore, the flicker does not occur even when the first electrode portion C1 and the second electrode portion C2 are formed by optimizing the relative positional relationship between the first electrode portion C1 and the second electrode portion C2. It is possible to prevent the occurrence. Therefore, it is particularly advantageous when realizing a high-definition and high-density liquid crystal display device because it is applied even when there are limitations on the formation area and size of each component.

Further, pixel areas P1, P2, ... corresponding to odd-numbered gate lines G1, G3, ..., and pixel areas P21 corresponding to even-numbered gate lines G2, .... , P22, ... are substantially the same in the pattern of the component parts other than the 1st electrode part C1. Thus, even if the alignment on the opposing substrate 20 and the active matrix substrate is not performed, at even ends of the pixel regions P11, P12, ... corresponding to the odd-numbered gate lines G1, G3, ... The difference in the aperture ratio between the pixel regions P21, P22, ... corresponding to the gate lines G2, ... is reduced and an uneven horizontal line can be prevented.

Second embodiment

6 is a plan view showing a formation pattern of components of an active matrix substrate of the liquid crystal display device of the present embodiment. In addition, in the active matrix substrate of the present embodiment, only the portions of the active matrix substrate and the storage capacitor according to the first embodiment differ from each other, and the same reference numerals are given to constituent parts having corresponding functions.

In the first embodiment, the front gate line is used to form the second electrode portion C2 of each storage capacitor CS. In this embodiment, the storage capacitor lines CM1, CM2, CM3, ... ) Is formed to extend in the X direction with the gate lines G1, G2, G3, ..., and the storage capacitor CS uses the storage capacitor lines CM1, CM2, CM3, ... for the second electrode portion. (C2) is comprised.

In the liquid crystal display of the present embodiment, like the first embodiment, three pixel areas P21, P22, and P23 corresponding to red, green, and blue are positioned in the X direction as one unit. In the pixel columns adjacent to each other in the Y direction, the pixel areas P11, P12, and P13 corresponding to one unit and the pixel areas P31, P32, and P33 are similarly spaced apart by one-half period alternately.

Here, each source line S1, S2, S3, ... is bent. In addition, only pixel electrodes of pixel regions corresponding to the same color are connected to the same source line. Therefore, it is sufficient for the same source line to display any of red, green and blue colors.

In addition, each pixel region has the same basic structure, so that when the pixel region P21 is described as an example, the pixel region P21 is formed of a doped silicon film electrically connected to the drain region 112 and the pixel electrode 12. The 1st electrode part 1 is formed and the 2nd electrode part C2 extended in a Y direction is formed in the storage capacitor line CM2. The first electrode portion C1 and the second electrode portion C2 face each other through the dielectric film, and the storage capacitor CS is formed between the pixel electrode 12 and the storage capacitor line CM2 in the pixel region P21. have.

In the active matrix substrate configured as described above, only the pixel electrodes 12 of the pixel regions P11, P12, P13, ... corresponding to the same color of each color filter 21 according to the delta arrangement are connected to the bent source lines. The pixel electrodes 12 of the pixel regions P12, P22, and P32 are connected to the same source line S2 in alternating left and right directions. The same applies to the other source lines S1, S3, ....

Therefore, similarly to the first embodiment, the TFTs 11, the pixel electrodes 12, and the storage capacitors CS (first electrode portion () between the pixel regions P11, P12, P13, ... in the X direction. While the relative formation positions of the C1 and the second electrode portion C2 are the same, the TFTs 11 and the pixel electrodes 12 in the pixel regions P12, P22, P32, ... are in the Y direction. The relative formation position is reversed left and right for each end.

However, the storage capacitor CS is formed at the same relative position in any pixel region. In other words, the relative positions of the storage capacitors CS are the same between the storage capacitors adjacent to each other in the Y direction.

In addition, the relative positions between the first electrode portion C1 of the storage capacitor CS and the second electrode portion C2 protruding from the storage capacitor lines CM1, CM2, ... are adjacent to each other in the Y direction. The same between the storage capacities. That is, the relative position is the same between each pixel area.

The manufacturing method of the active matrix substrate having such a configuration is almost the same as in the first embodiment, and when the gate electrode 113 and the gate lines G1, G2, G3, ... are formed, the storage capacitor lines CM1, Only the point of simultaneously forming CM2, CM3, ...) and the first electrode portion C2 protruding from the lines are different.

Therefore, in Fig. 7, the formation pattern A3 and gate lines G1, G2, G3, .. of the polycrystalline silicon film on the lower layer side for forming the TFT 11 and the first electrode portion C1 of the storage capacitor CS are shown. .), The gate electrode 113, the storage capacitor lines (CM1, CM2, CM3, ...) and the formation pattern A5 of the polycrystalline silicon film on the upper layer side for forming the second electrode portion C2 of the storage capacitor CS. When the overlapped portion is patterned diagonally as the opposite portion C0 of the storage capacitor CS, the arrangement between the formation pattern A3 of the polycrystalline silicon film and the formation pattern A5 of the polycrystalline silicon film is in the left-right direction (X direction). Although not aligned, the area of the opposing portion C0 (capacity value of the storage capacitors CS) patterned with diagonal lines is always pixels P11, P12, ..., P21, P22, .., P31, P32, ... Is the same among). As a result, the second embodiment has an effect similar to that of preventing the occurrence of flicker at each gate line, similar to the effect of the first embodiment.

Third embodiment

In both of the first and second embodiments, coplanar TFTs were used as the switching elements. In this embodiment, an inverse staggered TFT is used instead.

8 is a cross-sectional view of the TFT and the storage capacitor using the amorphous silicon film for the active layer. In FIG. 8, a gate electrode 113A made of a tantalum film on a base film 10A is formed on the surface of the glass substrate 10A, and tantalum oxide 114A as a gate insulating film is formed on the surface thereof. Silicon nitride 114B is formed on the surface of tantalum oxide 114A, and tantalum oxide 114A and silicon nitride 114B function as a gate insulating film. On the surface of the silicon nitride 114B, an intrinsic amorphous silicon film 117A for forming a channel is formed. On the surface of the intrinsic amorphous silicon film 117A, a high concentration N-type amorphous silicon film 116A is formed. A portion of the N-type amorphous silicon film 116A that is opposed to the gate electrode 113A is etched and divided into a source region 111A and a drain region 112A. In the source region 111A, an aluminum electrode layer 118B is formed on the molybdenum layer 118A, and the aluminum electrode layer 118B is connected to the source lines S1, S2, S3, .... The pixel electrode 12A made of an ITO film is connected to the drain region 112A.

The pixel electrode 12A (ITO film) is formed up to the end of the pixel regions P11, P12, P13, ... as shown in FIG. 9, so that the end of the pixel electrode 12A has a storage capacitor CS. It serves as the first electrode portion C1 of the.

On the lower layer side of the first electrode portion C1, a dielectric film C3 of storage capacitor CS made of tantalum oxide 114A and silicon nitride 114B formed simultaneously with the gate insulating film is formed. A tantalum film formed simultaneously with the gate electrode 113A is formed on the lower layer side of the dielectric film C3, and this tantalum film functions as the second electrode portion C2 of the storage capacitor CS.

Since other configurations are almost the same as in the first embodiment, detailed description thereof will be omitted. Also in this embodiment, as shown in FIG. 9, the pixel areas P11, P12, P13, ... are arranged corresponding to the color filters 21 in the delta arrangement. Here, only the pixel electrodes 12a of the pixel regions P11, P12, P13, ... corresponding to the same color are connected to the same source lines S1, S2, S3, .... Therefore, the pixel regions P12, P22, P32, ... corresponding to the green G are alternately connected at the left and right opposite sides of the same source line S2 and the source line S2.

In the present embodiment, like the first embodiment, for example, the storage capacitors CS are formed at the same position in the pixel region in the pixel regions P12, P22, P32, ... in the Y-direction along the source line S2. That is, although the first electrode portion C1 of the storage capacitor CS is formed at the end of the pixel electrode 12A unlike the first embodiment, the first electrode portion C1 is different from the first embodiment although it is formed. And the relative positional relationship between the second electrode portion C2 protruding from the adjacent gate lines G0, G1, G2, ... are between the pixel regions P11, P12, P13, ... It is set to coincide in either of the X and Y directions. Therefore, in FIG. 10, the formation pattern A7 of the ITO film and the gate lines G1, G2, G3, ... for forming the pixel electrode 12A and the first electrode portion C1 of the storage capacitor CS. .), When the overlapping portion with the formation pattern A6 of the tantalum film for forming the second electrode portion C2 of the gate electrode 113A and the storage capacitor CS is patterned diagonally with the opposing portion C0 of the storage capacitor CS. When forming the formation pattern A7 of the ITO film and the formation pattern A6 of the tantalum film, the pixels connected to the odd-numbered gate lines G1, G3, ... even if they are not aligned in the left-right direction (X direction). Accumulation capacitor CS of regions P11, P12, ..., P31, P32, ... and pixel capacitors P21, P22, ... connected to gate lines G2, ... The area | region (capacity value of accumulation capacitance CS) of opposing part C0 shown with the diagonal line between and is the same. Therefore, the present embodiment has an effect similar to that of the first embodiment, such that flicker can be prevented in each gate line.

In addition, in the present embodiment, although the adjacent gate lines G0, G1, G2, G3, ... are used as in the first embodiment in forming the second electrode portion C2, Similarly, it is possible to form dedicated storage capacitor lines CM1, CM2, CM3, ... and use them to construct the storage capacitance CS.

Fourth embodiment

In the first to third embodiments, an embodiment of a liquid crystal display device using a delta array of color filters is provided. The embodiment is an embodiment of a liquid crystal display device using a color filter of a mosaic array.

In addition, in this embodiment, since the color filters are arranged in accordance with the mosaic arrangement, the pixels are arranged in a grid. However, since the other parts are the same as in the first embodiment, corresponding parts are given the same reference numerals, and their detailed description is omitted.

11 is a diagram showing a pattern of each component part of the active matrix substrate of this embodiment. On the surface of the transparent substrate, the pixel region corresponds to the intersection of the gate lines G1, G2, G3, ... extending in the X direction and the source lines S1, S2, S3, ... extending in the Y direction. (P11, P12, P13, ...) are formed. In these pixel regions P11, P12, P13, ..., the source lines S1, S2, S3, ... are connected to the transparent pixel electrode 12 via the TFT 11 as a switching element. In addition, the storage capacitor CS is formed between the adjacent gate lines G0, G1, G2, G3, ... and the pixel electrode 12 in order to improve the accumulation characteristic in the liquid crystal capacitor portion CLC.

This configuration is the same as the first to third embodiments in which the color filters 21 have a delta arrangement, but in this embodiment, the color filters 21 of red R, green C, and blue B are formed in a mosaic arrangement. Therefore, the pixel regions P11, P12, P13, ... are arranged correspondingly to the color filters 21 of red R, green G, and blue B. FIG.

In FIG. 11, the types of colors of the color filters corresponding to the respective pixel areas P11, P12, P13, ... are shown as (R) (G) (B). Here, the three color filters of red, green, and blue are periodically arranged in the X direction with these three colors as one unit, as shown in FIG. The first color filter row F1 (color filter row of the hole means) and the second color filter row F2 '(even-numbered color filter row) are each one-third of the period of the first row in the X direction. Are placed apart.

Corresponding to the arrangement of the color filters, the pixel regions P11, P12, P13, ... connected to the gate line G1 correspond to the color filters 21 of red R, green G, and blue B. FIG. The three pixel regions P11, P12, P13, ... are linearly arranged in the X direction as one unit forming the first pixel column (the pixel column at the even end). Three corresponding to red R, green G, and blue B in the second pixel column (pixel column at an even end) including pixel regions P21, P22, P23, ... connected to the gate line G2. The pixel areas P21, P22, P23, ... form one unit and are repeatedly arranged linearly in the X direction.

The pixel region of three colors corresponding to the color filter 21 constituting the red R, the green G, and the blue B between the first pixel column (odd pixel column) and the second pixel column (even column pixel column). They are spaced apart in the X direction by a distance equivalent to one-third period when they are arranged periodically as one unit. As a result, the center positions of the pixel regions P11, P12, P13, ... are in a state of being alternated left and right by one pixel pitch for each stage.

In the active matrix substrate configured as described above, unlike the active matrix substrate using the delta array, only the pixel electrodes of the pixel region corresponding to the same color and the same source line among the source lines S1, S2, S3, ... are used. Even when connected, the source lines S1, S2, S3, ... are formed so as to extend linearly between the pixel areas in the Y direction.

As in the first to third embodiments, the pixel electrodes 12 in the pixel regions P12, P22, P32, ... are connected to the same source line S2 alternately in left and right. Therefore, for each pixel region P11, P12, P13, ... in the X direction, the TFT 11, the pixel electrode 12, and the storage capacitor CS (first electrode portion C1 and second electrode portion) While the relative formation positions of (C2) are the same, relative to the pixel regions P12, P22, P23, ... in the Y direction along the source line S2, the relative of the TFT 11 and the pixel electrode 12 The formation position is reversed left and right every step.

However, the storage capacitor CS is formed at the same relative position in any pixel region. That is, the relative positions of the storage capacitors CS in the pixel region are the same among the storage capacitors adjacent in the Y direction.

The relative positional relationship between the first electrode portion C1 of the storage capacitor CS and the second electrode portion C2 protruding from the adjacent gate lines G0, G1, G2, ... is defined in each pixel region. It is the same as any one of the X direction and the Y direction among (P12, P22, P32, ...).

Therefore, when forming the first electrode portion C1 and the second electrode portion C2 of the storage capacitor CS, even if not aligned in the left-right direction (X direction) or up-down direction (Y direction), Pixel areas P11, P12, P13, ... corresponding to gate lines G1, G2, G3, ... and pixel areas P21, corresponding to even-numbered gate lines G2, ... The same effects as those of the first embodiment can be obtained, such as the occurrence of flicker between P22, P23, ...).

In addition, similarly to the second embodiment, although a portion of the adjacent gate lines G0, G1, G2, G3, ... is used for the second electrode portion C2 of the storage capacitor CS, similarly to the first embodiment. It is possible to form dedicated storage capacitor lines CM1, CM2, CM3, ..., and use a portion thereof for the second electrode portion C2 of the storage capacitor CS.

As the TFT 11, not only a coplanar TFT but also an inverse staggered TFT may be used as in the third embodiment.

Other Examples

The active matrix substrate according to the present invention can prevent flicker due to misalignment even when used in a monochrome liquid crystal display device as in the case of a color liquid crystal display device.

Moreover, in each Example, although the transparent ITO electrode was used, this invention can be similarly applied also to the reflection type liquid crystal display device which used the aluminum electrode etc. as a pixel electrode.

The present invention can also be applied to an active matrix substrate using a diode having a metal-insulator-metal (MIM) structure as a switching element instead of a TFT. That is, by similarly manufacturing the formation positions relative to the first electrode portion and the second electrode portion of the storage capacitors between the storage capacitors adjacent to each other in the Y direction, it has an effect similar to those of the embodiments (1) to (4).

As described above, in the present invention, when the structures of the first electrode portion and the second electrode portion constituted by the storage capacitor of the active matrix substrate are moved in parallel between the pixel regions, they can overlap, that is, the first electrode portion and the second electrode. The relative positional relationship of the electrode portions is the same between each pixel region. Therefore, according to the present invention, the capacitance value of the storage capacitance becomes the same even if not aligned when forming the first electrode portion and the second electrode portion. Therefore, it is possible to eliminate the difference in the capacitance value of the storage capacitance between the odd gate stage and the even gate stage and to reduce flicker.

In addition, although the formation position and the occupied area of the first electrode portion and the second electrode portion are not limited in the pixel region, according to the present invention, the first electrode and Flickering due to misalignment when forming the second electrode portion can be prevented. Therefore, it is particularly advantageous when realizing a high precision and high density liquid crystal display device.

Further, only the formation pattern of the first electrode portion is different between the pixel region corresponding to the odd gate end and the pixel region corresponding to the even gate end, and the pattern of the other component parts is substantially the same. Therefore, between the opposing substrate including the color filter and the active matrix substrate, or between the pixel region connected to the odd gate end and the pixel region connected to the even gate end even without alignment on the active matrix substrate. The difference in aperture ratio is also eliminated, and non-uniform horizontal lines can be effectively prevented.

Claims (13)

As an active matrix substrate, A plurality of gate lines extending in the first direction, A plurality of source lines extending in a second direction crossing the first direction, A plurality of thin film transistors including a source region electrically connected to one of the source lines; A plurality of pixel electrodes electrically connected to one drain region of the thin film transistors, respectively; A plurality of storage capacitors disposed along a second direction, the first electrode electrically connected to one of the pixel electrodes and a second electrode electrically connected to the other of the gate lines adjacent to one of the gate lines. Including them, And the storage capacitors adjacent to each other in a second direction are located along the same side of the pixel electrodes, and the storage capacitors are disposed to overlap the source line. As an active matrix substrate, A plurality of gate lines extending in the first direction, A plurality of source lines extending in a second direction crossing the first direction, A plurality of thin film transistors including a source region electrically connected to one of the source lines; A plurality of pixel electrodes electrically connected to drain regions of one of the thin film transistors, A plurality of storage capacitors each including a first electrode electrically connected to one of the pixel electrodes and a second electrode electrically connected to the other of the gate lines adjacent to one of the gate lines, And the storage capacitors adjacent to each other in a second direction are located along the same side of the pixel electrodes, and the storage capacitors are disposed to overlap the source line. As a color liquid crystal display device, A plurality of gate lines extending in the first direction, A plurality of source lines extending in a second direction crossing the first direction, A plurality of thin film transistors including a source region electrically connected to one of the source lines; A plurality of pixel electrodes electrically connected to drains of one of the thin film transistors, respectively; A first electrode electrically connected to one of the pixel electrodes and a second electrode electrically connected to the other of the gate lines adjacent to one of the gate lines, the second electrode being disposed in a second direction or the source; A plurality of accumulation capacities arranged along the lines, A second set of color filters having a unit period periodically arranged in a first direction, the second set of color filters adjacent to the first color filter string in a second direction, and periodically arranged in a first direction And a first color filter string coupled to a corresponding electrode of the pixel electrodes and one of three colors, the first color filter string including one unit period set of a color filter string that determines a unit period. Storage capacitors adjacent to each other in a second direction are located along the same side of the pixel electrodes, and the storage capacitors are disposed to overlap the source line. The first color filter string and the second filter string are disposed to be separated from each other in the first direction by a distance corresponding to a half unit period, And each of the source lines is connected to one of the thin film transistors having only pixel electrodes corresponding to a color filter having a selected one of the three colors. As a color liquid crystal display device, A plurality of gate lines extending in the first direction, A plurality of source lines extending in a second direction crossing the first direction, A plurality of thin film transistors including a source region electrically connected to one of the source lines; A plurality of pixel electrodes electrically connected to drain regions of one of the thin film transistors, A first electrode electrically connected to one of the pixel electrodes and a second electrode electrically connected to another one of the gate lines adjacent to one of the gate lines, the second electrode being disposed in a second direction or the source; A plurality of accumulation capacities disposed along each of the lines, A second set of color filters periodically arranged in a first direction, the second color filter train being adjacent to the first color filter train in a second direction, and the first periodically arranged in a first direction; A first color filter string comprising a color filter string and a unit set of color filters associated with an electrode corresponding to one of the pixel electrodes, each of the color filters being one of three colors, and determining a unit period; The storage capacitors adjacent in the second direction are located along the same side of the pixel electrodes, and the storage capacitors are disposed to overlap the source line. The first color filter string and the second color filter string are disposed to be separated from each other in the first direction by a distance corresponding to a 1/3 unit period, Each of the source lines is connected to pixel electrodes corresponding to a color filter having a selected one of the three colors through one of the thin film transistors. As a color liquid crystal display device, A plurality of gate lines extending in the first direction, A plurality of storage capacitor lines extending in the first direction, A plurality of source lines extending in a second direction crossing the first direction, A plurality of thin film transistors including a source region electrically connected to one of the source lines; A plurality of pixel electrodes electrically connected to one drain region of the thin film transistors, respectively; A plurality of storage capacitors each including a first electrode electrically connected to one of the pixel electrodes and a second electrode electrically connected to one of the capacitor lines; Storage capacitors adjacent to each other in a second direction are located along the same side of the pixel electrodes, and the storage capacitors are disposed to overlap the source line. Each pixel electrode corresponds to a color, and only pixel electrodes corresponding to the same color are connected to the same source line through the thin film transistors. As an active matrix substrate, A plurality of gate lines extending in the first direction, A plurality of storage capacitor lines extending in the first direction, A plurality of source lines extending in a second direction crossing the first direction, A plurality of thin film transistors each comprising a source region electrically connected to one of the source lines; A plurality of pixel electrodes electrically connected to drain regions of one of the thin film transistors, Storage capacitors each including a first electrode electrically connected to one of the pixel electrodes and a second electrode electrically connected to one of the storage capacitor lines; The storage capacitors adjacent to each other in the second direction are located along the same side of the pixel electrodes, and the storage capacitors are disposed to overlap the source line. As an active matrix substrate, A plurality of gate lines extending in the first direction, A plurality of storage capacitor lines extending in the first direction, A plurality of source lines extending in a second direction crossing the first direction, A plurality of thin film transistors including a source region electrically connected to one of the source lines; A plurality of pixel electrodes electrically connected to drain regions of one of the thin film transistors; A first electrode electrically connected to one of the pixel electrodes and a second electrode electrically connected to one of the storage capacitor lines, and each of the plurality of storage capacitors disposed along each of the source lines; , The storage capacitors adjacent to each other in the second direction are positioned to cross the same side of the pixel electrodes, and the storage capacitors are disposed to overlap the source line. As a color liquid crystal display device, A plurality of gate lines extending in the first direction, A plurality of storage capacitor lines extending in the first direction, A plurality of source lines extending in a second direction crossing the first direction, A plurality of thin film transistors including a source region electrically connected to one of the source lines; A plurality of pixel electrodes electrically connected to drain regions of one of the thin film transistors, respectively; A plurality of accumulations including a first electrode electrically connected to one of the pixel electrodes and a second electrode electrically connected to one of the storage capacitor lines and disposed along a second direction or along each of the source lines; The capacitors, and the extended storage capacitors adjacent to each other in the second direction, are located along the same side of the pixel electrodes, and the storage capacitors are arranged to overlap the source line, The first color filter periodically arranged in a first direction and a second color filter string adjacent to the first color filter string in a second direction and including a unit set of the three color filters periodically arranged in a first direction A column and a first color filter column associated with a corresponding one of said pixel electrodes, said first color filter column being one of said three colors and comprising a unit set of color filters for determining a unit period, The first color filter string and the second color filter string are disposed to be separated from each other in the first direction by a distance corresponding to a half unit period, Each of the source lines is connected to pixel electrodes corresponding to a color filter having one selected color of the three colors through one of the thin film transistors. As a color liquid crystal display device, A plurality of gate lines extending in the first direction, A plurality of storage capacitor lines extending in the first direction, A plurality of source lines extending in a second direction crossing the first direction, A plurality of thin film transistors including a source region electrically connected to one of the source lines; A plurality of pixel electrodes and each of the pixel electrodes is electrically connected to one drain region of the thin film transistors, A first electrode electrically connected to one of the pixel electrodes and a second electrode electrically connected to one of the storage capacitor lines, respectively, disposed in a second direction or disposed along each of the source lines; A plurality of storage capacitors, wherein the storage capacitors adjacent to each other in a second direction are disposed along the same side of the pixel electrodes, and the storage capacitors are disposed to overlap the source line, A second color filter string comprising a unit set of the three color filters periodically arranged in a first direction and adjacent to the first color filter string in a second direction, and the first color periodically arranged in a first direction A first column of color filters, the first column of color filters associated with electrodes corresponding to one of the pixel electrodes, the first color filter row being one of the three colors and comprising a unit set of color filters for determining a unit period, The first color filter string and the second color filter string are disposed apart from each other in a first direction by a distance corresponding to a 1/3 unit period, Each of the source lines is connected to only pixel electrodes corresponding to a color filter having a selected one of the three colors through one of the thin film transistors. The method according to any one of claims 1, 2, 6, and 7, And the first electrode is a region in which a drain region of the transistor extends. The method according to any one of claims 1, 2, 6, and 7, And a dielectric film of a storage capacitor formed by the same process and of the same material as the gate insulating film of the thin film transistors. The method according to any one of claims 3, 4, 5, 8 and 9, And the first electrode is a region in which a drain region of the transistor is extended. The method according to any one of claims 3, 4, 5, 8 and 9, And a storage capacitor dielectric film formed of the same material and by the same processing as the gate insulating film of the thin film transistors.