Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
  • G06F15/163—Interprocessor communication
  • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Definitions

• the present invention relates to a method according to the preamble of the appended claim 1 for transferring data between at least two processors.
• the invention also relates to a multiprocessor system according to the preamble of the appended claim 4, in which at least two processors communicate with each other via a common memory area.
• processor refers in this context generally to any equipment operating according to an external or internal program.
• processors communicate with each other by means of a common memory area such as a parallel register
• at least one of the processors writes to said memory area and at least one processor reads from said memory area.
• Writing and reading are usually carried out via different data buses, the load on the data bus of each processor being thus kept to the minimum.
• the error situation described above can be avoided by synchronizing the operation of the processors so that simultaneous reading and writing are prevented.
• synchronizing can be carried out by means of equipment.
• this kind of solution complicates the implementation and thus entails additional costs.
• different processors give the control signals used for reading and writing automatically, in which case synchronizing them by means of equipment may be impossible or may include its own malfunction risks.
• the object of the present invention is to obviate the disadvantages described above and to provide a solution by means of which the transfer of erroneous data can be avoided in the simplest possible manner.
• the idea of the invention is to use one or more interruption signals for the mutual timing of write and read operations, whereby (a) where one common interruption signal is used, the read and write operations performed by different processors are conducted by the program of each processor with respect to the common interruption moment so that no simultaneous reading and writing will occur, or (b) where several interruption signals are used, the mutual order in time domain of these signals is constantly kept the same, the interval between them being also kept within predetermined limits, whereby it is possible to perform the read and/or write operation of at least one but preferably every processor immediately after the interruption moment corresponding to the processor concerned. Since a simultaneous read operation performed by several processors will not, depending on the configuration, necessarily cause a malfunction, it can be allowed on certain conditions.
• Figure 1 shows a multiprocessor system operating according to the first embodiment of the invention
• Figure 2 shows the timing of read and write operations in the system shown in Figure 1
• FIG. 3 shows the multiprocessor system shown in Figure 1, which operates in this case according to the second embodiment of the invention.
• Figure 4 shows the timing of read and write operations in the system shown in Figure 3.
• Figures 1 and 2 show by way of example the solution of the invention as applied to communication between a main controller (e.g. MC68302) and a digital signal processor (e.g. DSP16) included in an equipment unit of the applicant's DYNACARD® product family .
• a main controller e.g. MC68302
• a digital signal processor e.g. DSP16
• a main controller 11 and a DSP circuit 12 communicate with each other via a parallel interface 13 of the DSP circuit.
• the parallel interface of the DSP circuit comprises two internal registers.
• the internal processing unit of the DSP circuit writes to one of these registers and reads the content of the other one.
• the parallel bus PB of the main controller 11 is connected to the parallel interface 13 of the DSP circuit.
• the main controller writes to the register which the internal processing unit of the DSP circuit reads from, and the main controller reads from the register which the internal processing unit of the DSP circuit writes to.
• Both the main controller and the DSP circuit operate in synchronism with their respective clock signals (C K1 and CLK2, respectively).
• the clock signals are not synchronized with each other.
• the same interruption signal INTR producing an interruption at intervals of (in this example) 125 microseconds is applied to the interruption input INT_IN of both controllers ( Figure 2).
• the main controller 11 is programmed to operate so that it writes to and reads from the parallel registers of the DSP circuit for a short time, e.g. less than 50 microseconds, from the interruption, that is to say well before the next interruption arrives.
• the DSP circuit it is programmed to operate so that once having received an interruption, it performs different calculations and other operations for so long that the time of 125 microseconds almost comes to an end.
• FIG. 3 and 4 corresponds thus otherwise to the embodiment in Figures 1 and 2 except that now a separate interruption signal is applied to both processors: an interruption signal INTR1 to the main controller 11 and an interruption signal INTR2 to the DSP circuit 12.
• the interruption signal INTR1 causes the main controller to perform read and write operations
• the interruption signal INTR2 causes the DSP circuit to perform its respective read and write operations.
• the first embodiment described above is more difficult to implement, because it requires ensuring by means of software that the DSP circuit performs calculations and other operations for a sufficiently long time after an interruption, whereas with the latter alternative, a separate interruption signal INTR2 ensures that it is not possible for the DSP circuit to perform reading and writing too early (permitted only after the interruption moment), and thus it is possible to perform the read and write operations immediately after the interruption (it is not necessary to ensure by means of a program that a desired amount of time has elapsed).
• the first embodiment described above is more preferable because it is not necessary to take into account the mutual timing of different interruption signals.
• the alternatives described above can also be used as combined so that some of the processors have a common interruption signal while others have their respective interruption signals, which are synchronized with each other and with respect to the common interruption signal in the manner described above.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Theoretical Computer Science (AREA)
• Software Systems (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Multi Processors (AREA)

Priority Applications (5)

Applications Claiming Priority (2)

Publications (1)

Family

ID=8538771

Family Applications (1)

Country Status (6)

Citations (3)

• 1993
  • 1993-10-13 FI FI934523A patent/FI94190C/fi active
• 1994
  • 1994-10-12 DE DE4497671A patent/DE4497671B4/de not_active Expired - Fee Related
  • 1994-10-12 DE DE4497671T patent/DE4497671T1/de active Pending
  • 1994-10-12 AU AU78150/94A patent/AU7815094A/en not_active Abandoned
  • 1994-10-12 GB GB9607540A patent/GB2298064B/en not_active Expired - Fee Related
  • 1994-10-12 WO PCT/FI1994/000459 patent/WO1995010811A1/en active Application Filing
• 1996
  • 1996-04-10 SE SE9601346A patent/SE515581C2/sv not_active IP Right Cessation

Patent Citations (3)

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