WO1994014244A1 - Compensateur de commande de gain pour synthetiseur asservi en phase - Google Patents

Compensateur de commande de gain pour synthetiseur asservi en phase Download PDF

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Publication number
WO1994014244A1
WO1994014244A1 PCT/US1993/011810 US9311810W WO9414244A1 WO 1994014244 A1 WO1994014244 A1 WO 1994014244A1 US 9311810 W US9311810 W US 9311810W WO 9414244 A1 WO9414244 A1 WO 9414244A1
Authority
WO
WIPO (PCT)
Prior art keywords
gain control
pll synthesizer
multiplication factor
generating
reference frequency
Prior art date
Application number
PCT/US1993/011810
Other languages
English (en)
Inventor
Michael A. Wyatt
Original Assignee
Honeywell Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc. filed Critical Honeywell Inc.
Publication of WO1994014244A1 publication Critical patent/WO1994014244A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth

Definitions

  • the present invention relates generally to PLL synthesizers and more particularly to a gain control compensator to linearize PLL synthesizers over the frequency range of operation of the PLL synthesizer.
  • Phase locked loop (PLL) synthesizers are utilized in numerous types of operations, typically as a frequency multiplier for utilization as a signal or modulation source.
  • the PLL synthesizers generally have a designed frequency range of operation.
  • the PLL synthesizers include a programmable divider which generates a multiplication factor (N).
  • the programmable divider is coupled to a voltage controlled oscillator (VCO) to provide an operation of the VCO of N times the PLL synthesizer's input reference frequency (Fr).
  • VCO voltage controlled oscillator
  • the natural frequency (Wn) of the PLL synthesizer loop changes, as does a dampening factor (Zeta).
  • Wn natural frequency
  • Zeta dampening factor
  • the present invention therefore was developed to provide a substantially constant PLL synthesizer loop gain, over the frequency range, by eliminating the undesirable changes due to changing N.
  • the present invention is directed to an improved PLL synthesizer having a gain control compensator which compensates the PLL synthesizer loop gain over the frequency range of operation of the PLL synthesizer.
  • the gain control compensator includes a gain control amplifier which functions to eliminate the effects of changing N over the frequency range of operation.
  • the gain control amplifier couples the loop filter to the VCO and generates a factor equal to an inverse N to compensate the PLL synthesizer.
  • the gain control amplifier includes a digitally programmable resistor which is programmed as N is changed to eliminate the effects of changing N and can also compensate for gain non-linearity in the VCO transfer function.
  • FIGURE 1 is a block diagram of a prior art PLL synthesizer
  • FIGURE 2 is a block diagram of a PLL synthesizer including the gain control compensator of the present invention.
  • FIGURE 3 is a schematic diagram of one embodiment of a gain control amplifier of the present invention.
  • a block diagram of a prior art PLL synthesizer is designated generally by the reference numeral 10.
  • the PLL synthesizer 10 receives a reference frequency (Fr) signal on an input line 12.
  • the Fr signal is input to a phase detector 14, which generates an output signal on a line 16.
  • the output signal of the phase detector 14 is coupled to a loop filter 18.
  • a filtered signal from the filter 18 is coupled to a voltage controlled oscillator (VCO) 20 via a line 22.
  • VCO voltage controlled oscillator
  • the VCO 20 generates an output signal (N*Fr) on a line 24, which is the Fr signal multiplied by the factor N.
  • the loop of the PLL synthesizer 10 is completed by also coupling the output signal of the VCO 20 to a programmable divider 26 on a line 28.
  • the programmable divider 26 provides a frequency divided by N output signal on a line 30, which is coupled back to the phase detector 14 to provide the desired N*Fr output signal.
  • the PLL synthesizer 10 has a natural frequency (Wn) and a dampening factor (Zeta). As N is changed in the PLL synthesizer 10, both Wn and Zeta change in accordance with the following formulas:
  • Ko is a transfer function related to the VCO 20
  • Ka is a transfer function related to the filter 18
  • Kd is a transfer function related to the phase detector 14 and ⁇
  • ⁇ 2 are filter time constants. Since N is a factor in determining both Wn and Zeta, loop changes are produced in the PLL synthesizer 10 as N is changed. Thus, for example, both the transient response and the settling time of the PLL synthesizer 10 are effected as N is changed.
  • an improved PLL synthesizer 10' which includes one embodiment of a gain control amplifier 40 of the present invention.
  • the gain control amplifier 40 acts on the output signal from the filter 18 on the line 22 and is coupled to the VCO 20 by a line 42.
  • the gain control amplifier 40 is designed to have a transfer function Ka as shown in the following equation:
  • the gain control amplifier 40 includes a fixed input resistor 44 and a digitally p rogrammable resistor (RDAC) 46 coupled in parallel with a conventional inverting operational amplifier 48.
  • RDAC digitally p rogrammable resistor
  • the function K' of the transfer function (3) of the gain control amplifier 40 is expressed by the following formula:
  • the VCO 20 generally has a gain constant K 0 , which also will vary with the output frequency N*Fr.
  • the gain control amplifier 40 also can be programmed to compensate for the gain constant variations in the VCO 20 in addition to the factor N.
  • the RQAC 46 can be one of several device types, such as a CMOS device.
  • the VCO 20 can be of several different types, each type of which has some gain non-linearity.
  • a second gain control amplifier (not illustrated), like the gain control amplifier 40, can be added to the PLL synthesizer 10' to compensate for the non- linearity of the specific type of the VCO 20.
  • the two gain control amplifiers can be cascaded together in the PLL synthesizer 10'. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced other than is specifically described.

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Un synthétiseur (10) asservi en phase amélioré est constitué d'un compensateur de commande de gain (40) qui compense la sortie du synthétiseur asservi en phase dans la gamme de fréquences de fonctionnement de ce dernier. Le compensateur de commande de gain se compose d'un amplificateur (48) de commande de gain et d'une résistance programmable (46) servant à éliminer les effets du changement du facteur N sur la gamme de fréquences de fonctionnement. L'amplification de commande de gain couple un signal de sortie d'un filtre en boucle (18) à l'oscillateur commandé en tension (20), et produit un facteur égal à un facteur N inversé afin de compenser ledit synthétiseur. Le synthétiseur peut compenser la non-linéarité du gain dans la fonction de transfert de l'oscillateur commandé en tension.
PCT/US1993/011810 1992-12-11 1993-12-07 Compensateur de commande de gain pour synthetiseur asservi en phase WO1994014244A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US98911092A 1992-12-11 1992-12-11
US07/989,110 1992-12-11

Publications (1)

Publication Number Publication Date
WO1994014244A1 true WO1994014244A1 (fr) 1994-06-23

Family

ID=25534768

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1993/011810 WO1994014244A1 (fr) 1992-12-11 1993-12-07 Compensateur de commande de gain pour synthetiseur asservi en phase

Country Status (1)

Country Link
WO (1) WO1994014244A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000021197A1 (fr) * 1998-10-02 2000-04-13 Ericsson, Inc. Boucles a phase asservie comprenant des reseaux de multiplicateurs analogiques produisant une largeur de bande constante pour la boucle
US11545982B2 (en) 2021-03-23 2023-01-03 Nxp B.V. Type-I PLLs for phase-controlled applications

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1444860A (en) * 1974-12-12 1976-08-04 Mullard Ltd Frequency synthesiser
GB2207310A (en) * 1987-07-11 1989-01-25 Plessey Co Plc Phase-locked loop circuits

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1444860A (en) * 1974-12-12 1976-08-04 Mullard Ltd Frequency synthesiser
GB2207310A (en) * 1987-07-11 1989-01-25 Plessey Co Plc Phase-locked loop circuits

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
M. J. UNDERHILL: "Wide range frequency synthesizers with improved dymamic performance", RADIO AND ELECTRONIC ENGINEER, vol. 50, no. 6, June 1980 (1980-06-01), LONDON GB, pages 291 - 296, XP002011879 *
RICHARD YEAGER: "Loop Gain Compensation in Phase-Locked Loops", RCA REVIEW, vol. 47, March 1986 (1986-03-01), PRINCETON., US, pages 78 - 87 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000021197A1 (fr) * 1998-10-02 2000-04-13 Ericsson, Inc. Boucles a phase asservie comprenant des reseaux de multiplicateurs analogiques produisant une largeur de bande constante pour la boucle
US6150857A (en) * 1998-10-02 2000-11-21 Ericsson Inc. Phase locked loops including analog multiplier networks that can provide constant loop bandwidth
US11545982B2 (en) 2021-03-23 2023-01-03 Nxp B.V. Type-I PLLs for phase-controlled applications

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