WO1992000558A3 - Appareil destine a generer des signaux d'horloge multiphases, detecteur de phase et son appareil de retablissement - Google Patents

Appareil destine a generer des signaux d'horloge multiphases, detecteur de phase et son appareil de retablissement Download PDF

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Publication number
WO1992000558A3
WO1992000558A3 PCT/US1991/004648 US9104648W WO9200558A3 WO 1992000558 A3 WO1992000558 A3 WO 1992000558A3 US 9104648 W US9104648 W US 9104648W WO 9200558 A3 WO9200558 A3 WO 9200558A3
Authority
WO
WIPO (PCT)
Prior art keywords
signal
phase
tap
delay line
phase detector
Prior art date
Application number
PCT/US1991/004648
Other languages
English (en)
Other versions
WO1992000558A2 (fr
Inventor
Gregory T Koker
Steven T Tsang
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/545,887 external-priority patent/US5120990A/en
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Priority to DE69106362T priority Critical patent/DE69106362T2/de
Priority to EP91913180A priority patent/EP0536301B1/fr
Publication of WO1992000558A2 publication Critical patent/WO1992000558A2/fr
Publication of WO1992000558A3 publication Critical patent/WO1992000558A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H03D13/004—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means the logic means delivering pulses at more than one terminal, e.g. up and down pulses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

Circuit détecteur de phase destiné à corriger le fonctionnement d'un générateur d'horloge à ligne de temporisation synchrone. Le détecteur de phase comprend des détecteurs de bords multiples (144, 146, 148). Les détecteurs de bords multiples donnent une priorité d'action correctrice par le reste du détecteur de phase à la sortie de lignes de temporisation synchrones, en dépit de la présence ou de l'absence d'une éventuelle erreur de phase inférieure à 360°, si la position de phase du signal de sortie de lignes de temporisation est décalée d'un multiple intégral de 360°. Des branchements multiples (TAP 2, TAP 9, TAP 14), réalisés à partir d'éléments de lignes de temporisation connectés en guirlande ou en série sont aménagés pour les détecteurs de bords multiples. Lesdits détecteurs de bords multiples comparent le bord produit par chacun desdits branchements avec une division d'un signal d'horloge divisé. On a prévu un appareil et un procédé destinés à sauvegarder un signal de commande pour un système commandé par signal. Un signal de commande est transmis à un multiplexeur, lequel produit normalement ce signal de commande. Ce signal de commande est numérisé et stocké par un dispositif de stockage. La sortie du dispositif de stockage est reliée à la fois au multiplexeur et à un comparateur. Le comparateur reçoit également la sortie du multiplexeur, et il compare la sortie du dispositif de stockage et du multiplexeur. Le comparateur transmet un signal au dispositif de stockage afin d'incrémenter ou de décrémenter ce dernier.
PCT/US1991/004648 1990-06-29 1991-06-28 Appareil destine a generer des signaux d'horloge multiphases, detecteur de phase et son appareil de retablissement WO1992000558A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE69106362T DE69106362T2 (de) 1990-06-29 1991-06-28 Verfahren und vorrichtung zur abspeicherung eines digitalen signals zur anwendung in einer synchronlaufzeitkette.
EP91913180A EP0536301B1 (fr) 1990-06-29 1991-06-28 Methode et appareil destine a stocker un signal numerique pour utilisation dans un circuit de retard synchrone

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US07/545,887 US5120990A (en) 1990-06-29 1990-06-29 Apparatus for generating multiple phase clock signals and phase detector therefor
US59172690A 1990-10-02 1990-10-02
US545,887 1990-10-02
US591,726 1990-10-02

Publications (2)

Publication Number Publication Date
WO1992000558A2 WO1992000558A2 (fr) 1992-01-09
WO1992000558A3 true WO1992000558A3 (fr) 1992-04-02

Family

ID=27068059

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1991/004648 WO1992000558A2 (fr) 1990-06-29 1991-06-28 Appareil destine a generer des signaux d'horloge multiphases, detecteur de phase et son appareil de retablissement

Country Status (4)

Country Link
EP (3) EP0609967B1 (fr)
JP (1) JP2812453B2 (fr)
DE (3) DE69130486T2 (fr)
WO (1) WO1992000558A2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572554A (en) * 1994-07-29 1996-11-05 Loral Corporation Synchronizer and method therefor
EP0703673A3 (fr) * 1994-08-26 1996-05-29 Ascom Tech Ag Appareil pour distribuer une multitude de signaux identiques périodiques, qui sont déphasés l'un par rapport à l'autre
WO1996025795A1 (fr) * 1995-02-16 1996-08-22 Telefonaktiebolaget Lm Ericsson Modulateur sigma-delta rapide ayant un generateur de signal d'horloge
JP3195236B2 (ja) 1996-05-30 2001-08-06 株式会社日立製作所 接着フィルムを有する配線テープ，半導体装置及び製造方法
US5821785A (en) * 1996-08-02 1998-10-13 Rockwell Int'l Corp. Clock signal frequency multiplier
WO1998049802A1 (fr) 1997-04-25 1998-11-05 Siemens Aktiengesellschaft Dispositif d'adaptation de phase programmable
EP1040578A1 (fr) 1998-08-04 2000-10-04 Koninklijke Philips Electronics N.V. Boucle d'asservissement du delai avec detection harmonique d'asservissement
CN1084266C (zh) * 1999-11-29 2002-05-08 范勇 上下油封中间夹有油槽和连接导向器的汽车减振器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2112236A (en) * 1981-11-03 1983-07-13 Telecommunications Sa Digital device for clock signal synchronization
US4496861A (en) * 1982-12-06 1985-01-29 Intel Corporation Integrated circuit synchronous delay line
US4672639A (en) * 1984-05-24 1987-06-09 Kabushiki Kaisha Toshiba Sampling clock pulse generator
US4849996A (en) * 1988-03-10 1989-07-18 Ncr Corporation Phase perturbation compensation system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4754164A (en) * 1984-06-30 1988-06-28 Unisys Corp. Method for providing automatic clock de-skewing on a circuit board
US4818894A (en) * 1987-03-09 1989-04-04 Hughes Aircraft Company Method and apparatus for obtaining high frequency resolution of a low frequency signal
JPH0656955B2 (ja) * 1987-08-31 1994-07-27 日本電気株式会社 位相同期発振器
US4833695A (en) * 1987-09-08 1989-05-23 Tektronix, Inc. Apparatus for skew compensating signals
US4868430A (en) * 1988-02-11 1989-09-19 Ncr Corporation Self-correcting digitally controlled timing circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2112236A (en) * 1981-11-03 1983-07-13 Telecommunications Sa Digital device for clock signal synchronization
US4496861A (en) * 1982-12-06 1985-01-29 Intel Corporation Integrated circuit synchronous delay line
US4672639A (en) * 1984-05-24 1987-06-09 Kabushiki Kaisha Toshiba Sampling clock pulse generator
US4849996A (en) * 1988-03-10 1989-07-18 Ncr Corporation Phase perturbation compensation system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 9, No. 11, April 1967 C. E. DORRELL. C. D. SOUTHARD: "CLOCKING CIRCUIT ", *
Patent Abstracts of Japan, Vol 13, No 272, E777, abstract of JP 01- 61120, publ 1989-03-08 *

Also Published As

Publication number Publication date
DE69106362D1 (de) 1995-02-09
DE69130486D1 (de) 1998-12-17
DE69130486T2 (de) 1999-07-15
EP0536301A1 (fr) 1993-04-14
EP0609967B1 (fr) 1998-03-11
JPH06500673A (ja) 1994-01-20
EP0609969A3 (en) 1994-09-28
EP0609969B1 (fr) 1998-11-11
WO1992000558A2 (fr) 1992-01-09
EP0609967A3 (fr) 1995-01-04
DE69106362T2 (de) 1995-05-18
EP0609969A2 (fr) 1994-08-10
DE69129074D1 (de) 1998-04-16
EP0609967A2 (fr) 1994-08-10
EP0536301B1 (fr) 1994-12-28
JP2812453B2 (ja) 1998-10-22
DE69129074T2 (de) 1998-07-02

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