DE69106362D1 - Verfahren und vorrichtung zur abspeicherung eines digitalen signals zur anwendung in einer synchronlaufzeitkette. - Google Patents

Verfahren und vorrichtung zur abspeicherung eines digitalen signals zur anwendung in einer synchronlaufzeitkette.

Info

Publication number
DE69106362D1
DE69106362D1 DE69106362T DE69106362T DE69106362D1 DE 69106362 D1 DE69106362 D1 DE 69106362D1 DE 69106362 T DE69106362 T DE 69106362T DE 69106362 T DE69106362 T DE 69106362T DE 69106362 D1 DE69106362 D1 DE 69106362D1
Authority
DE
Germany
Prior art keywords
storing
digital signal
running chain
synchronized running
synchronized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69106362T
Other languages
English (en)
Other versions
DE69106362T2 (de
Inventor
Gregory Koker
Steven Tsang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/545,887 external-priority patent/US5120990A/en
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Publication of DE69106362D1 publication Critical patent/DE69106362D1/de
Application granted granted Critical
Publication of DE69106362T2 publication Critical patent/DE69106362T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H03D13/004—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means the logic means delivering pulses at more than one terminal, e.g. up and down pulses
DE69106362T 1990-06-29 1991-06-28 Verfahren und vorrichtung zur abspeicherung eines digitalen signals zur anwendung in einer synchronlaufzeitkette. Expired - Lifetime DE69106362T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/545,887 US5120990A (en) 1990-06-29 1990-06-29 Apparatus for generating multiple phase clock signals and phase detector therefor
US59172690A 1990-10-02 1990-10-02
PCT/US1991/004648 WO1992000558A2 (en) 1990-06-29 1991-06-28 Apparatus for generating multiple phase clock signals and phase detector and recovery apparatus therefor

Publications (2)

Publication Number Publication Date
DE69106362D1 true DE69106362D1 (de) 1995-02-09
DE69106362T2 DE69106362T2 (de) 1995-05-18

Family

ID=27068059

Family Applications (3)

Application Number Title Priority Date Filing Date
DE69129074T Expired - Lifetime DE69129074T2 (de) 1990-06-29 1991-06-28 Gerät zum Erkennen von Phasenfehlern
DE69106362T Expired - Lifetime DE69106362T2 (de) 1990-06-29 1991-06-28 Verfahren und vorrichtung zur abspeicherung eines digitalen signals zur anwendung in einer synchronlaufzeitkette.
DE69130486T Expired - Lifetime DE69130486T2 (de) 1990-06-29 1991-06-28 Synchrone Verzögerungsleitung

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69129074T Expired - Lifetime DE69129074T2 (de) 1990-06-29 1991-06-28 Gerät zum Erkennen von Phasenfehlern

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69130486T Expired - Lifetime DE69130486T2 (de) 1990-06-29 1991-06-28 Synchrone Verzögerungsleitung

Country Status (4)

Country Link
EP (3) EP0609969B1 (de)
JP (1) JP2812453B2 (de)
DE (3) DE69129074T2 (de)
WO (1) WO1992000558A2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572554A (en) * 1994-07-29 1996-11-05 Loral Corporation Synchronizer and method therefor
EP0703673A3 (de) * 1994-08-26 1996-05-29 Ascom Tech Ag Vorrichtung zum Abgeben von mehreren gleichen, gegeneinander phasenverschobenen, periodischen Signalen
WO1996025795A1 (en) * 1995-02-16 1996-08-22 Telefonaktiebolaget Lm Ericsson A fast sigma-delta modulator having a controlled clock generator
JP3195236B2 (ja) 1996-05-30 2001-08-06 株式会社日立製作所 接着フィルムを有する配線テープ，半導体装置及び製造方法
US5821785A (en) * 1996-08-02 1998-10-13 Rockwell Int'l Corp. Clock signal frequency multiplier
EP0978177A1 (de) 1997-04-25 2000-02-09 Siemens Aktiengesellschaft Programmierbare phasenanpassung
WO2000008758A1 (en) * 1998-08-04 2000-02-17 Koninklijke Philips Electronics N.V. A delay locked loop with harmonic lock detection
CN1084266C (zh) * 1999-11-29 2002-05-08 范勇 上下油封中间夹有油槽和连接导向器的汽车减振器

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2515902B1 (fr) * 1981-11-03 1985-12-06 Telecommunications Sa Dispositif numerique de synchronisation d'horloge et son application aux reseaux de connexion
US4496861A (en) * 1982-12-06 1985-01-29 Intel Corporation Integrated circuit synchronous delay line
US4672639A (en) * 1984-05-24 1987-06-09 Kabushiki Kaisha Toshiba Sampling clock pulse generator
US4754164A (en) * 1984-06-30 1988-06-28 Unisys Corp. Method for providing automatic clock de-skewing on a circuit board
US4818894A (en) * 1987-03-09 1989-04-04 Hughes Aircraft Company Method and apparatus for obtaining high frequency resolution of a low frequency signal
JPH0656955B2 (ja) * 1987-08-31 1994-07-27 日本電気株式会社 位相同期発振器
US4833695A (en) * 1987-09-08 1989-05-23 Tektronix, Inc. Apparatus for skew compensating signals
US4868430A (en) * 1988-02-11 1989-09-19 Ncr Corporation Self-correcting digitally controlled timing circuit
GB8805767D0 (en) * 1988-03-10 1988-04-07 Ncr Co Phase perturbation compensation system

Also Published As

Publication number Publication date
WO1992000558A2 (en) 1992-01-09
DE69129074T2 (de) 1998-07-02
EP0609967B1 (de) 1998-03-11
EP0609969B1 (de) 1998-11-11
DE69130486T2 (de) 1999-07-15
EP0609969A2 (de) 1994-08-10
EP0609967A2 (de) 1994-08-10
WO1992000558A3 (en) 1992-04-02
EP0609969A3 (en) 1994-09-28
JP2812453B2 (ja) 1998-10-22
EP0609967A3 (de) 1995-01-04
DE69129074D1 (de) 1998-04-16
EP0536301A1 (de) 1993-04-14
DE69130486D1 (de) 1998-12-17
JPH06500673A (ja) 1994-01-20
EP0536301B1 (de) 1994-12-28
DE69106362T2 (de) 1995-05-18

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