WO1991007781A1 - Circuit a semi-conducteurs integre bi-stable - Google Patents

Circuit a semi-conducteurs integre bi-stable Download PDF

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Publication number
WO1991007781A1
WO1991007781A1 PCT/SE1990/000695 SE9000695W WO9107781A1 WO 1991007781 A1 WO1991007781 A1 WO 1991007781A1 SE 9000695 W SE9000695 W SE 9000695W WO 9107781 A1 WO9107781 A1 WO 9107781A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistors
transistor
connection
circuit
channel region
Prior art date
Application number
PCT/SE1990/000695
Other languages
English (en)
Inventor
Per Svedberg
Original Assignee
Asea Brown Boveri Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asea Brown Boveri Ab filed Critical Asea Brown Boveri Ab
Publication of WO1991007781A1 publication Critical patent/WO1991007781A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Definitions

  • the present invention relates to a bistable integrated semiconductor circuit.
  • a bistable circuit has an output signal which may assume either of two definite positions. With the aid of a control signal supplied to the circuit, the circuit may be switched to the desired position. The circuit and its output signal thereafter remain unchanged for an unlimited period of time until the circuit, with the aid of a control signal, is switched to the opposite position.
  • Bistable circuits have extensive use in, for example, logic circuits and in circuits and equipment for digital signal and information processing.
  • One example of such use is in so-called semiconductor memories. Such a memory is designed as an integrated circuit comprising a very large number of bistable circuits.
  • the so-called packing density and hence the number of bistable circuits are limited by the dimensions of the individual circuit. These dimensions, in turn, are determined by the number of circuit elements included in a bistable circuit, by their dimensions and by the necessary space for connections between circuit elements included in the circuit.
  • the invention aims to provide a bistable circuit of the kind described in the introduction, which has a simple and space- saving configuration and hence makes possible a high packing density and thus the arrangement of a large number of bistable circuits within one and the same integrated circuit.
  • Figure 1 schematically shows the principle of a bistable circuit according to the invention.
  • Figure 2 shows the electric circuit diagram of the circuit.
  • Figure 3 shows an embodiment of a circuit according to the invention, Figure 3a showing the circuit seen in a direction perpendicular to the surface of the substrate on which it is arranged.
  • Figure 3b showing in the form of a perspective drawing the semiconducting regions included in the circuit,
  • Figure 3c showing the section C-C in Figure 3a and Figure 3d showing the section D-D in Figure 3a.
  • the circuit according to the invention shown in Figure 1 comprises four field effect transistors.
  • the designation "field effect transistors” is used here and in the following in spite of the fact that the transistors lack conventional control electrodes. Further, in the following the designation “main regions” are used for the source and drain regions of the transistors.
  • the transistors 1 and 2 are of P-type and the transistors 3 and 4 of N-type.
  • the transistor 1 has the P-doped main regions 11 and 13 and the intermediate v-doped (weakly N-doped) channel region 15.
  • the transistor 2 has the P-doped main regions 21 and 23 and the intermediate V-doped channel region 25.
  • the transistor 2 has the P-doped main regions 21 and 23 and the intermediate V-doped channel region 25.
  • the transistor 3 has the N-doped main regions 31 and 33 and the intermediate ⁇ -doped (weakly P-doped) channel region 35.
  • the transistor 4 has the N-doped main regions 41 and 43 and the intermediate ⁇ -doped chanel region 45.
  • the transistors are arranged in two planes, the transistors 2 and 4 being located in the lower plane and the transistors 1 and 3 in the upper plane.
  • the transistors 1 and 3 are separated from the underlying transistors 2 and 4 by a thin electrically insulating layer of, for example, silicon dioxide.
  • the main region 13 of the transistor 1 overlaps the underlying channel region 25 of the transistor 2 and the main region 33 of the transistor 3 overlaps the underlying channel region 45 of the transistor 4.
  • the main region 23 of the transistor 2 extends under the channel region 15 of the transistor 1, and the main region 43 of the transistor 4 extends under the channel region 35 of the transistor 3. Within the region of these overlaps the transistors are separated merely by the thin insulating layer.
  • the potential of that main region of one of the transistors in each crossing pair which overlaps the channel region of the other transistor will therefore, like a conventional control electrode of a field effect transistor, influence the conductivity of the latter transistor.
  • a negative potential of the main region 13 in relation to the potential of the transistor 2 will cause a conducting channel to be formed in the channel region 25 of the transistor 2 between its main regions, i.e. the transistor 2 is brought into conducting state.
  • a negative potential of the main region 23 of the transistor 2 will bring the transistor 1 into conducting state.
  • a positive potential of the main region - 33 or 43 - of one of the transistors leads to a conducting channel being induced in the channel region of the other transistor, i.e. the latter transistor is brought into conducting state.
  • the transistors 1 and 3 are connected, in series with each other, between two supply voltage connections 5 and 6.
  • the connection 5 is intended for the supply of a positive direct voltage in relation to the voltage of the connection 6.
  • the transistors 2 and 4 are connected, in series with each other, betweeen the two supply connections mentioned.
  • the main regions of the transistors are provided with metal contacts 12, 14, 22, 24, 32, 34, 42, 44.
  • the point of connection between the transistors 1 and 3 is connected to a signal connection 7 which constitutes the control input of the circuit.
  • the point of connection between the transistors 2 and 4 is connected to a signal connection
  • the signal (potential) at the connection 7 is designated B and the signal (potential) of the connection 8 is designated B.
  • Figure 2 shows a symbolic circuit diagram of the circuit shown in Figure 1.
  • the diagram shows the transistors 1, 2, 3, 4 and how the transistors are connected to the connections 5, 6, 7, 8. It further shows how a main region (e.g. 23) of a transistor (2) functions as a control electrode for another transistor (1) .
  • the function of the circuit is as follows. If the assumption is made that the signal B is "high", i.e. positive, the region 33 will induce a conducting signal in the underlying part of the channel region 45 of the transistor 4. The connection 8 and the signal B then become "low” (negative) .
  • the region 23 of the transistor 2 also becomes negative and induces a signal in the overlying channel region 15 of the transistor 1. This transistor then becomes conducting and locks the connection 7 and the signal B in a "high" position. The circuit has now assumed a stable position and remains in this position as long as no negative signal is applied to the connection 7.
  • the conducting channel in the transistor 4 is turned off and the transistor becomes non-conducting.
  • the region 13 of the transistor 1 also becomes negative and induces a channel in the channel region 25 of the transistor 2.
  • the transistor 2 is now conducting and the transistor 4 non-conducting, and the signal B therefore becomes "high” (positive) .
  • the region 43 of the transistor 4 also becomes positive and induces a conducting channel in the channel region 35 of the transistor 3, which becomes conducting.
  • the signal B is thereby locked in a "low” position.
  • the circuit has now assumed the second of its both stable positions and remains in this position until a "high" (positive) signal is applied to the connection 7.
  • connection 7 is used for control of the circuit.
  • connection 8 may just as well be used for this purpose.
  • the position of the circuit may be read out by sensing the voltage at any of the signal connections 7 and 8. If desired, one and the same signal connection may possibly be used both for control of the circuit and for reading out the position of the circuit, in which case the second signal connection may be left unconnected.
  • FIG. 3a shows the surface of a substrate, included,in an integrated circuit, with a bistable circuit according to the invention.
  • Figure 3b shows the in the form of a perspective sketch how the four transistors of the circuit are arranged in two separate planes.
  • the transistors 2 and 4 are arranged in a lower silicon layer with their regions 21, 25, 23 and 41, 45, 43, respectively.
  • the transistors 1 and 3 are arranged in an upper silicon layer with their regions 13, 15, 11 and 31, 35, 33, respectively.
  • the two silicon layers are separated by a thin electrically insulating layer of silicon dioxide (not shown in Figure 3b) .
  • the transistors are arranged in pairs in an L- shape and in such a way that the main regions 13, 23, 33, 43 overlap the channel regions 25, 15, 45 and 35, respectively.
  • Figure 3a shows a metal contact 51 which is connected to the main regions 11 and 21 and connects these regions to the supply connection 5.
  • a metal contact 61 is shown which is connected to the regions 31 and 41 and connects these regions to the supply connection 6.
  • a metal contact 71 is arranged in contact with the adjoining regions 13 and 33 and connects them to the signal connection 7.
  • a metal contact 81 is connected to the adjoining regions 23 and 43 and connects them to the signal connection 8.
  • the contacts just mentioned are not shown in Figure 3b.
  • the surfaces 71a and 81a which constitute the contact points of the contacts 71 and 81 with the semiconductor layers are shown in Figure 3b (dashed lines) .
  • the contacts there short- circuit the PN-junctions between the regions 13, 33 and 23, 43, respectively.
  • Figure 3c shows a section through the circuit at the location marked C-C in Figure 3a.
  • ' Figure 3d shows the section marked D-D in Figure 3a.
  • the circuit according to the invention is arranged on an electrically insulating base 100. This may, for example, consist of a silicon dioxide layer produced on a silicon substrate. On top of this layer that silicon layer is arranged in which the transistors 2 and 4 are formed. Of these transistors Figure 3c shows the channel region 25 of the transistor 2 and Figure 3d the regions 41, 43 and 45 of the transistor 4 as well as the region 23 of the transistor 2.
  • the silicon layer is transformed into silicon dioxide, for example by the supply of oxygen and heat treatment.
  • This silicon dioxide layer is designated 101.
  • a thin silicon dioxide layer 102 is applied. This layer separates the upper silicon layer from the lower and fulfils the same function as the so-called gate oxide in a conventional field effect transistor.
  • a second silicon layer is arranged in which the transistors 1 and 3 are produced.
  • Figure 3c shows the regions 11, 15, 13 of the transistor 1 and the region 33 of the transistor 3
  • Figure 3d shows the region 35 of the transistor 3.
  • the upper silicon layer outside the region constituting the transistors 1 and 3, is transformed into a silicon dioxide layer 103.
  • an additional silicon dioxide layer 104 is applied.
  • Figure 3c shows how the metal contact 71 is connected to the regions 33 and 13 and the contact 51 to the region 11.
  • Figure 3d shows how the metal contact 61 is connected to the region 41 and the metal contact 81 to the regions 43 and 23.
  • the two silicon layers in which the transistors of the circuit are produced may, for example, have a thickness of 30-40 nm.
  • the silicon dioxide layer 102 may have a thickness of 20 nm.
  • the length and width of the main and' channel regions of the transistors may be 0.1-10 ⁇ m.
  • the dimensions and the thicknesses must, of course, be adapted to the desired voltage level and current handling capacity and the technical possibilities of defining small dimensions.
  • those main regions of the transistors which are connected to the supply connections overlap the channel region of the other transistor in each pair of crossing transistors. If desired, this overlap may be omitted.
  • a semiconductor device which, at the bottom, has a substrate consisting of a silicon wafer with a silicon dioxide layer lying on top of the substrate.
  • a first silicon layer with a thickness of 30-40 nm
  • a thin silicon dioxide layer with a thickness of 10-20 nm
  • a second silicon layer with a thickness of 30- 40 nm.
  • that silicon layer which is located nearest the substrate may first be formed and, by suitable doping, the transistors arranged in that layer be produced. Thereafter, the intermediate oxide layer 102 may be produced, whereupon the upper silicon layer is formed and the transistors arranged in that layer are produced in a corresponding manner.
  • a bistable semiconductor circuit according to the invention has a simple configuration and may be given small dimensions. Since the transistors overlap each other, they take up a considerably smaller area than conventional circuits. This makes possible a higher packing density during the manufacture of integrated circuits which contain a plurality of bistable circuits. In a known manner, this high packing density provides considerable practical and economic advantages.
  • additional circuits may be arranged in a layer on top of the bistable circuit according to the invention.
  • a transmission gate for signals to and from the circuit may be arranged on top of each bistable circuit and separated therefrom by an electrically insulating layer. This makes possible an additionally increased packing density.

Landscapes

  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention se rapporte à un circuit à semi-conducteurs intégré bi-stable qui comprend quatre transistors à effet de champ (1, 2, 3, 4), deux (1, 2) de type P et deux (3, 4) de type N. Ce circuit porte des connexions (5, 6) pour une tension d'alimentation, entre lesquelles les transistors sont connectés en série par paires, chaque connexion en série comprenant un transistor de type P et un transistor de type N. Les points de connexion des transistors sont connectés à des connexions de signaux (7, 8). Les transistors de type P (1, 2) sont connectés à la connexion d'alimentation positive (5) et les transistors (3, 4) de type N sont connectés à la connexion d'alimentation négative (6). Les deux transistors de type P (1, 2) sont disposés à des niveaux différents et sont séparés par une mince couche électro-isolante. Cette région principale (13 et 23 respectivement) de chaque transistor qui est connectée à une connexion de signaux, chevauche la région canal (25 et 15, respectivement) de l'autre transistor. Les deux transistors de type N sont disposés selon un mode correspondant. En appliquant une tension positive à une connexion de signaux (7), on amène le circuit dans l'une de ses deux positions stables, tandis que les transistors (1 et 4) sont à l'état conducteur et que les transistors (2 et 3) sont à l'état non conducteur. En appliquant une tension négative à une connexion de signaux, on amène le circuit dans l'autre de ses deux positions stables, tandis que les transistors (2 et 3) sont à l'état conducteur et que les transistors (1 et 4) sont à l'état non conducteur.
PCT/SE1990/000695 1989-11-09 1990-10-26 Circuit a semi-conducteurs integre bi-stable WO1991007781A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE8903763-4 1989-11-09
SE8903763A SE464950B (sv) 1989-11-09 1989-11-09 Bistabil integrerad halvledarkrets

Publications (1)

Publication Number Publication Date
WO1991007781A1 true WO1991007781A1 (fr) 1991-05-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE1990/000695 WO1991007781A1 (fr) 1989-11-09 1990-10-26 Circuit a semi-conducteurs integre bi-stable

Country Status (3)

Country Link
AU (1) AU6757590A (fr)
SE (1) SE464950B (fr)
WO (1) WO1991007781A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998005075A2 (fr) * 1996-07-26 1998-02-05 Telefonaktiebolaget Lm Ericsson (Publ) Composant a semi-conducteur a caracteristiques courant/tension lineaires

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0252999A1 (fr) * 1986-07-09 1988-01-20 Deutsche ITT Industries GmbH Circuit CMOS à commande d'horloge comportant au moins un interrupteur CMOS
EP0331063A1 (fr) * 1988-02-29 1989-09-06 Asea Brown Boveri Ab Commutateur MOS à deux directions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0252999A1 (fr) * 1986-07-09 1988-01-20 Deutsche ITT Industries GmbH Circuit CMOS à commande d'horloge comportant au moins un interrupteur CMOS
EP0331063A1 (fr) * 1988-02-29 1989-09-06 Asea Brown Boveri Ab Commutateur MOS à deux directions

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998005075A2 (fr) * 1996-07-26 1998-02-05 Telefonaktiebolaget Lm Ericsson (Publ) Composant a semi-conducteur a caracteristiques courant/tension lineaires
WO1998005075A3 (fr) * 1996-07-26 1998-03-05 Ericsson Telefon Ab L M Composant a semi-conducteur a caracteristiques courant/tension lineaires
US5886384A (en) * 1996-07-26 1999-03-23 Telefonakitebolaget Lm Ericsson Semiconductor component with linear current to voltage characteristics

Also Published As

Publication number Publication date
SE8903763D0 (sv) 1989-11-09
SE8903763L (sv) 1991-05-10
AU6757590A (en) 1991-06-13
SE464950B (sv) 1991-07-01

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