WO1990012367A1 - Systeme d'imagerie de champ a centrage automatique et a compression d'image - Google Patents

Systeme d'imagerie de champ a centrage automatique et a compression d'image Download PDF

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Publication number
WO1990012367A1
WO1990012367A1 PCT/US1990/001953 US9001953W WO9012367A1 WO 1990012367 A1 WO1990012367 A1 WO 1990012367A1 US 9001953 W US9001953 W US 9001953W WO 9012367 A1 WO9012367 A1 WO 9012367A1
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WO
WIPO (PCT)
Prior art keywords
raster
frame
image
imaging surface
data
Prior art date
Application number
PCT/US1990/001953
Other languages
English (en)
Inventor
Suhas S. Patil
Chester Floyd Bassetti, Jr.
Dayakar Chandrum Reddy
Original Assignee
Cirrus Logic, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cirrus Logic, Inc. filed Critical Cirrus Logic, Inc.
Publication of WO1990012367A1 publication Critical patent/WO1990012367A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0421—Horizontal resolution change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0464—Positioning
    • G09G2340/0471—Vertical positioning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0464—Positioning
    • G09G2340/0478—Horizontal positioning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0464—Positioning
    • G09G2340/0485—Centering horizontally or vertically
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/04—Display device controller operating with a plurality of display units

Definitions

  • This invention pertains to the field of raster image systems and relates more particularly to the field of raster image systems for driving display, hardcopy or other graphical output devices such as used for displaying photographs, printing, imaging or otherwise outputting as a two-dimensional image text, diagrams, graphs and pictures.
  • CTR's cathode ray tubes
  • LCD's liquid crystal displays
  • the chip SED 1341 F QE requires 40K bytes of memory to work with 640 times 480 display (Page 38, Technical Reference Manual SED 1341 F QE ).
  • An example of a suitable LCD for use in the present invention is the model LM640487Z sold by the Elecom Group of the Sharp Corporation.
  • centering of an image on the imaging device required altering the characteristics of raster data from the source or the use of flexible imaging devices, such as CRT's with multisync capabilities.
  • Currently available flat panel displays, such as LCD's have no such flexibility.
  • the control of image position was dependent on ensuring the proper positioning of horizontal and vertical synchronization signals.
  • the present invention provides for driving a multisegment raster imaging device employing the invention disclosed in copending patent application.
  • the present invention is particularly useful when used with the grayscale shading techniques disclosed in copending application Serial Number 07/335,622, filed April 10, 1989, titled “Method And Apparatus For Producing Perception Of High Quality Grayscale Shading On Digitally Commanded Displays", assigned to the same assignee as the present application. That application is incorporated herein by reference.
  • the present invention provides a design with sufficient speed so that dynamic random access memories (DRAMS), which are less expensive but slower than static random access memories (SRAMS), can be used as buffer memory.
  • DRAMS dynamic random access memories
  • SRAMS static random access memories
  • the present invention applies multiple transformations on an input stream of raster data for increased speed of operation and superior results from applying the transformation even in the context of the data compression and double-stream output requirements described above.
  • the present invention is capable of automatically centering a raster image of arbitrary height on the imaging device. This is accomplished using multiple-state-machine- based control for flexibility in altering and adapting the design, and for performing the above functions in one integrated system.
  • the present invention also provides for image compression, where a stream of raster data describing an image that is larger horizontally than the imaging device can be compressed to fit into the desired area.
  • Figure 1 is a block diagram showing a graphics display system in which this invention may be employed;
  • Figure 2 is a diagram showing the functioning of the invention in processing a single stream of raster image data;
  • Figures 3a-3d illustrate the operation of the invention in providing image centering
  • Figures 4a-4c show the operation of the invention in providing image compression
  • FIG. 5 is a block diagram of the preferred embodiment for carrying out the present invention.
  • FIGS. 6-8 are block diagrams showing different elements of the logic circuitry utilized in this invention.
  • Figures 9-11 are state machine diagrams showing the operation of different techniques of the invention.
  • FIG. 1 there is shown the portion of a system for employing Video Graphics Array (VGA) graphics in connection with an IBM PC/AT or PC/XT or equivalent computer system.
  • the system includes a host bus 21 which acts as an interface between the host computer (not shown) and the VGA graphics portion. Address information is supplied on an address bus to address decode logic 22 whose output is supplied as one input to a sequencer/CRT controller 23. Sequencer/controller 23 communicates with a graphics attribute controller 24 through two buses identified as S/C-G/A control and I/O control.
  • VGA Video Graphics Array
  • Elements 23 and 24 may be of the type shown and described in the publication entitled "CL-GD 610/620 CRT/Flat Panel Enhanced VGA Controller” Preliminary Data Sheet, March, 1989, published by Cirrus Logic, Inc., Milpitas, California. This publication is incorporated herein by reference.
  • the system of Figure 1 includes an 8 or 16 bit data bus which conveys data to and from host interface 21 through a data buffer 26.
  • An additional address bus is connected to a buffer 27 which communicates with sequencer/controller 23 and a random access memory-digital- to-analog converter (RAMDAC) 28.
  • the system also includes a plurality of oscillators 29 for providing different frequency clock signals, as is well known in the art.
  • a Basic Input Output System (BIOS) ROM 31 is employed to store the VGA BIOS information. ROM 31 receives address control signals from element 23 through a bus 23a and supplies ROM output data on a bus 31a.
  • the ROM address information on bus 23a is utilized in accordance with the teachings of the present invention, as will be described in detail below.
  • the system of Figure 1 further includes a 1/2 frame dynamic random access memory (DRAM) buffer 32 connected to the graphics attributes device 24 and employed in generating raster imaging information for use in imaging frames of information on raster type devices such as a liquid crystal display (LCD) 33, a plasma panel 34, an EL panel 36, a printer, or a digital or analog cathode ray tube (CRT) represented by digital and analog monitors 37 and 38, respectively.
  • DRAM 1/2 frame dynamic random access memory
  • Half frame buffer memory 32 is preferably utilized in the manner taught in copending application Serial Number 07/334,059, filed April 4, 1989, titled "Converter For Raster Image Data From Single-Segment to Multi-Segment Streams" and assigned to the same assignee as the present application.
  • the system of Figure 1 also includes a dynamic random access memory represented by DRAMs 39 for storing raster imaging information supplied from the host system to element 23 through the 8/16 bit data bus and for supplying the stored information to one or more of the raster imaging devices.
  • DRAMs 39 for storing raster imaging information supplied from the host system to element 23 through the 8/16 bit data bus and for supplying the stored information to one or more of the raster imaging devices.
  • the present invention is a part of the graphics attribute controller 24. Its function is shown in Figure 2.
  • Other circuitry in the graphics attribute controller provides the present invention with a source of raster image data in a single stream.
  • the present invention transforms, optionally compresses and optionally centers the image data before passing it on to a raster imaging device.
  • a raster data stream consists of a temporal sequence of frames, where each frame consists of a vertical sequence of horizontal lines and where each line consists of a sequence of pixels (i.e. picture elements).
  • Figure 3a shows a typical raster data stream generated for producing images on devices such as TV monitors, video displays or computer terminals. Each dot represents one pixel time.
  • the data stream (shown as a thick line) describes the visual characteristics (color and/or intensity) of each pixel.
  • the timing signals V Sync and H Sync mark the start of a frame and the start of a line, respectively.
  • the source of raster data determines the parameters of the raster data stream such as the total number of lines in the frame (Vertical Total or VTL), the total number of pixel times in a line time (Horizontal Total Lines or HTL), the number of lines containing valid data to be displayed (Vertical Display Lines or VDL), the number of pixels of displayed data in a line (Horizontal Display Pixels or HDP), the location of the start of the first displayed line (Vertical Data Start or VDA) , with respect to V Sync and the number of Pixel times between the H Sync signal and the first pixel in the line (Horizontal Data Start or HDS) . These parameters may vary from image to image and application to application.
  • Imaging devices such as the multisync CRT, are flexible with respect to the number of image lines and the number of image pixels that the imaging device can work with.
  • Other imaging devices such as a flat-panel LCD display as used in a lap-top computer, have a fixed format; each make and model may have a unique and inflexible set of parameters such as total lines displayed, total pixels in a line, location of the first displayed line in a frame and location of first displayed pixel in a line.
  • Figure 3b shows how this data stream might look on such an LCD panel.
  • the one blank line at the top (shown as a thin line) corresponds to the one data-less line at the top of Figure 3a.
  • Figure 3c shows how one would like this raster data to be displayed on the LCD; viewers may prefer a vertically and horizontally centered image.
  • the display picture is centered without the need to alter the input video data.
  • Figure 3d shows the temporal sequence that must occur for the raster data to be displayed centered in both dimensions.
  • the LCD imaging device must start each line prior to the end of the previous line (as defined by H Sync), and must start each frame prior to the end of the previous frame (as defined by V Sync).
  • the basis of the invention is to synchronize with respect to the start or the end of the display data, not with respect to the timing signals H Sync and V Sync.
  • the preferred embodiment described herein implements only automatic vertical centering. Nevertheless, the invention claimed herein can realize both horizontal and vertical centering.
  • the preferred embodiment does not make use of the V Sync timing signal. Its current dependence on H Sync for centering purposes could be removed by the same technique as is applied to remove dependence on V Sync.
  • interfacing from typical raster data to an imaging device with a fixed number of pixels sometimes requires compressing of the image.
  • Figure 4a shows an image that is too wide for the display lines shown in Figure 4c.
  • Figure 4b shows the image broken into pixels. The missing dots in Figure 4b show how by taking every ith pixel and omitting it, or merging it with its neighbor, the image can be compressed to fit the display device with loss of visual quality that may be acceptable to the viewer.
  • FIG. 5-11 The preferred embodiment of this invention is shown in Figures 5-11.
  • This embodiment employs DRAMS for frame buffer storage.
  • the DRAMS are used in a page-mode read- modify-write manner of operation for achieving superior speed of operation for a given choice of technology.
  • the block diagram of Figure 5 shows the logic of the entire embodiment as well as the data-flow.
  • the details of the Address Counters and Control Logic block Bl of Figure 5 are shown in Figures 6-11.
  • An explanation of the operation of the diagram of Figure 5 is as follows.
  • Data transformations on the single-stream raster data input (such as converting color data to black and white data or controlling pixel intensities to achieve the effect of a half-tone picture on a digital imaging device) are performed by Data Transforms Tl and T2.
  • Transform Tl affects the data that goes directly to the two-segment imaging device.
  • Transform T2 affects the data that goes to the imaging device after being stored in the DRAM memory Ml.
  • a number K of Data Transforms similar to elements 41 and 42 are required.
  • these transformation functions can depend on a number of parameters, accept the Single-Stream Raster Data data signals in various data widths, and produce outputs of various widths.
  • the specific Data Transforms Tl and T2 of the preferred embodiment generate gray-shades control and depend on the row and column locations of the pixel in a frame and the serial number of the frame. They receive as input the timing signals ShiftClock, LineClock,
  • Each of Data Transforms Tl and T2 produces a single-bit-wide output to meet the requirements of a class of digitally controlled LCD panels such as those manufactured by Sharp and Epson.
  • Tl produces a data stream describing the double-segment raster frame 2i
  • T2 produces a data stream describing the frame 2i+l.
  • Each of the shift registers SRI and SR2 is clocked by the Pixel Clock timing signal ANDed with the SkipData control signal.
  • the SkipData control signal implements the requirement for data compression. Any pixel data that appears on the single-stream raster input when SkipData is ⁇ is either ignored or merged with the next pixel.
  • Shift registers SRI and SR2 assemble a four-bit word which represents data for four adjacent pixels from the output of Tl or T2, respectively.
  • the 4-bit output of the shift register SRI goes to the 0 input of the selector SU as well as to the 1 input of the selector SL.
  • the output of the shift register SR2 goes to the data input of the 4-bit register Rl.
  • Register Rl is clocked by the timing signal Shift Clock, which is produced by Address Counter and Control Logic block Bl.
  • the Shift Clock timing signal operates at a rate 1/4 that of the Pixel Clock timing signal. It provides the timing to handle 4 pixels of data at a time for each of the two segments within a frame.
  • Register Rl loads the output of shift register SR2 at the right time (as defined by the Shift Clock timing signal) and holds this value as a constant input to tristate buffer TB1 while shift register SR2 is assembling the next 4 pixels of data.
  • the ShiftClock timing signal also clocks registers RU and RL which receive their data from selectors SU and SL, respectively, and output the double-stream raster data to the double-segment display device. Registers RU and RL are reset by the timing signal LineClock.
  • Bidirectional bus DI sends data to DRAM memory Ml and receives data from this memory.
  • Tristate Buffer TB1 supplies data on bidirectional bus DI when the Data Out control signal (generated by block Bl) is 1.
  • DRAM memory Ml supplies data on bus DI only when the control signal oe (NOT output enable generated by block Bl) is a 0.
  • Block Bl also produces the bus Address and the control signals ras (NOT row address), cas (NOT column address), and we (NOT write enable) for operating DRAM memory Ml in the desired mode.
  • Bus IO-bus is an input/output bus which provides the software read/write mechanism for the ROR, RSTR, COR and CTR registers.
  • the IO-bus has eight address lines R address, eight data lines R data, a write control line R write, and a read control line R read.
  • block Bl receives as input the timing signals Pixel Clock, V Sync, H Sync and Display Enable as well as the control signals Reset, AutoCnEn (auto centering enable) and SkipData.
  • Block Bl uses these input signals to keep track of the position of the pixel for which data is being received, both with respect to the two-dimensional position of the current pixel within a frame and with respect to the temporal position of the current frame in the series of frames.
  • Block Bl contains logic circuits to maintain row count, column count and frame count and to produce the desired address and control signals as required by DRAM memory Ml.
  • the present invention combines both automatic control of the vertical centering operation and software-specified parameters and control.
  • This software control (which is typically exercised by the Video BIOS) is usable both to adapt the invention to different display or imaging devices and to vary the display or image on a particular device.
  • the software control is realized by the AutoCnEn control signal as well as the parameters Row Offset, (RO), Column Offset (CO), Row Segment Total (RST), and Column Total (CT).
  • the software When auto-centering is disabled by the AutoCnEn control signal, the software has direct control over the vertical position of the image on the imaging surface. Increasing the value of the Row Offset parameter by one moves the image up one line on the imaging surface (assuming the imaging device produces lines from top to bottom).
  • the present invention detects how many displayed lines are in the current image and, from that information, computes the required value of the offset parameter that specifies how far down the display surface the image should start. In the next frame, the image is offset appropriately.
  • the Row Offset parameter is not ignored when auto-centering is active; rather it is loaded by the software with a value that is independent of image size, but that can still be used to adjust the exact position of the image on the surface.
  • the software has direct control over the horizontal position of the image on the imaging surface. Increasing the value of the Column Offset parameter moves the image right one pixel on the imaging surface (assuming the imaging device produces pixels from left to right) .
  • the Row Segment Total (RST) parameter must be set to the number of rows or lines in each of the two segments of the display, i.e. RST must be 240 for a two-segment LCD panel of 480 lines.
  • the Column Total (CT) parameter must be set to the number of columns in the imaging device divided by 4 (which is the number of Shift Clock timing signals that are required to handle one line of raster data). Any values of the RST or the CT parameter that does not correspond to the display or imaging device being used may result in an ill-formed image, and possibly an unstable image.
  • Block Bl also generates the control signal
  • Bl generates the timing signals Shift Clock, Line Clock and Frame Clock as required by the two-segment imaging device.
  • the preferred embodiment of the Address Counters and Control Logic block Bl is shown in the logic diagrams of Figures 6-8 and the state machine diagrams of Figures 9-11.
  • ROR row offset register
  • RSTR row segment total register
  • COR column offset register
  • CTR columnur ⁇ i total register
  • RCtr and CCtr are row and column counters.
  • NCtr is a counter used in realizing vertical (row) offset and vertical centering. All three counters are loadable and decrementing counters.
  • Each of the counters has feedback logic that disables the counter from decrementing any further when its value reaches 1 or 0: counters NCtr and RCtr stop at a value of 1 or 0: (i.e. decrementing is disabled until another value is loaded into the counter).
  • Each of the three counters is reset to 0 when the Reset signal is a 1.
  • Each counter performs a synchronous load of its value from its D input bus at the rising edge of its elk input when its Id input is a 1.
  • Tristate buffers TB/2, TBN and TBR select what data is loaded into the counter NCtr: if the control signal NCtr ⁇ -RO is a 1, then the counter receives the value RO put into it; if the control signal NCtr ⁇ -RST is a 1, then the counter gets the value RST; and if the control signal NCtr ⁇ -NCtr+2 is a 1, then the counter receives a value that is half the value of NCtr. To avoid a conflict, at most one of the control signals NCtr ⁇ -RO, NCtr ⁇ -RST and NCtr ⁇ -NCtr+2 is a 1 at any given time.
  • Tristate buffers TBC1 and TBC2 select the value that is loaded into the counter CCtr when ld-CCtr is a 1: If control signal CCtr ⁇ -CO is a 1, then the counter CCtr gets loaded with the value CO; and if the signal CCtr ⁇ -CT is a 1, then the counter CCtr gets loaded with the value CT. To avoid conflict, both CCtr ⁇ -CO and CCtr ⁇ -CT are never 1 at the same time.
  • Counters NCtr and RCtr are clocked by a synchronizing signal called RowClk which occurs once every line.
  • RowClk is the same as the H Sync signal. In other embodiments it could either be directly supplied to the control block Bl or be derived from the Display Enable Signal if it is an integrated signal encoding both display enable and horizontal sync functions.
  • Figures 9, 10, and 11 show state diagrams for the three state machines that provide control signals needed in the logic circuit of Figures 6, 7 and 8.
  • Figure 9 shows the Vertical Centering/Offset State Machine
  • Figure 10 shows the Row State Machine
  • Figure 11 shows the Column State Machine. A description of the state machines and the operations that they control follows.
  • the Vertical/Centering/Offset State Machine and the Row State Machine control the operation of the system during one frame of operation. Different states of these machines correspond to different phases of the raster frame.
  • the Vertical Centering/Offset State Machine provides the Row State Machine with the RowBegin signal, which is true when the Vertical Centering/Offset State Machine is in state NsO and the NCtr is at a value of 1 or 0. Also, the Vertical Centering/Offset State Machine, in conjunction with the NCtr counter, determines the row of the single- segment raster data input at which to start the two-segment raster output data so as to center the image on the two- segment display. If the AutoCnEn signal is a 0, then this state machine does not perform the auto centering function, but it still causes the image to be offset by the Row Offset parameter.
  • the Reset signal resets the Vertical Centering/Offset State Machine to state NsO.
  • This state machine then waits for the FirstDE control signal to become 1, at which time it makes a transition to the state Nsl, and in so doing causes RST to be loaded into the NCtr.
  • the NCtr counter decrements by 1 until it reaches the value 1.
  • this state machine makes a transition Ntl to state Ns2, and once again loads the NCtr with the value RST.
  • the value that remains in the NCtr when the FirstWithoutDE becomes a true signal is computationally equal to the difference between the sum of lines in the two segments in the two segment display and the number of lines in the image to be displayed.
  • the state machine makes a transition Nt3 to state Ns3. In so doing, it loads counter NCtr with a value that is half its value at the time of the transition. This value provides the additional lines by which the start of the two-segment output raster data is to be offset from the last line for which the
  • Display Enable has a true value.
  • Transition Nt4 is taken when the NCtr reaches the count 1 and during this transition the NCtr counter is loaded with the value RO. The counter NCtr then counts down to the value 1 and waits for a new cycle of operation of the state machine to begin.
  • a typical value for the Row Offset parameter is one less than the difference between the total lines in the single-segment raster data stream and the total lines in the two-segment imaging device. Increasing (decreasing) the value in RO by 1 causes the image to move up (down) by one line (if the device images lines from top to bottom).
  • the Row State Machine ( Figure 10) controls the row lines in the two-segment imaging device.
  • State RsO is the idle state in which the imaging device does not get the signals required to form any image.
  • state Rsl the upper segment gets the data directly.
  • state Rs2 the lower segment gets the data directly.
  • the signal Reset sets the Row State Machine to idle state RsO.
  • this state machine waits for the RowBegin signal from the Vertical Centering/Offset State Machine.
  • this state machine detects a 1 on RowBegin, it loads RCtr with the value RST and makes a transition to state Rsl.
  • the RCtr counter then decrements at each falling edge of the RowClk until the value 1 is reached, at which time the Row State Machine makes a transition to state Rs2 and loads the counter RCtr with the value RST. Once again the RCtr counter decrements for each RowClk until its value is 1.
  • the Row State Machine makes a transition to state RsO.
  • the Row State Machine then waits for the RowBegin signal to become true again to begin a new cycle of operation.
  • the Column State Machine ( Figure 11) controls the operation of the system during one line of operation. Different states of the Column State Machine correspond to different phases of the raster line. State CsO is the idle state and corresponds to the horizontal retrace time. During this time, the DRAM in memory Ml is given signals to perform a cas-before-ras refresh operation controlled by the counter PhCtr. In this mode of refresh operation, the cas signal is set to active low and the ras cycles between active and inactive state. The Column State Machine goes through the operation only when the RowOper signal is 1. The RowOper signal is supplied by the Row State Machine.
  • PhCtr, ras is inactive and a change in the state of the Column State Machine here avoids marginal signals being generated on ras which could affect the integrity of the data stored in the DRAM memory Ml.
  • the Column State machine waits for the display enable signal DE to become true, at which time it makes transition Ctl and in so doing loads the counter CCtr with the value CO (column offset value) and resets the phase counter PhCtr.
  • the counter CCtr counts down by 1 until it reaches the value 0, at which time the Column State Machine transitions by way of state Ct2 to state Ct3 (the ColOper phase).
  • the single-stream raster input data moves through the data paths shown in Figure 1 and is both directly supplied to one segment of the two-segment imaging device and stored in the DRAM memory Ml, while the other segment receives the raster data that is read out from memory Ml.

Abstract

Un procédé de réglage du centrage vertical de cadres séquentiels d'une image de champ sur une surface d'imagerie de champ, consiste à détecter l'emplacement vertical de la dernière ligne de l'image de champ, dans le cadre précédant le cadre à régler; et à régler le début de l'image de champ du cadre réglé, sur la base de l'emplacement de la dernière ligne détectée (registre de décalage de rangées ROR; registre total de segments de rangées RSTR; compteur de rangées RCtr; compteur NCtr). L'invention concerne également le centrage automatique de l'image sur une surface d'imagerie, ainsi que la compression de l'image de champ.
PCT/US1990/001953 1989-04-10 1990-04-10 Systeme d'imagerie de champ a centrage automatique et a compression d'image WO1990012367A1 (fr)

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Application Number Priority Date Filing Date Title
US33638489A 1989-04-10 1989-04-10
US336,384 1989-04-10

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EP0607778A1 (fr) * 1993-01-05 1994-07-27 Nec Corporation Dispositif de commande d'un panneau d'affichage à cristaux liquides capable d'afficher des images de petite taille
EP0673153A2 (fr) * 1994-03-18 1995-09-20 Canon Kabushiki Kaisha Sytème d'affichage d'image
EP0609843B1 (fr) * 1993-02-01 1998-06-10 Nec Corporation Dispositif de commande d'un panneau d'affichage à cristaux liquides pour différentes tailles d'image
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EP0607778A1 (fr) * 1993-01-05 1994-07-27 Nec Corporation Dispositif de commande d'un panneau d'affichage à cristaux liquides capable d'afficher des images de petite taille
US5442372A (en) * 1993-01-05 1995-08-15 Nec Corporation Apparatus for driving liquid crystal display panel for small size image
EP0609843B1 (fr) * 1993-02-01 1998-06-10 Nec Corporation Dispositif de commande d'un panneau d'affichage à cristaux liquides pour différentes tailles d'image
EP0673153A2 (fr) * 1994-03-18 1995-09-20 Canon Kabushiki Kaisha Sytème d'affichage d'image
EP0673153A3 (fr) * 1994-03-18 1996-08-28 Canon Information Syst Inc Sytème d'affichage d'image.
US5844568A (en) * 1994-03-18 1998-12-01 Canon Kabushiki Kaisha System for selectively extracting pixels from an image and for forming an abstract image by displaying the extracted pixels
US8073291B2 (en) 2007-10-17 2011-12-06 Seiko Epson Corporation Center based image resizer

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