Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/70—Masking faults in memories by using spares or by reconfiguring
  • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by group G11C11/00

Definitions

• the subject of the present invention is a method and a device for repairing an image memory of the type used in the medical field, in association with an image processor, for viewing high definition images (1024 X 1024 points ).
• These images are generally representative of prior clinical examinations carried out using tomographs, CT scanners, or nuclear magnetic resonance (NMR) machines.
• the invention can nevertheless find its application in other fields, where the simultaneous viewing of high definition images is necessary.
• a high definition image with one Mega image elements (1 Mega 1024 X 1024) or 1 Mega pixels, requires for its storage eight Mega memory cells if each of these memory cells contains a bit, and if brightness levels to be affected to the picture elements of this picture, are coded on eight bits.
• the storage of an image therefore requires the presence of integrated memory circuits in sufficient number for their cumulative capacities to be equal to eight Mega bits.
• the image memory of which it is question is of course a very quick memory. In current teohnology it is preferably dynamic and therefore volatile. This means that before using the image processor and this image memory, it is advisable to load this memory, in a prior operation, with corresponding image information stored on another medium: a magnetic disc for example .
• a magnetic disc for example.
• intermediate boards are used. These boards are of the printed circuit type and are of rectangular shape. On these boards one usually assembles side by side eight integrated circuits.
• the integrated circuits used are of rectangular shape. Either these integrated circuits are put side by side adjacent by their long sides to form an alignment which extends in the direction of the length of the rectangular plate. Either the integrated circuits are aligned end to end, by their short sides, and in this case they are in more implanted on both sides of the wafer. The wafers are then themselves skewered on edge on the motherboard of the processor.
• an integrated circuit can contain a Mega bits, from what we put eight on a wafer and thus a wafer corresponds to the storage of an image, and we want to make image processors with sixteen images, it is advisable to install on the motherboard sixteen plates placed side by side.
• the plates are erected on edge substantially against each other with minimum space between them. This minimum space is for example of the order of 0.5 mm. It is completely insufficient to allow the disassembly of an integrated circuit of these wafers without at the same time requiring removal of the wafer itself from the motherboard.
• the repair has a big drawback: the interposition of the connectors changes the size of the board above the motherboard.
• the plate thus repaired can no longer be slid between the other plates of the image memory of the image processor since it is now embellished with oversized components.
• the plate erected on edge protrudes above the level of the others due to the presence of its connector.
• the plates Given the compactness, the plates have a height such that they just subscribe to a standard of spacing between main cards of an electronic cabinet where the motherboard of the image processor is engaged.
• the result of this repair is that the new motherboard or the new board is no longer usable in the space which is too correctly calculated.
• the solution which consists in making spacings out of norms is not industrially acceptable because the problems of compatibility between the equipment which it poses disqualifies its use in large electronic assemblies. It is recalled in this regard that the manufacturing standards are binding on all designers. Their non-compliance leads to considerable delays in the final manufacture of the equipment sold on the market.
• the repair of image memories thus recommended is not without effect on the reliability of the final memory. Indeed, by having undergone welding and unsoldering operations, the structure of this image memory and therefore its reliability is altered in one way or another. In the invention, it is proposed to remedy this drawback drawback by proposing a completely different repair.
• the principle of the invention consists in making image processors with an image memory comprising an image memory capacity in excess compared to the nominal usage requirements. This excess capacity is used to replace the useful but defective parts of the image memory.
• an address transcoder is used which makes it possible to store in replacement areas of the memory, information which would normally be stored in other areas of the latter, which are known moreover to have malfunctions.
• the address transcoder is normally placed between an address generator, controlled by a microprocessor and the image memory. This means that the repair of the image memory becomes transparent to the user who continues to manage, via the microprocessor, this image memory.
• This procedure has the immediate result that the reliability of the image processor, or of the image memory thus produced is not affected by the repair.
• a study of faults has shown that image memories fail in 90% of cases due to a malfunction of a memory circuit cell. Consequently, by doing so, the failure rate of the entire image processor is divided by ten.
• the determination of the good operating condition of the elementary electronic integrated circuits of memory is carried out by a so-called recipe program.
• This recipe program is implemented by the microprocessor which manages the memory.
• This recipe program delivers a list of blocks or cells in this memory which are defective. It is with this list that repairs are normally carried out.
• the transcoder interposed between the address generator and the image memory is coded as a function of the result of this recipe: as a function of the content of this list. Consequently, a memory repair operation consists in putting the recipe program into service regularly, for example every three months.
• the immobilization of the image processor and the image memory during the course of this recipe program is of the order of 1 hour. It cannot be considered as a breakdown in the same way as that known in the state of the art where, for repairs with withdrawals and reconnections, the downtime was estimated in days or even weeks.
• the repair can in addition be carried out directly by the user who has only one software type procedure to be implemented. This user does not need to have any skill in repair technology.
• the image processor mounted with the method of the invention then has an MTBF (Medium Time of Good
• the subject of the invention is a method for repairing an image memory of an image processor, this memory comprising a set of memory modules pressed against each other, each module comprising a rectangular connection plate, of the printed circuit type, each plate being provided with a certain number of elementary electronic integrated circuits of memory,
• this processor comprising
• an address generator for accessing memory cells of a first partition of this memory, these memory cells of this first partition being loaded with information relating to image elements of a first image
• a reading circuit for reading information contents stored in said cells, a so-called recipe memory for storing a list of memory cells from the set of memory module image memory whose operation has previously been deemed to be defective, and
• an address coder characterized in that one performs
• FIG. 1 a block diagram of an image processor according to the invention capable of implementing the invented method
• FIG. 2 a schematic representation of the allocation of parts of an area in excess of the memory to corresponding parts of this memory having been found defective.
• FIG. 1 shows an image processor usable to implement the method of the invention.
• An image memory 1 to be repaired comprises, in a bank 2, memory modules such as 3 to 5.
• Each module comprises a connection plate of the printed circuit type, provided with a number of integrated circuits such as 6 to 9 electronic elementary memory.
• the modules are pressed against each other on edge above a so-called motherboard 10 so that the removal of integrated circuits 6 to 9 for their replacement is normally not possible, at least for pads that are not at the ends.
• bank 2 has 16 plates so as to contain 16 images.
• the image processor comprises an address generator 11 for accessing memory cells of a first partition of this memory, this first partition corresponding to one of the stored images.
• this first partition corresponding to one of the stored images.
• the image processor also includes a read / write circuit for reading information stored in the memory cells.
• This read circuit essentially comprises a control bus 12 by which the microprocessor 13 sends read and write instructions so that, via an address bus 14 and a data bus 15, the images to be represent are displayed on a monitor 16.
• the particularity of the invention lies in the presence of an address coder 17 intermediate between the address generator il and the image memory 1.
• This address coder 17 is in fact a transcoder. It receives addresses from memory cells of the image memory, to be read or written, coming from the address generator. If the addresses of the cells concerned are addresses which correspond to cells in good condition, the address coder lets them pass as they are. Consequently, the memory cells of the image memory which are thus addressed by the address generator are effectively those where the address generator had intended the information.
• the address coder 17 when it recognizes a defective address, transmits on the downstream bus 14 an address different from the one it received, and corresponding to a replacement memory cell whose address is associated.
• this address coder 17 has an address decoder at its input and a programmable random access memory at its output.
• the information content loaded at each address of this programmable random access memory of the address coder is, on the one hand the address itself if this address corresponds to a memory cell deemed to be in good condition of the memory of images or, on the other hand, an address of a replacement memory cell in the opposite case.
• the number of memory locations in the programmable memory of the address coder 17 must be 1 Mega, and the capacity of each of these locations must be 20 bits.
• addresses, called default, of memory bytes from the image memory which are defective are extracted from a recipe memory 18. These fault addresses are sent by the address generator 15.
• the content of the programmable memory located at these addresses is loaded with exactly the same information at these addresses.
• the address coder 17 is then able to play its role of rerouting, in read or write, memory cells of the image memory on the initiative of the address generator 15 controlled by the microprocessor 13.
• a group of bytes replacement by group of bytes is preferred.
• a group of bytes replacement by group of bytes is preferred.
• one is satisfied with a storage of 15 images and one reserves the capacity of the sixteenth image with the capacity of the groups of bytes of replacement.
• we will access all the bytes of a sixteenth of the image.
• the address decoder of the address coder 17 should no longer receive as address only eight-bit words and no longer contain in each of the 256 boxes of its corresponding programmable memory only eight-bit words.
• the eight address bits correspond, for the first four bits, to the choice of one image among the 16 possible, and for the next four bits, to four most significant bits of the addresses of the image elements of the chosen image.
• the programming of the address coder 17 is then as follows. We locate in a memory partition assigned to an image (we thus know the first four bits) a byte corresponding to a defective memory cell. Only the four most significant bits are retained from the address coded on 20 bits in this image of this defective byte.
• This program can be launched regularly, every 3 months for example, or from that a defect in the image memory has been detected by other means. These other means are for example the detection in the images of a local fault.
• the recipe memory 18 is therefore a non-volatile memory which makes it possible, at the cost of this additional duration of 1 second, to have an image memory 1 constantly repaired.
• the images are normally stored for a long time in a disk or magnetic drum unit 19. They are loaded when the need arises from this unit 19 into the image memory 1 using the address generator 15 coupled to the address coder 17. Therefore, for this member also the address transcoding is transparent.
• the image memory is not normally the memory which is read so that these images are viewed on the monitor 16.
• a viewing memory 30 is used, which is an integral part of the image memory 1 but in which are loaded according to the needs of the parts of memory modules of the image memory that one wishes to appear.
• the memory 30 of course has a capacity at least equal to the maximum resolution of the largest image that we want to see. In practice, it has at least 1 Mega bytes of capacity. We then realized that this display memory was also prone to breakdowns and that it was possible to apply the same reasoning to repair any deficiencies in this display memory 30. We were thus led to carry out a display memory of 2 Mega bytes of capacity when in fact only 1 Mega bytes are used.
• the addresses for storing, in the display memory are the addresses produced by the address generator 15 before their transcoding. If faults have been detected and if a replacement is to be made in the display memory 30, the address coder 17 includes, in addition, a part intended to perform the same function as above, but with regard to the memory of visualization this time.
• the address 14 and data bus 15 are managed by the microprocessor 13 in the same way as for the memory modules of the image memory.
• FIG. 2 schematically represents the memory capacity 20 of the image memory 1.
• This memory as indicated so far is divided into sixteen partitions, the sixteenth partition 21 being intended to serve as a repair partition.
• the implementation of the recipe program made it possible to store in the recipe memory 18 addresses of memory blocks 22 or 23 of the memory 2 which have been found to be defective.
• the address coder 17 comprises in its programmable memory a coding which makes it possible to assign to each of these blocks, for example block 24, a corresponding region 25 (surrounded by two lines) of the sixteenth partition 21.
• the Recipe program which also scans the sixteenth partition 21 can determine the presence in this sixteenth partition 21 of a bad block 26. Under these conditions it prohibits the use of this block 26 as a replacement.

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• Techniques For Improving Reliability Of Storages (AREA)
• For Increasing The Reliability Of Semiconductor Memories (AREA)

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Citations (2)

• 1989
  • 1989-03-31 FR FR8904302A patent/FR2645296A1/fr active Granted
• 1990
  • 1990-03-30 WO PCT/FR1990/000224 patent/WO1990012364A1/fr unknown

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