WO1989012940A1 - Recepteur de television - Google Patents

Recepteur de television Download PDF

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Publication number
WO1989012940A1
WO1989012940A1 PCT/JP1989/000592 JP8900592W WO8912940A1 WO 1989012940 A1 WO1989012940 A1 WO 1989012940A1 JP 8900592 W JP8900592 W JP 8900592W WO 8912940 A1 WO8912940 A1 WO 8912940A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
television
clock
aspect ratio
conversion
Prior art date
Application number
PCT/JP1989/000592
Other languages
English (en)
Japanese (ja)
Inventor
Masanori Hamada
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to KR1019900700290A priority Critical patent/KR930000952B1/ko
Publication of WO1989012940A1 publication Critical patent/WO1989012940A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
    • H04N7/0122—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal the input and the output signals having different aspect ratios

Definitions

  • the present invention relates to a television receiver for receiving a television signal having a different aspect ratio, such as a high-vision broadcast and a current broadcast (NTSC), and particularly to an NTSC signal.
  • a television receiver for displaying on a high-vision receiver.
  • a conventional television receiver is disclosed in, for example, Japanese Patent Application Laid-Open No. Sho 61-553386.
  • Fig. 2 shows the configuration of this conventional television receiver.
  • the NTSC system (A / P ratio: 5: 3) is used for the high-vision receiver (aspect ratio 5: 3). It is a television signal with a 4: 3) spectral ratio, which is projected by high-quality image processing (noninterlaced scanning conversion processing).
  • 11 is an NTSC signal input terminal with an aspect ratio of 4: 3
  • 12 and 13 are C with an aspect ratio of 5: 3.
  • An input terminal for the vision signal 14 is an NTSC decoder for demodulating the NTSC signal and outputting R, G, B signals and a synchronizing signal
  • 15 is a decoder for demodulating the R, G, B signals.
  • Noninterlacing processing circuit for converting to interlaced scanning 16 switches between the noninterlaced scanning converted signal and the high-vision signal RGB switching circuit for supplying CRT, 17 for switching the synchronization signal, deflection switching circuit for supplying CRT, 18 for NTSC signal with aspect ratio of 4: 3 and aspect ratio of 5 This is a 5: 3 aspect ratio CRT that displays a: 3 high-vision signal.
  • the operation of the television receiver configured as described above will be described with reference to FIG. 4 showing a display screen with an aspect ratio of 5: 3.
  • the NTSC decoder 4 demodulates the R, G, and B signals and the synchronization signal, and outputs the signal to the noninterlacing circuit 15. Supply.
  • the non-interlace processing circuit 15 is composed of a plurality of line memories, and performs horizontal time axis conversion processing and synchronous signal processing for non-interlace scanning conversion. .
  • the conversion of the time axis is to compress the horizontal time axis by a factor of 2 when displaying on a CRT with an aspect ratio of 4: 3, so that the signal processing clock of the NTSC decoder is 4 fsc ( If it is 4 times the subcarrier), write to line memory with a 4 fsc clock signal and read with 8 fsc clock signal.
  • reference numerals 150 and 151 denote line memories for time base conversion
  • 152 denotes a write clock signal generator for line memories 150 and 151
  • 153 is a read clock signal generator
  • 154 and 155 are write switches and read switches that switch every horizontal period, and the state switches every horizontal period.
  • the R signal output from the NTSC decoder 4 for example, the R signal is output via the write switch 15 54 of the noninterlacing circuit 15.
  • the R signal in one horizontal period is the write clock signal of the write clock signal generator 15 2 (4 fsc clock if the clock frequency of the signal processing of the NTSC decoder is 4 fsc). (Lock signal) to write to the line memory.
  • the horizontal signal for one horizontal period of the R signal written to the RGB is read twice consecutively, and this is supplied to the RGB switching circuit 16 as a non-interlace signal via the read switch 15 55 I do.
  • the write and read clock generators 15 2 and 15 3 are composed of PLL circuits and the like, and are controlled by NTSC signal synchronization signals.
  • the non-interlaced scan signal and the time-base-converted output signal of the aspect ratio in the non-interlaced processing circuit 17 pass through the RGB switching circuit 16 to the CRT 18 To be displayed.
  • the sync signal is not related to the aspect ratio. Regardless, the compression processing is doubled and supplied to the CRT 18 via the deflection switching circuit 17.
  • Fig. 4 shows the display status.
  • Figure 4 shows a CRT 18 with an aspect ratio of 5: 3 and a video signal with an aspect ratio of 4: 3 (NTSC signal is processed by non-interlacing and This shows the state in which (processed signal) is displayed. A is the rest.
  • the present invention has been made in view of the above circumstances and provides a television receiver having a simple processing circuit.
  • the present invention relates to a scan conversion method that performs time-base conversion processing of an interlaced scanning television signal and displays the non-interlaced image on a receiver having a different aspect.
  • a time axis conversion circuit for performing non-interlaced scan conversion and an aspect ratio conversion of the input input signal of the in-line scan method.
  • a first clock signal for generating a clock signal for performing write control of the time axis conversion circuit.
  • the second clock generator corresponds to one scanning line of the second clock generator. This is a television receiver characterized by having an even number of clocks.
  • the present invention converts the aspect ratio and the scanning line density of an NTSC television signal simultaneously with a simple circuit configuration to provide a high-resolution television signal of high quality. It is projected on a revision receiver.
  • FIG. 1 is a configuration diagram of a television receiver according to an embodiment of the present invention
  • FIG. 2 is a configuration diagram of a conventional television receiver
  • FIG. 4 is a configuration diagram of a scan conversion circuit in a television receiver
  • FIG. 4 is a diagram showing a display screen of a CRT having an aspect ratio of 5: 3.
  • FIG. 1 shows a configuration diagram of a television receiver according to an embodiment of the present invention.
  • the same components as those in the conventional example shown in FIG. 9 is a time base conversion circuit, 90 is a first clock generator for writing, and 91 is a second clock signal generator for reading.
  • the RGB switching circuit 6 and the deflection switching circuit 7 receive an input signal having an aspect ratio of 5: 3 as in the conventional case.
  • the signal is switched to be supplied to CRT 8 and the output signal is displayed on CRT 8.
  • the R signal output from the NTSC decoder is a non-interlaced scan conversion process and an aspect ratio conversion by a time axis conversion circuit 9 composed of line memory.
  • the control for writing to the line memory is performed by the clock signal of the first clock generator 90 for writing as in the conventional case.
  • the reading of the line memory is controlled by the clock signal output from the second clock generator for reading.
  • the frequency of the second clock signal is a clock signal having a cycle that takes into account the conversion of the aspect ratio and non-interlaced scanning.
  • the number of clocks in the horizontal unit near lO fsc is an even number, for example, 2275 at 22 fsc at 10 fsc becomes 2274 or 2276.
  • the frequency of the second clock signal of the second clock signal generator is set to be an even number and the conversion of the peak ratio is performed.
  • the clock frequency may be n or 3 ⁇ 2 n (n is an integer) and the roundness when a circle is displayed on the CRT is within an allowable range.
  • the aspect ratio is described as 5: 3, but the same processing is performed at 16: 9.
  • the conversion of the aspect ratio has been described using the R, G, and B signals. However, it is needless to say that a luminance signal and a color difference signal may be used.
  • the NTSC system television signal is improved in image quality by non-interlaced scanning conversion (the number of scanning lines is increased).
  • the CRT can be viewed at the same viewing distance as in the high-vision system.
  • the circuit can be simplified. And can be done.
  • the number of clock signals can be set to an even number as in this embodiment.
  • processing can be performed by a simple processing circuit (for example, parallel processing).
  • the present embodiment by setting the number of clocks per scan line of the read clock signal to an even number, it is possible to perform the flash processing with a simple processing circuit. Conversion and noninterlaced scan conversion can be performed.
  • the number of clocks per scanning line of a read clock signal is set to an even number, thereby enabling a simple processing circuit.
  • Spectral conversion and non-interlaced conversion can be performed.
  • the NTSC signal may be transmitted with an increased number of scanning lines by simply adding a simple circuit to the current high-definition television receiver. ⁇ Images can be viewed without any image loss due to differences in the cut-off ratio.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Graphics (AREA)
  • Television Systems (AREA)

Abstract

Des signaux NTSC (1) présentant un rapport largeur/hauteur égal à 4 : 3 sont reçus et envoyés à un décodeur NTSC (4), les signaux R, V et B ainsi que les signaux de synchronisation sont démodulés et envoyés à un circuit de conversion d'axes temporels (9), le traitement de conversion à balayage non entrelacé et le traitement de conversion de rapport largeur/hauteur sont commandés par des signaux d'horloge produits par un premier générateur de signaux d'horloge (90) pour l'écriture et par un deuxième générateur de signaux d'horloge (91) pour la lecture, et ce deuxième générateur de signaux d'horloge (91) pour la lecture règle sur un chiffre pair le nombre de signaux d'horloge pour une ligne de balayage, lit lesdits signaux et les visualise à l'écran d'un récepteur de télévision présentant un rapport largeur/hauteur égal à 5 : 3.
PCT/JP1989/000592 1988-06-14 1989-06-13 Recepteur de television WO1989012940A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900700290A KR930000952B1 (ko) 1988-06-14 1989-06-13 텔레비젼 수신기

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP14643188 1988-06-14
JP63/146431 1988-06-14

Publications (1)

Publication Number Publication Date
WO1989012940A1 true WO1989012940A1 (fr) 1989-12-28

Family

ID=15407516

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1989/000592 WO1989012940A1 (fr) 1988-06-14 1989-06-13 Recepteur de television

Country Status (2)

Country Link
KR (1) KR930000952B1 (fr)
WO (1) WO1989012940A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132793A (en) * 1989-03-10 1992-07-21 Hitachi, Ltd. Television receiver compatible with both standard system television signal and high definition television signal

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5351922A (en) * 1976-10-21 1978-05-11 Sony Corp Television receiver
JPS5854783A (ja) * 1981-09-28 1983-03-31 Matsushita Electric Ind Co Ltd テレビジヨン受像機
JPS59122286A (ja) * 1982-12-28 1984-07-14 Toshiba Corp テレビシステム変換方法
JPS61206380A (ja) * 1985-03-11 1986-09-12 Victor Co Of Japan Ltd 画像デイスプレイ装置
JPS61267469A (ja) * 1985-05-21 1986-11-27 Canon Inc 出力装置
JPS6326174A (ja) * 1986-07-18 1988-02-03 Matsushita Electric Ind Co Ltd 高品位テレビジヨン受信装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5351922A (en) * 1976-10-21 1978-05-11 Sony Corp Television receiver
JPS5854783A (ja) * 1981-09-28 1983-03-31 Matsushita Electric Ind Co Ltd テレビジヨン受像機
JPS59122286A (ja) * 1982-12-28 1984-07-14 Toshiba Corp テレビシステム変換方法
JPS61206380A (ja) * 1985-03-11 1986-09-12 Victor Co Of Japan Ltd 画像デイスプレイ装置
JPS61267469A (ja) * 1985-05-21 1986-11-27 Canon Inc 出力装置
JPS6326174A (ja) * 1986-07-18 1988-02-03 Matsushita Electric Ind Co Ltd 高品位テレビジヨン受信装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132793A (en) * 1989-03-10 1992-07-21 Hitachi, Ltd. Television receiver compatible with both standard system television signal and high definition television signal

Also Published As

Publication number Publication date
KR900702717A (ko) 1990-12-08
KR930000952B1 (ko) 1993-02-11

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