WO1988002182A1 - Method of manufacturing integrated circuits - Google Patents

Method of manufacturing integrated circuits Download PDF

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Publication number
WO1988002182A1
WO1988002182A1 PCT/GB1986/000548 GB8600548W WO8802182A1 WO 1988002182 A1 WO1988002182 A1 WO 1988002182A1 GB 8600548 W GB8600548 W GB 8600548W WO 8802182 A1 WO8802182 A1 WO 8802182A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
integrated circuits
test structures
structures
connections
Prior art date
Application number
PCT/GB1986/000548
Other languages
French (fr)
Inventor
Michael Geoffrey Pitt
Original Assignee
The General Electric Company, P.L.C.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to GB08515659A priority Critical patent/GB2176653B/en
Application filed by The General Electric Company, P.L.C. filed Critical The General Electric Company, P.L.C.
Priority to PCT/GB1986/000548 priority patent/WO1988002182A1/en
Priority to EP19860905369 priority patent/EP0281553A1/en
Priority to JP50486386A priority patent/JPH01500784A/en
Publication of WO1988002182A1 publication Critical patent/WO1988002182A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • G01R31/2858—Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection

Definitions

  • This invention relates to methods of manufactur ⁇ ing integrated circuits.
  • Electromigration of conductive tracks has been identified as a major reliability hazard in integrated circuits particularly in VLSIs.
  • the resistance to electromigration of the circuit depends on a number of factors such as conductive track composition, morphology etc. it is not always possible to control this during the manufacture of an integrated circuit, and it is therefore necessary to assess electromigration resistance routinely on a batch-to-batch basis during the manufacture of the circuit.
  • To do this it is known to incorporate a number of conductive test structures on the wafer on which a number of integrated circuits are formed during the manufacture of the circuits. As each structure must be individually bonded up in order to be tested to determine whether electromigration has caused failure of the structure, however, this proceedure is necessarily slow and thus expensive.
  • a method of manufacturing integrated circuits includes the steps of: forming a plurality of conductive test structures for monitoring electromigration each at a different point on the wafer on which the integrated circuits are formed; forming electrical connections between the structures on the wafer; and monitoring an electrical parameter of the current path constituted by the structures and the connections and using the value of the electrical para- meter to determine whether any of the test structures have failed.
  • each test structure is not required, and thus bonding to each structure is not necessary.
  • the electrical connections are such that a current path is maintained in the event of one of the test structures becoming open circuit.
  • the electrical parameter is suitably resistance.
  • connections preferably include resistances.
  • the conductive test structures and connections are formed within wafer scribe channels.
  • Figure 1 is a schematic diagram of part of a wafer includixig, the integrated circuit at a stage during the manufacture of the circuit;
  • Figure 2 is an equivalent circuit of an electro ⁇ migration test structure incorporated on the wafer of Figure 1.
  • the method includes forming a number of conventional integrated circuits, indicated as 1, upon a wafer, the circuits being separated from each other by scribe channels 3 formed within the wafer in the usual manner.
  • a conductive track 5 running across the wafer this being deposited on the wafer at the same time as the conductive tracks within the circuits 1.
  • Electromigration test stripes 7 are defined at intervals along the length of the track 5, usually one such stripe being provided in respect of each integrated circuit 1.
  • Each stripe 7 is arranged to pass over a number of steps 9 formed on the wafer so as to simulate the conditions under which a con ⁇ ductive track is prone to become open circuit.
  • a respective polysilicon resistor 11 is deposited next to each stripe 7, the conductive track 5 being arranged to connect each resistor 11 in parallel with its adjacent stripe 7.
  • each scribe channel 3 is as shown in Figure 2 where R M1 to R MN represent the stripes 7 associated with each inte ⁇ grated circuit 1, in a row across the wafer, and R p , to R represent the resistors 11 provided in respect of each stripe 7-
  • the value of resistance of each of the resistors R p _ to R pM is designed to be much greater than the resistance of each stripe R. M,l_ to R.M,.N ⁇ .
  • each track 5 At suitable times during the manufacturing of the wafer, electrical connections are made at each end of each track 5 such that current of a suitable value to electrically stress the stripes 7 may flow through the track 5, and the resistance across the track 5 is monitored. In the event that one of the stripes 7 has failed by becoming open circuit, an increased value of resistance will be monitored. As the parallel arrangement of resistors 11 and stripes 7 enables current to flow through the remaining stripes 7, any further failures may also be monitored, the total number of failures being indicated by the increase in resistance monitored across the track.
  • test stripe 7 will normally run over a variety of topological features on the wafer so as to give a worst case situation. It will also be appreciated that many other test structures may be designed, for example for monitoring closed circuits due to electromigration.
  • test structures and connections within the scribe channels of the wafer may be formed on other portions of the wafer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A method of manufacturing integrated circuits in which a number of conductive test structures (7) for monitoring electromigration are formed at different points on the wafer on which the integrated circuits (1) are being manufactured. Electrical connections (5) are formed between the test structures (7) on the wafer, and the resistance of the current path constituted by the structures (7) and connections (5) is monitored to determine whether any of the test structures (7) have failed.

Description

Method of manufacturing integrated circuits
This invention relates to methods of manufactur¬ ing integrated circuits.
Electromigration of conductive tracks has been identified as a major reliability hazard in integrated circuits particularly in VLSIs. As the resistance to electromigration of the circuit depends on a number of factors such as conductive track composition, morphology etc. it is not always possible to control this during the manufacture of an integrated circuit, and it is therefore necessary to assess electromigration resistance routinely on a batch-to-batch basis during the manufacture of the circuit. To do this it is known to incorporate a number of conductive test structures on the wafer on which a number of integrated circuits are formed during the manufacture of the circuits. As each structure must be individually bonded up in order to be tested to determine whether electromigration has caused failure of the structure, however, this proceedure is necessarily slow and thus expensive. It is an object of the present invention to provide a method of manufacturing integrated circuits wherein this problem is alleviated. According to the present invention a method of manufacturing integrated circuits includes the steps of: forming a plurality of conductive test structures for monitoring electromigration each at a different point on the wafer on which the integrated circuits are formed; forming electrical connections between the structures on the wafer; and monitoring an electrical parameter of the current path constituted by the structures and the connections and using the value of the electrical para- meter to determine whether any of the test structures have failed.
Thus in a method in accordance with the invention individual testing of each test structure is not required, and thus bonding to each structure is not necessary. Preferably the electrical connections are such that a current path is maintained in the event of one of the test structures becoming open circuit.
It is thus possible to continue to monitor for the failure of any further test structures. The electrical parameter is suitably resistance.
The connections preferably include resistances. Preferably the conductive test structures and connections are formed within wafer scribe channels.
One method of manufacturing an integrated circuit in accordance with the invention will now be described, by way of example only, with reference to the accompanying drawings in which:
Figure 1 is a schematic diagram of part of a wafer includixig, the integrated circuit at a stage during the manufacture of the circuit; and
Figure 2 is an equivalent circuit of an electro¬ migration test structure incorporated on the wafer of Figure 1.
Referring to Figure 1, the method includes forming a number of conventional integrated circuits, indicated as 1, upon a wafer, the circuits being separated from each other by scribe channels 3 formed within the wafer in the usual manner. In respect of each row of circuits 1 across the wafer, there is provided in an adjacent scribe channel a conductive track 5 running across the wafer this being deposited on the wafer at the same time as the conductive tracks within the circuits 1. Electromigration test stripes 7 are defined at intervals along the length of the track 5, usually one such stripe being provided in respect of each integrated circuit 1. Each stripe 7 is arranged to pass over a number of steps 9 formed on the wafer so as to simulate the conditions under which a con¬ ductive track is prone to become open circuit. A respective polysilicon resistor 11 is deposited next to each stripe 7, the conductive track 5 being arranged to connect each resistor 11 in parallel with its adjacent stripe 7.
Thus the equivalent circuit for the structure within each scribe channel 3 is as shown in Figure 2 where RM1 to RMN represent the stripes 7 associated with each inte¬ grated circuit 1, in a row across the wafer, and Rp, to R represent the resistors 11 provided in respect of each stripe 7- The value of resistance of each of the resistors Rp_ to RpM is designed to be much greater than the resistance of each stripe R. M,l_ to R.M,.Nτ.
At suitable times during the manufacturing of the wafer, electrical connections are made at each end of each track 5 such that current of a suitable value to electrically stress the stripes 7 may flow through the track 5, and the resistance across the track 5 is monitored. In the event that one of the stripes 7 has failed by becoming open circuit, an increased value of resistance will be monitored. As the parallel arrangement of resistors 11 and stripes 7 enables current to flow through the remaining stripes 7, any further failures may also be monitored, the total number of failures being indicated by the increase in resistance monitored across the track.
It will be appreciated that each test stripe 7 will normally run over a variety of topological features on the wafer so as to give a worst case situation. It will also be appreciated that many other test structures may be designed, for example for monitoring closed circuits due to electromigration.
It will also be appreciated that whilst it is particularly convenient to form the test structures and connections within the scribe channels of the wafer, as they do not then take up space on the wafer, they may be formed on other portions of the wafer.

Claims

1. A method of manufacturing integrated circuits in which a plurality of conductive test structures (7) for monitoring electromigration are formed each at a different point on the wafer on which the integrated circuits (1) are formed, the method being characterised in that it includes the steps of: forming electrical connections (5) between the structures (7) on the wafer; and monitoring an electrical parameter of the current path constituted by the structures ( 7) and the connect- ions (5,11) and using the value of the electrical para¬ meter to determine whether any of the test structures (7) have failed.
2. A method according to Claim 1 in which the electrical connections (5,11) are such that a current path is maintained in the event of one of the test structures (7) becoming open circuit.
3. A method according to either of the preceding claims in which the electrical parameter is resistance.
4. A method according to any one of the preceding claims in which the connections include resistance (11).
5. A method according to any one of the preceding claims in which the conductive test structures (7) and connections (5,11) are formed within wafer scribe channels (3) .
PCT/GB1986/000548 1985-06-20 1986-09-17 Method of manufacturing integrated circuits WO1988002182A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB08515659A GB2176653B (en) 1985-06-20 1985-06-20 Method of manufacturing integrated circuits
PCT/GB1986/000548 WO1988002182A1 (en) 1986-09-17 1986-09-17 Method of manufacturing integrated circuits
EP19860905369 EP0281553A1 (en) 1986-09-17 1986-09-17 Method of manufacturing integrated circuits
JP50486386A JPH01500784A (en) 1986-09-17 1986-09-17 Integrated circuit manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/GB1986/000548 WO1988002182A1 (en) 1986-09-17 1986-09-17 Method of manufacturing integrated circuits

Publications (1)

Publication Number Publication Date
WO1988002182A1 true WO1988002182A1 (en) 1988-03-24

Family

ID=10591174

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1986/000548 WO1988002182A1 (en) 1985-06-20 1986-09-17 Method of manufacturing integrated circuits

Country Status (3)

Country Link
EP (1) EP0281553A1 (en)
JP (1) JPH01500784A (en)
WO (1) WO1988002182A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0448273A1 (en) * 1990-03-21 1991-09-25 AT&T Corp. Integrated circuit electromigration monitor
EP0547693A2 (en) * 1991-12-18 1993-06-23 Koninklijke Philips Electronics N.V. Circuit arrangement comprising an end-of-life detector
US5264377A (en) * 1990-03-21 1993-11-23 At&T Bell Laboratories Integrated circuit electromigration monitor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3611338B2 (en) * 1993-06-21 2005-01-19 財団法人国際科学振興財団 Current-driven conductive material evaluation method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2262409A1 (en) * 1974-02-22 1975-09-19 Bosch Gmbh Robert
EP0073721A2 (en) * 1981-08-28 1983-03-09 Fujitsu Limited Large scala integration semiconductor device having monitor element and method of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2262409A1 (en) * 1974-02-22 1975-09-19 Bosch Gmbh Robert
EP0073721A2 (en) * 1981-08-28 1983-03-09 Fujitsu Limited Large scala integration semiconductor device having monitor element and method of manufacturing the same

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Vol. 14, No. 9, February 1972 (New York, USA), A. MANDIA et al., "Formation of kerf Metallurgy on Integrated Semiconductor Circuit Wafers", see pages 2620-2621 *
IBM Technical Disclosure Bulletin, Vol. 26, No. 4, September 1983 (New York, USA), C.M. HSIEH et al., "Metal Electromigration Sensor", see pages 1998-1999 *
IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 1, February 1984 (IEEE, New York, USA) K.P. RODBELL et al., "A new Method for Detecting Electro-Migration Failure in VLSI Metallization", pages 98-99, see paragraph: "Experimental Details" *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0448273A1 (en) * 1990-03-21 1991-09-25 AT&T Corp. Integrated circuit electromigration monitor
US5264377A (en) * 1990-03-21 1993-11-23 At&T Bell Laboratories Integrated circuit electromigration monitor
EP0547693A2 (en) * 1991-12-18 1993-06-23 Koninklijke Philips Electronics N.V. Circuit arrangement comprising an end-of-life detector
EP0547693A3 (en) * 1991-12-18 1993-11-18 Philips Nv Circuit arrangement comprising an end-of-life detector
US5598101A (en) * 1991-12-18 1997-01-28 U.S. Philips Corporation Circuit arrangement having a wear indicator to indicate end of service life

Also Published As

Publication number Publication date
JPH01500784A (en) 1989-03-16
EP0281553A1 (en) 1988-09-14

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