JPH01500784A - Integrated circuit manufacturing method - Google Patents
Integrated circuit manufacturing methodInfo
- Publication number
- JPH01500784A JPH01500784A JP50486386A JP50486386A JPH01500784A JP H01500784 A JPH01500784 A JP H01500784A JP 50486386 A JP50486386 A JP 50486386A JP 50486386 A JP50486386 A JP 50486386A JP H01500784 A JPH01500784 A JP H01500784A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- integrated circuit
- test structures
- test
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
- G01R31/2858—Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。 (57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 集積回路の製造方法 本発明は集積回路の製造方法に関する。[Detailed description of the invention] Integrated circuit manufacturing method The present invention relates to a method for manufacturing integrated circuits.
導電性トラックの電気移動（ｅｌｅｅｔｒｏｍｉｇｒａｔｉｏｎ）は、特にＶＬ ＳＩにおける集積回路の大きな信頼性問題として確認されている。回路の電気移 動に対する抵抗は導電性トラックの組成や形態などの多くのファクターに依存す るため、集積回路の製造時これを制御することは必ずしも可能でなく、従って回 路の製造時に製造毎に定期的に電気移動抵抗を評価することが必要である。この 目的から、回路の製造時に、多数の集積回路を形成したウェハに多数の導電性試 験構造体を組み込むことが知られている。ところが、電気移動により構造体が破 損したかどうか調べる試験を行うためには、各構造体を個々に結合しなければな らないため、必然的に時間がかかり、従ってコストが高くなる。Electromigration of conductive tracks is particularly important for VL It has been identified as a major reliability problem for integrated circuits in SI. electrical transfer of circuits The resistance to motion depends on many factors such as the composition and morphology of the conductive tracks. It is not always possible to control this during the manufacture of integrated circuits due to It is necessary to evaluate the electromigration resistance at regular intervals during the manufacture of the road. this For this purpose, during circuit manufacturing, a large number of conductive tests are applied to a wafer on which a large number of integrated circuits are formed. It is known to incorporate experimental structures. However, the structure was destroyed due to electromigration. To test for damage, each structure must be joined individually. This inevitably results in time-consuming and therefore high costs.
本発明の目的は、この問題のない集積回路の製造方法を提供することにある。It is an object of the present invention to provide a method for manufacturing integrated circuits that does not have this problem.
本発明によれば、集積回路の製造方法は、多数の集積回路を形成した１クエ八り の各界なる点で電気移動をギニ々−する複数の導電性試験構造体を形成（５、そ ）、て該構造体と接続部とＩ、−よって構成された電流路の電気バ、ンメ−タを モニターし、この電気パラメータの値を使用して、試験構造体のどれが破損した かどうかを調べる工程を含むものである。According to the present invention, a method for manufacturing an integrated circuit includes one Formation of multiple electrically conductive test structures that significantly increase electromigration at various points in the field (5, ), the structure, the connection part, and the electric bar of the current path constituted by I. Monitor and use the value of this electrical parameter to determine which of the test structures are damaged. This includes the process of checking whether the
従って、本発明による方法では、各試験構造体を個々に試験する必要がなく、従 って各構造体に結合する必要もない。The method according to the invention therefore eliminates the need to test each test structure individually; There is no need to connect it to each structure.
好ましくは、試験構造体のひとつが開回路になった場合に、電流路が維持される ように電気接続を設定する。Preferably, a current path is maintained if one of the test structures becomes an open circuit. Set up the electrical connections as shown.
従って、試験構造体の破損を連続的にモニターすること可能である。It is therefore possible to continuously monitor failure of the test structure.
電気パラメータは適当には抵抗である。The electrical parameter is suitably resistance.
接続部は好適には抵抗を含む。The connection preferably includes a resistor.
好ましくは、導電性試験構造体及び接続部はウェハのスクライブ・チャネル内に 形成する。Preferably, the conductive test structures and connections are within the scribe channel of the wafer. Form.
以下、本発明による集積回路の製造方法を例示のみを目的とする添付図面につい て説明する。Hereinafter, reference will be made to the accompanying drawings, which are for illustrative purposes only, the method of manufacturing an integrated circuit according to the present invention. I will explain.
第１図は、集積回路製造段階における該回路を含むウェハ要部を示す概略図であ り、そして 第２図は、第１図ウェハに組み込んだ電気移動試験構造体の等価回路を示す図で ある。FIG. 1 is a schematic diagram showing the main part of a wafer including the integrated circuit at the stage of manufacturing the integrated circuit. ri, and Figure 2 is a diagram showing the equivalent circuit of the electromigration test structure incorporated into the wafer in Figure 1. be.
第１図について説明すると、本発明方法はウェハ上に多数の従来集積回路ｌを形 成することからなり、各集積回路は常法でウェハ内に形成したスクライブ・チャ ネル３によって分離する。ウェハを横断する回路ｌの各列に特表平１−５００７ ８４ （２） ついて、隣接スクライブ・チャネルにウェハを横断する導電性トラック５を設け る。これは、回路ｌ内の導電性トラックと同時Ｉこウェハに付着させる。電気移 動試験片７はトラック５の全長に沿って間隔をおいて設けるが、通常は、各集積 回路ｌに対してひとつの試験片を設ける。各試験片７はウェハに形成した多数の ステップ９上を通過するように配列して、導電性トラックが容易に開回路になる 条件をシュミレートする。各試験片７に隣接してポリシリコン抵抗器１１を付着 し、各抵抗器１１はその隣接試験片７に並列接続するように導電性トラック５を 設ける。Referring to FIG. 1, the method of the present invention forms a large number of conventional integrated circuits l on a wafer. Each integrated circuit consists of scribe channels formed within the wafer using conventional methods. Separate by channel 3. Special table 1-5007 for each row of circuits that cross the wafer 84 (2) Then, adjacent scribe channels are provided with conductive tracks 5 across the wafer. Ru. This is deposited on the wafer at the same time as the conductive tracks in the circuit. electrotransfer Dynamic specimens 7 are spaced along the length of track 5, but typically at each stack. One test piece is provided for circuit l. Each test piece 7 has a large number of Arrange to pass over step 9 so that the conductive track easily becomes an open circuit Simulate conditions. A polysilicon resistor 11 is attached adjacent to each test piece 7. Each resistor 11 has a conductive track 5 connected in parallel to its adjacent test piece 7. establish.
従って、各スクライブ・チャネル３内に構造体の等価回路が、第２図に示すよう に形成される。第２図において、Ｒ−Ｍｌ−Ｒ−ＭＮはウェハを一列となって横 断する、各集積回路ｌに関連する試験片７を示し、Ｒ−ＰＩ〜Ｒ−ＰＮは各試験 片７に設けた抵抗器１１を示す。各抵抗器Ｒ−ＰＩ−Ｒ−ＰＮの抵抗値は各試験 片Ｒ−Ｍｌ〜Ｒ−ＭＮの抵抗よりかなり大きくしである。Therefore, the equivalent circuit of the structure within each scribe channel 3 is as shown in FIG. is formed. In FIG. The test piece 7 associated with each integrated circuit l is shown, and R-PI to R-PN represent each test piece. A resistor 11 provided on piece 7 is shown. The resistance value of each resistor R-PI-R-PN is It is considerably larger than the resistance of the pieces R-Ml to R-MN.
ウェハ製造時の適当な時期に、各トラック５の各端部を電気的に接続して、試験 片７に電気応力を加える適当な値の電流をトラック５に流し、トラック５の両端 間の抵抗をモニターする。開回路になることによって試験片７の一つが破損する と、モニターしている抵抗値が大きくなる。抵抗器１１と試験片７とを平行に配 列しているため、電流が残りの試験片７に流れるので、さらに生じる破損もモニ ターできる。この場合、破損の総数はトラック両端間でモニターされた抵抗の増 大によって示される。At an appropriate time during wafer manufacturing, each end of each track 5 is electrically connected and tested. A suitable value of current is applied to the track 5 to apply electrical stress to the strip 7, and both ends of the track 5 are Monitor the resistance between. One of the specimens 7 is damaged due to an open circuit. , the resistance value being monitored increases. The resistor 11 and the test piece 7 are arranged in parallel. Since the current flows through the remaining specimen 7, further damage can be monitored. You can. In this case, the total number of breaks is determined by the increase in resistance monitored across the track. Indicated by large.
なお、各試験片７は、最悪のケースを作り出せるように、位相空間特徴が可変に なっている。In addition, each test piece 7 has variable phase space characteristics to create the worst case. It has become.
また、例えば電気移動による閉回路をモニターする目的から、他の多くの試験片 を設計することも可能である。In addition, many other test specimens are used, for example for the purpose of monitoring closed circuits due to electromigration. It is also possible to design
さらにまた、ウェハのスクライブ・チャネル内に試験片及び接続部を形成するこ とが特に有利である。というのは、この場合、ウェハ上のスペースを取らず、従 ってウェハの他の部分にこれらを形成できるからである。Furthermore, forming test strips and connections within the scribe channel of the wafer is also possible. is particularly advantageous. In this case, it takes up less space on the wafer and This is because they can be formed on other parts of the wafer.
国際調査報告 ＡＮＮＥＸτＯｈ郡：ＮＴＥＲＮＡＴＩＯＩ’Ａ’−ＥＥＡＲＣＨＲＥＰＯＲＴ ＯＮinternational search report ANNEXτOh county: NTERNATIOI’A’-EEARCHREPORT ON
Claims (5)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/GB1986/000548 WO1988002182A1 (en) | 1986-09-17 | 1986-09-17 | Method of manufacturing integrated circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01500784A true JPH01500784A (en) | 1989-03-16 |
Family
ID=10591174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50486386A Pending JPH01500784A (en) | 1986-09-17 | 1986-09-17 | Integrated circuit manufacturing method |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0281553A1 (en) |
| JP (1) | JPH01500784A (en) |
| WO (1) | WO1988002182A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995000971A1 (en) * | 1993-06-21 | 1995-01-05 | Tadahiro Ohmi | Method of evaluating current-driven conductive material |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5264377A (en) * | 1990-03-21 | 1993-11-23 | At&T Bell Laboratories | Integrated circuit electromigration monitor |
| EP0448273B1 (en) * | 1990-03-21 | 1994-09-28 | AT&T Corp. | Integrated circuit electromigration monitor |
| TW216472B (en) * | 1991-12-18 | 1993-11-21 | Philips Nv |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2408540C2 (en) * | 1974-02-22 | 1982-04-08 | Robert Bosch Gmbh, 7000 Stuttgart | Semiconductor component from a large number of at least approximately identical circuit elements and a method for identifying and separating defective circuit elements |
| JPS602775B2 (en) * | 1981-08-28 | 1985-01-23 | 富士通株式会社 | Large-scale integrated circuit with monitor function and its manufacturing method |
-
1986
- 1986-09-17 EP EP19860905369 patent/EP0281553A1/en not_active Withdrawn
- 1986-09-17 JP JP50486386A patent/JPH01500784A/en active Pending
- 1986-09-17 WO PCT/GB1986/000548 patent/WO1988002182A1/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995000971A1 (en) * | 1993-06-21 | 1995-01-05 | Tadahiro Ohmi | Method of evaluating current-driven conductive material |
| US5554938A (en) * | 1993-06-21 | 1996-09-10 | Ohmi; Tadahiro | Method of evaluating current-driven conductive material |
Also Published As
| Publication number | Publication date |
|---|---|
| WO1988002182A1 (en) | 1988-03-24 |
| EP0281553A1 (en) | 1988-09-14 |
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