EP0281553A1 - Method of manufacturing integrated circuits - Google Patents
Method of manufacturing integrated circuitsInfo
- Publication number
- EP0281553A1 EP0281553A1 EP19860905369 EP86905369A EP0281553A1 EP 0281553 A1 EP0281553 A1 EP 0281553A1 EP 19860905369 EP19860905369 EP 19860905369 EP 86905369 A EP86905369 A EP 86905369A EP 0281553 A1 EP0281553 A1 EP 0281553A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- wafer
- integrated circuits
- test structures
- structures
- connections
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
- G01R31/2858—Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
Definitions
- This invention relates to methods of manufactur ⁇ ing integrated circuits.
- Electromigration of conductive tracks has been identified as a major reliability hazard in integrated circuits particularly in VLSIs.
- the resistance to electromigration of the circuit depends on a number of factors such as conductive track composition, morphology etc. it is not always possible to control this during the manufacture of an integrated circuit, and it is therefore necessary to assess electromigration resistance routinely on a batch-to-batch basis during the manufacture of the circuit.
- To do this it is known to incorporate a number of conductive test structures on the wafer on which a number of integrated circuits are formed during the manufacture of the circuits. As each structure must be individually bonded up in order to be tested to determine whether electromigration has caused failure of the structure, however, this proceedure is necessarily slow and thus expensive.
- a method of manufacturing integrated circuits includes the steps of: forming a plurality of conductive test structures for monitoring electromigration each at a different point on the wafer on which the integrated circuits are formed; forming electrical connections between the structures on the wafer; and monitoring an electrical parameter of the current path constituted by the structures and the connections and using the value of the electrical para- meter to determine whether any of the test structures have failed.
- each test structure is not required, and thus bonding to each structure is not necessary.
- the electrical connections are such that a current path is maintained in the event of one of the test structures becoming open circuit.
- the electrical parameter is suitably resistance.
- connections preferably include resistances.
- the conductive test structures and connections are formed within wafer scribe channels.
- Figure 1 is a schematic diagram of part of a wafer includixig, the integrated circuit at a stage during the manufacture of the circuit;
- Figure 2 is an equivalent circuit of an electro ⁇ migration test structure incorporated on the wafer of Figure 1.
- the method includes forming a number of conventional integrated circuits, indicated as 1, upon a wafer, the circuits being separated from each other by scribe channels 3 formed within the wafer in the usual manner.
- a conductive track 5 running across the wafer this being deposited on the wafer at the same time as the conductive tracks within the circuits 1.
- Electromigration test stripes 7 are defined at intervals along the length of the track 5, usually one such stripe being provided in respect of each integrated circuit 1.
- Each stripe 7 is arranged to pass over a number of steps 9 formed on the wafer so as to simulate the conditions under which a con ⁇ ductive track is prone to become open circuit.
- a respective polysilicon resistor 11 is deposited next to each stripe 7, the conductive track 5 being arranged to connect each resistor 11 in parallel with its adjacent stripe 7.
- each scribe channel 3 is as shown in Figure 2 where R M1 to R MN represent the stripes 7 associated with each inte ⁇ grated circuit 1, in a row across the wafer, and R p , to R represent the resistors 11 provided in respect of each stripe 7-
- the value of resistance of each of the resistors R p _ to R pM is designed to be much greater than the resistance of each stripe R. M,l_ to R.M,.N ⁇ .
- each track 5 At suitable times during the manufacturing of the wafer, electrical connections are made at each end of each track 5 such that current of a suitable value to electrically stress the stripes 7 may flow through the track 5, and the resistance across the track 5 is monitored. In the event that one of the stripes 7 has failed by becoming open circuit, an increased value of resistance will be monitored. As the parallel arrangement of resistors 11 and stripes 7 enables current to flow through the remaining stripes 7, any further failures may also be monitored, the total number of failures being indicated by the increase in resistance monitored across the track.
- test stripe 7 will normally run over a variety of topological features on the wafer so as to give a worst case situation. It will also be appreciated that many other test structures may be designed, for example for monitoring closed circuits due to electromigration.
- test structures and connections within the scribe channels of the wafer may be formed on other portions of the wafer.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Automation & Control Theory (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Dans un procédé de fabrication de circuits intégrés, on contrôle l'électro-migration en formant un certain nombre de structures de test conductrices (7) en différents points sur la tranche sur laquelle sont fabriqués les circuits intégrés (1). On établit des connexions électriques (5) entre les structures de test (7) disposées sur la tranche et on contrôle la résistance du trajet du courant constitué par les structures (7) et par les connexions (5) afin de déterminer si une panne de l'une ou l'autre des structures de test (7) est intervenue.In an integrated circuit manufacturing process, electro-migration is controlled by forming a number of conductive test structures (7) at different points on the wafer on which the integrated circuits (1) are manufactured. Electrical connections (5) are made between the test structures (7) arranged on the wafer and the resistance of the current path formed by the structures (7) and by the connections (5) is checked in order to determine whether a failure of one or other of the test structures (7) intervened.
Description
Claims
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/GB1986/000548 WO1988002182A1 (en) | 1986-09-17 | 1986-09-17 | Method of manufacturing integrated circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0281553A1 true EP0281553A1 (en) | 1988-09-14 |
Family
ID=10591174
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19860905369 Withdrawn EP0281553A1 (en) | 1986-09-17 | 1986-09-17 | Method of manufacturing integrated circuits |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0281553A1 (en) |
JP (1) | JPH01500784A (en) |
WO (1) | WO1988002182A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5264377A (en) * | 1990-03-21 | 1993-11-23 | At&T Bell Laboratories | Integrated circuit electromigration monitor |
SG30537G (en) * | 1990-03-21 | 1995-09-01 | At & T Corp | Integrated circuit electromigration monitor |
TW216472B (en) * | 1991-12-18 | 1993-11-21 | Philips Nv | |
JP3611338B2 (en) * | 1993-06-21 | 2005-01-19 | 財団法人国際科学振興財団 | Current-driven conductive material evaluation method |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2408540C2 (en) * | 1974-02-22 | 1982-04-08 | Robert Bosch Gmbh, 7000 Stuttgart | Semiconductor component from a large number of at least approximately identical circuit elements and a method for identifying and separating defective circuit elements |
JPS602775B2 (en) * | 1981-08-28 | 1985-01-23 | 富士通株式会社 | Large-scale integrated circuit with monitor function and its manufacturing method |
-
1986
- 1986-09-17 JP JP50486386A patent/JPH01500784A/en active Pending
- 1986-09-17 WO PCT/GB1986/000548 patent/WO1988002182A1/en not_active Application Discontinuation
- 1986-09-17 EP EP19860905369 patent/EP0281553A1/en not_active Withdrawn
Non-Patent Citations (1)
Title |
---|
See references of WO8802182A1 * |
Also Published As
Publication number | Publication date |
---|---|
JPH01500784A (en) | 1989-03-16 |
WO1988002182A1 (en) | 1988-03-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19880531 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR IT NL |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
17Q | First examination report despatched |
Effective date: 19880909 |
|
18D | Application deemed to be withdrawn |
Effective date: 19890120 |