WO1988001118A3 - Improvements relating to data transmission systems - Google Patents

Improvements relating to data transmission systems Download PDF

Info

Publication number
WO1988001118A3
WO1988001118A3 PCT/GB1987/000531 GB8700531W WO8801118A3 WO 1988001118 A3 WO1988001118 A3 WO 1988001118A3 GB 8700531 W GB8700531 W GB 8700531W WO 8801118 A3 WO8801118 A3 WO 8801118A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
synchronisation
signals
data transmission
transmission systems
Prior art date
Application number
PCT/GB1987/000531
Other languages
French (fr)
Other versions
WO1988001118A2 (en
Inventor
Anthony Peter Hulbert
Original Assignee
Plessey Overseas
Anthony Peter Hulbert
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Overseas, Anthony Peter Hulbert filed Critical Plessey Overseas
Publication of WO1988001118A2 publication Critical patent/WO1988001118A2/en
Publication of WO1988001118A3 publication Critical patent/WO1988001118A3/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Abstract

A data transmission system receiver comprising a data synchronisation unit and first-in first-out data store connected in parallel to receive incoming data signals, in which the data store delays the incoming data signals by a time period which corresponds to the time required for the synchronisation unit to achieve synchronisation of a clock with the incoming data signals and in which data gate or sampler means responsive to signals from the synchronisation unit indicating that synchronisation has been achieved enables data signals to be passed from the store to a data line.
PCT/GB1987/000531 1986-07-25 1987-07-27 Improvements relating to data transmission systems WO1988001118A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8618206A GB2193863B (en) 1986-07-25 1986-07-25 Improvements relating to data transmission systems
GB8618206 1986-07-25

Publications (2)

Publication Number Publication Date
WO1988001118A2 WO1988001118A2 (en) 1988-02-11
WO1988001118A3 true WO1988001118A3 (en) 1988-05-19

Family

ID=10601693

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1987/000531 WO1988001118A2 (en) 1986-07-25 1987-07-27 Improvements relating to data transmission systems

Country Status (5)

Country Link
EP (1) EP0276272A1 (en)
JP (1) JPH01500950A (en)
AU (1) AU592011B2 (en)
GB (1) GB2193863B (en)
WO (1) WO1988001118A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE9300679L (en) * 1993-03-01 1994-09-02 Ellemtel Utvecklings Ab bit synchronizer
JP3195274B2 (en) 1997-06-16 2001-08-06 埼玉日本電気株式会社 TDMA audio information reading device
JP4276647B2 (en) 2005-08-25 2009-06-10 富士通マイクロエレクトロニクス株式会社 Semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2293112A1 (en) * 1974-11-27 1976-06-25 Philips Nv RECEIVER USED IN A BINARY PULSE SIGNAL TRANSMISSION SYSTEM AND INCLUDING A CIRCUIT FOR AUTOMATIC CORRECTION OF INTERRUPTIONS IN THE LEVEL OF THE CONTINUOUS VOLTAGE
EP0006384A1 (en) * 1978-06-20 1980-01-09 Thomson-Csf Synchronisation device using a received digital signal and transmission system including such a device
EP0007209A1 (en) * 1978-07-07 1980-01-23 The Post Office Demodulator Arrangement for Diphase Digitally Modulated Signals
EP0056208A1 (en) * 1981-01-09 1982-07-21 Thomson-Csf Process and device for synchronizing messages
US4531223A (en) * 1979-03-20 1985-07-23 Hitachi, Ltd. Clock derivation circuits

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1355495A (en) * 1970-08-18 1974-06-05 Cossor Ltd A C Apparatus for clocking digital data
JPS5823796B2 (en) * 1978-10-19 1983-05-17 工業技術院長 Imaging device
JPS5584007A (en) * 1978-12-19 1980-06-24 Matsushita Electric Ind Co Ltd Recoder/reproducer of digital signal
JPS55146618A (en) * 1979-04-27 1980-11-15 Hitachi Ltd Data synchronizing circuit
JPS60170377A (en) * 1984-02-14 1985-09-03 Sony Corp Automatic black level controlling circuit
US4691375A (en) * 1984-06-06 1987-09-01 National Research Development Corporation Data transmission using a transparent tone-in band system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2293112A1 (en) * 1974-11-27 1976-06-25 Philips Nv RECEIVER USED IN A BINARY PULSE SIGNAL TRANSMISSION SYSTEM AND INCLUDING A CIRCUIT FOR AUTOMATIC CORRECTION OF INTERRUPTIONS IN THE LEVEL OF THE CONTINUOUS VOLTAGE
EP0006384A1 (en) * 1978-06-20 1980-01-09 Thomson-Csf Synchronisation device using a received digital signal and transmission system including such a device
EP0007209A1 (en) * 1978-07-07 1980-01-23 The Post Office Demodulator Arrangement for Diphase Digitally Modulated Signals
US4531223A (en) * 1979-03-20 1985-07-23 Hitachi, Ltd. Clock derivation circuits
EP0056208A1 (en) * 1981-01-09 1982-07-21 Thomson-Csf Process and device for synchronizing messages

Also Published As

Publication number Publication date
AU7754387A (en) 1988-02-24
EP0276272A1 (en) 1988-08-03
AU592011B2 (en) 1989-12-21
WO1988001118A2 (en) 1988-02-11
GB2193863B (en) 1990-12-12
JPH01500950A (en) 1989-03-30
GB8618206D0 (en) 1986-12-17
GB2193863A (en) 1988-02-17

Similar Documents

Publication Publication Date Title
WO2000008800A3 (en) Synchronizing source-synchronous links in a switching device
AU552672B2 (en) Signal synchronization system
EP0811928A3 (en) Data synchronization between two devices
DE3854231D1 (en) Bit rate adaptation system for digital transmission systems.
EP0392565A3 (en) System bus control system
WO2000078037A3 (en) System and method for synchronizing, storing and accurately reproducing video signals
WO1988001118A3 (en) Improvements relating to data transmission systems
CA2055823A1 (en) Clock information transmitting device and clock information receiving device
EP0056748A3 (en) Method and device for the synchronization, on reception, of digital signals transmitted as packets
EP0319663A3 (en) Bidirectional control signalling bus interface apparatus for transmitting signals between two bus system
AU4737693A (en) Real time digital data transmission speed conversion system
EP0392397A3 (en) Symbol-wide elasticity buffer
DE3064097D1 (en) Device for synchronizing a clock signal and synchronous data transmission system comprising such a device
AU7907481A (en) Data receiver synchronization
EP0108702A3 (en) Serial to parallel data conversion circuit
GB8826399D0 (en) Device for synchronising clock in relation to incident digital signal particular at high transmission rates
JPS575453A (en) Nonaudio processing system for digital audio
JPS5452433A (en) Data stansmitter
EP0344736A3 (en) High-speed synchronous data transfer system
AU8476982A (en) Digital signal transmission system
JPS5746550A (en) Synchronizing system for data transmission between devices
JPS5588456A (en) Access control system for common circuit
JPS52132703A (en) Time sharing multiplex data transmission system
CA2199647C (en) Synchronization of communication devices connected over an asynchronous link
JPS5389307A (en) Test system for communicating line system

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AU JP US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE FR IT LU NL SE

WWE Wipo information: entry into national phase

Ref document number: 1987904907

Country of ref document: EP

AK Designated states

Kind code of ref document: A3

Designated state(s): AU JP US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE FR IT LU NL SE

WWP Wipo information: published in national office

Ref document number: 1987904907

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1987904907

Country of ref document: EP