EP0276272A1 - Improvements relating to data transmission systems - Google Patents
Improvements relating to data transmission systemsInfo
- Publication number
- EP0276272A1 EP0276272A1 EP19870904907 EP87904907A EP0276272A1 EP 0276272 A1 EP0276272 A1 EP 0276272A1 EP 19870904907 EP19870904907 EP 19870904907 EP 87904907 A EP87904907 A EP 87904907A EP 0276272 A1 EP0276272 A1 EP 0276272A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- data
- synchronisation
- transmission system
- signals
- store
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Definitions
- This invention relates to data transmission systems and relates more especially to such systems in which short data packets (i.e. groups of data bits) are required to be transmitted and received.
- short data packets i.e. groups of data bits
- the data packets may comprise about 160 data bits.
- transmitted data packets may comprise as few as 16 data bits.
- a receiver for a data transmission system in which data packets are transmitted comprises a data synchronisation unit and a first-in first-out data store connected in parallel to receive incoming data signals, in which the data store delays the incoming data signals by a time period which corresponds to the time required for the synchronisation unit to achieve synchronisation of a clock with the incoming data signals and in which data gate or sampler means responsive to signals from the synchronisation unit indicating that clock synchronisation has been achieved enables data signals to be passed from the store to a data line.
- the data store may be of analogue or digital form and may also provide for the reception of medium length data packets provided that the store delay, although shorter than the duration of the data packet, permits clock acquisition and synchronisation to be achieved.
- a receiver R for a data transmission system comprises a data input terminal DI for receiving incoming data packets from a remote transmitter (not shown) of the system.
- the receiver R comprises an analogue store AS which may be of the so-called bucket-brigade type producing a high resolution delay for delaying the appearance at the output end of the store of the data bits of an incoming data packet received, or being received, into the store from the input data terminal DI, until a synchronised clock SC of a synchronisation unit SU has been acquired and synchronised with the incoming data signals.
- an analogue store AS which may be of the so-called bucket-brigade type producing a high resolution delay for delaying the appearance at the output end of the store of the data bits of an incoming data packet received, or being received, into the store from the input data terminal DI, until a synchronised clock SC of a synchronisation unit SU has been acquired and synchronised with the incoming data signals.
- the unit For the purpose of controlling the clock SC to achieve synchronisation with the incoming data signals the unit comprises a pulse shaper PU and a pair of parallelled monostable devices MON1 and MON2 operable respectively to the leading and trailing edges of incoming data bits.
- An output from the parallelled monostable devices is gated to an early/late gating circuit EL together with the output from the clock SC.
- Early or late outputs from the gate EL are fed to another gate CB which is controlled by an up/down counter CO receiving an edge signal from the early/late gate EL. Control of the gate CB provides an output therefrom for advancing or retarding the clock SC to achieve synchronisation with the incoming data signals.
- the clock output is applied to a digital sampler DS which also receives the delayed data store output from the analogue store AS.
- the sampling rate of the sampler DS which is dependent upon the clock output should be higher than the nominal nyquist rate (i.e. one sample/bit) in order to ensure that the replica of the data input signal waveform can be reconstructed at the analogue data store output.
- incoming data packets may be fed to an integrator IN having a time constant (T) equal to the duration of data packets.
- the start of a data packet which may be determined by carrier signal sense may be arranged to "clear" and release the integrator IN.
- the clock will be correctly synchronised with the data timing and the integrator will be charged to the level of the pedestal voltage of the received data waveform.
- the integrator should therefore be switched to the 'hold' state 'T' seconds after its release.
- the clock in conjunction with the sampler SA, effectively samples the data from the analogue store AS which has an integral bit delay corresponding exactly to the number of bits in a dat packet whilst the integrator output can be used as the slicing threshold.
- the invention is eminently suitable for use in both frequency hopping and packet radio systems and enables all the data packets received at the receiver R to be fully recovered without loss of any data bits of the packet due to the delay of the synchronising clock in acquiring to the incoming data timing.
- the use of an integrator as just above desribed permits threshold determination of the incoming data signal to be achieved.
- Priority Country GB Before the expiration of the time limit for amendin claims and to be republished in the event of the recei amendments.
- Agent SORENTI, Gino; The Plessey Company pic, Intellectual Property Department, Vicarage Lane, Ilford, Essex IG1 4AQ (GB).
- a data transmission system receiver comprising a data synchronisation unit and f ⁇ rst-in first-out data store connected in parallel to receive incoming data signals, in which the data store delays the incoming data signals by a time period which corresponds to the time required for the synchronisation unit to achieve synchronisation of a clock with the incoming data signals and in which data gate or sampler means responsive to signals from the synchronisation unit indicating that synchronisation has been achieved enables data signals to be passed from the store to a data line.
Abstract
Un récepteur d'un système de transmission de données comprend une unité de synchronisation de données et une mémoire de données ''premier reçu, premier envoyé'' connectées en parallèle pour recevoir des signaux entrants de données. La mémoire de données retarde les signaux entrants de données d'une durée correspondante au temps nécessaire pour que l'unité de synchronisation effectue la synchronisation d'une horloge avec les signaux entrants de données. Un dispositif échantillonneur ou de porte de données sensible à des signaux fournis par l'unité de synchronisation pour indiquer que la synchronisation est achevée permet à des signaux de données de passer de la mémoire à une ligne de transmission de données.A receiver of a data transmission system includes a data synchronization unit and a "first received, first sent" data memory connected in parallel to receive incoming data signals. The data memory delays the incoming data signals by a duration corresponding to the time required for the synchronization unit to synchronize a clock with the incoming data signals. A sampler or data gate device responsive to signals supplied by the synchronization unit to indicate that synchronization is complete allows data signals to pass from memory to a data transmission line.
Description
IMPROVEMENTS RELATING TO DATA TRANSMISSION SYSTEMS
This invention relates to data transmission systems and relates more especially to such systems in which short data packets (i.e. groups of data bits) are required to be transmitted and received. By way of example, in a so- called frequency hopping data transmission system in which the frequency of the transmitted data is changed to provide 100 hops/per second the data packets may comprise about 160 data bits. However, transmitted data packets may comprise as few as 16 data bits.
One of the difficulties experienced with the reception of short data packets in non-return to zero (NRZ) data modulation transmission systems resides in the acquisition and synchronisation of the usual synchronised clock by the averaging of data transition timing errors sufficiently rapidly to avoid the loss of incoming data bits.
In accordance with the present invention a receiver for a data transmission system in which data packets are transmitted, comprises a data synchronisation unit and a first-in first-out data store connected in parallel to receive incoming data signals, in which the data store delays the incoming data signals by a time period which corresponds to the time required for the synchronisation
unit to achieve synchronisation of a clock with the incoming data signals and in which data gate or sampler means responsive to signals from the synchronisation unit indicating that clock synchronisation has been achieved enables data signals to be passed from the store to a data line.
By storing the incoming data signals in the data store clock synchronisation can be achieved without loss of incoming data bits.
The data store may be of analogue or digital form and may also provide for the reception of medium length data packets provided that the store delay, although shorter than the duration of the data packet, permits clock acquisition and synchronisation to be achieved.
By way of example the present invention will now be described with reference to the accompanying drawing which shows a block schematic diagram of a data transmission system receiver constructed in accordance with the present invention.
Referring to the drawing a receiver R for a data transmission system (e.g. frequency hopping or packet radio system) comprises a data input terminal DI for receiving incoming data packets from a remote transmitter (not shown) of the system.
The receiver R comprises an analogue store AS which may be of the so-called bucket-brigade type producing a
high resolution delay for delaying the appearance at the output end of the store of the data bits of an incoming data packet received, or being received, into the store from the input data terminal DI, until a synchronised clock SC of a synchronisation unit SU has been acquired and synchronised with the incoming data signals.
For the purpose of controlling the clock SC to achieve synchronisation with the incoming data signals the unit comprises a pulse shaper PU and a pair of parallelled monostable devices MON1 and MON2 operable respectively to the leading and trailing edges of incoming data bits. An output from the parallelled monostable devices is gated to an early/late gating circuit EL together with the output from the clock SC. Early or late outputs from the gate EL are fed to another gate CB which is controlled by an up/down counter CO receiving an edge signal from the early/late gate EL. Control of the gate CB provides an output therefrom for advancing or retarding the clock SC to achieve synchronisation with the incoming data signals. The clock output is applied to a digital sampler DS which also receives the delayed data store output from the analogue store AS. The sampling rate of the sampler DS which is dependent upon the clock output should be higher than the nominal nyquist rate (i.e. one sample/bit) in order to ensure that the replica of the data input signal
waveform can be reconstructed at the analogue data store output.
It may here be mentioned that when a short data packet is received at the receiver R the NRZ waveform will initially be imposed on a pedestal voltage of height proportional to the frequency difference between the receiver and transmitter. The pedestal voltage will decay with a time constant determined by the receiver high pass filtering. A short time constant is required to produce rapid elimination of the pedestal voltage but too short a time constant will result in distortion pf the data waveform (i.e. modulation droop) which could cause errors. To achieve the desired elimination of the pedestal voltage without the occurrence of errors, incoming data packets may be fed to an integrator IN having a time constant (T) equal to the duration of data packets. The start of a data packet which may be determined by carrier signal sense may be arranged to "clear" and release the integrator IN. At the end of the incoming data packet which is fed into the analogue store AS the clock will be correctly synchronised with the data timing and the integrator will be charged to the level of the pedestal voltage of the received data waveform. The integrator should therefore be switched to the 'hold' state 'T' seconds after its release. Thus the clock, in conjunction
with the sampler SA, effectively samples the data from the analogue store AS which has an integral bit delay corresponding exactly to the number of bits in a dat packet whilst the integrator output can be used as the slicing threshold.
As will be apparent from the foregoing description of one embodiment of the present invention, the invention is eminently suitable for use in both frequency hopping and packet radio systems and enables all the data packets received at the receiver R to be fully recovered without loss of any data bits of the packet due to the delay of the synchronising clock in acquiring to the incoming data timing. Moreover, the use of an integrator as just above desribed permits threshold determination of the incoming data signal to be achieved.
PCT WORLD INTELLECTUAL PROPERTY ORGANIZATION International Bureau
INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)
(51) International Patent Classification (11) International Publication Number: WO 88/ 01
A3 H04L 7/02,25/06 (43) International Publication Date: 11 February 1988 (11.0
(21) International Application Number: PCT/GB87/00531 (81) Designated States: AT (European patent), AU, BE ropean patent), CH (European patent), DE (E
(22) International Filing Date : 27 July 1987 (27.07.87) pean patent), FR (European patent), IT (Euro patent), JP, LU (European patent), NL (Europea tent), SE (European patent), US.
(31) Priority Application Number: 8618206
(32) Priority Date: 25 July 1986 (25.07.86) Published
With international search report.
(33) Priority Country: GB Before the expiration of the time limit for amendin claims and to be republished in the event of the recei amendments.
(71) Applicant (for all designated States except US): PLES-
SEY OVERSEAS LIMITED [GB/GB]; Vicarage (88) Date of publication of the international search report: Lane, Ilford, Essex IG1 4AQ (GB). 19 May 1988 (19.05.
(72) Inventor; and
(75) Inventor/ Applicant (for US only) : HULBERT, Anthony, Peter [GB/GB]; 6 Hanley Road, Shirley, Southampton (GB).
(74) Agent: SORENTI, Gino; The Plessey Company pic, Intellectual Property Department, Vicarage Lane, Ilford, Essex IG1 4AQ (GB).
(54) Title: IMPROVEMENTS RELATING TO DATA TRANSMISSION SYSTEMS
(57) Abstract
A data transmission system receiver comprising a data synchronisation unit and fϊrst-in first-out data store connected in parallel to receive incoming data signals, in which the data store delays the incoming data signals by a time period which corresponds to the time required for the synchronisation unit to achieve synchronisation of a clock with the incoming data signals and in which data gate or sampler means responsive to signals from the synchronisation unit indicating that synchronisation has been achieved enables data signals to be passed from the store to a data line.
FOR THE PURPOSES OFINFORMAHON ONLY
Codes used to identify States party to the PCT on the front pages of pamphlets publishing international applications under the PCT.
AT Austria FR France ML Mali
AU Australia GA Gabon MR Mauritania
•B Barbados GB United Kingdom MW Malawi-
BE Belgium HU Hungary NL Netherlands
BG Bulgaria IT Italy- NO Norway
BJ Benin JP Japan RO Romania
BR Brazil KP Democratic People's Republic SD Sudan
CF Central African Republic of Korea SE Sweden
CG CcngΛ KR Republic of Korea SN Senegal
CM Switzerland LI Liechtenstein SU Soviet Union
CM Cameroon LK Sri Lanka TD Chad
DE Germany, Federal Republic of LU Luxembourg TG Togo
DE Denmark MC Monaco US United States of America π Finland MG Madagascar
Claims
1. A data transmission system receiver comprising a data synchronisation unit and first-in first-out data store connected in parallel to receive incoming data signals, in which the data store delays the incoming data signals by a time period which corresponds to the time required for the synchronisation unit to acheive synchronisation of a clock with the incoming data signals and in which data gate or sampler means responsive to signals from the synchronisation unit indicating that clock synchronisation has been acheived enables data signals to be passed from the store to a data line.
2. A data transmission system receiver as claimed in claim 1, in which the data store is of analogue form.
3. A data transmission system receiver as claimed in claim 1 or claim 2, in which the synchronisation unit comprises a pulse shaper and a pair of monostable devices connected in parallel and responsive to the leading and trailing edges of incoming data bits, the output from the monostable devices being gated to an early/late gating circuit which serves to control advancement or retardation of a synchronisation clock to acheive synchronisation with incoming data signals.
4. A data transmission system receiver as claimed in claim 3, in which the early/late gating circuit provides an appropriate early or late signal which is fed to another gating circuit under the control of a counter which is also controlled by a signal derived from the early/late gating circuit, an advance or retard signal being accordingly applied to the synchronisation clock to provide synchronisation thereof with the incoming data signals.
5. A data transmission system receiver as claimed in claim 3 or claim 4, in which the synchronisation clock provides an output which is applied to a sampler which also receives the delayed data store output.
6. A data transmission system receiver as claimed in any preceding claim in which the incoming data signals are fed to an integrator having a time constant equal to the duration of incoming data packets whereby threshold determination of incoming data signals can be acheived.
7. A data transmission system receiver as claimed in any preceding claim, in which the data store provides for the reception of medium length data packets even though the store delay is shorter than the duration of the data packet.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8618206A GB2193863B (en) | 1986-07-25 | 1986-07-25 | Improvements relating to data transmission systems |
| GB8618206 | 1986-07-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP0276272A1 true EP0276272A1 (en) | 1988-08-03 |
Family
ID=10601693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP19870904907 Withdrawn EP0276272A1 (en) | 1986-07-25 | 1987-07-27 | Improvements relating to data transmission systems |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0276272A1 (en) |
| JP (1) | JPH01500950A (en) |
| AU (1) | AU592011B2 (en) |
| GB (1) | GB2193863B (en) |
| WO (1) | WO1988001118A2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE9300679L (en) * | 1993-03-01 | 1994-09-02 | Ellemtel Utvecklings Ab | bit synchronizer |
| JP3195274B2 (en) | 1997-06-16 | 2001-08-06 | 埼玉日本電気株式会社 | TDMA audio information reading device |
| JP4276647B2 (en) | 2005-08-25 | 2009-06-10 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor device |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1355495A (en) * | 1970-08-18 | 1974-06-05 | Cossor Ltd A C | Apparatus for clocking digital data |
| IT1026581B (en) * | 1974-11-27 | 1978-10-20 | Philips Spa | RECEIVER FOR BINARY PULSE SIGNAL TRANSMISSION SYSTEM INCLUDING A CIRCUIT FOR THE AUTOMATIC CORRECTION OF DISTURBANCES IN THE DIRECT CURRENT LEVEL |
| FR2429525A1 (en) * | 1978-06-20 | 1980-01-18 | Thomson Csf | DIGITAL TRANSMISSION SYNCHRONIZATION DEVICE AND TRANSMISSION SYSTEM COMPRISING SUCH A DEVICE |
| US4330863A (en) * | 1978-07-07 | 1982-05-18 | Wright Simon C M | Demodulator arrangement |
| JPS5823796B2 (en) * | 1978-10-19 | 1983-05-17 | 工業技術院長 | Imaging device |
| JPS5584007A (en) * | 1978-12-19 | 1980-06-24 | Matsushita Electric Ind Co Ltd | Recoder/reproducer of digital signal |
| JPS6016145B2 (en) * | 1979-03-20 | 1985-04-24 | 株式会社日立製作所 | Clock signal extraction method |
| JPS55146618A (en) * | 1979-04-27 | 1980-11-15 | Hitachi Ltd | Data synchronizing circuit |
| FR2498035B1 (en) * | 1981-01-09 | 1986-01-17 | Thomson Csf | METHOD AND DEVICE FOR SYNCHRONIZING MESSAGES |
| JPS60170377A (en) * | 1984-02-14 | 1985-09-03 | Sony Corp | Automatic black level controlling circuit |
| US4691375A (en) * | 1984-06-06 | 1987-09-01 | National Research Development Corporation | Data transmission using a transparent tone-in band system |
-
1986
- 1986-07-25 GB GB8618206A patent/GB2193863B/en not_active Expired - Lifetime
-
1987
- 1987-07-27 JP JP50444887A patent/JPH01500950A/en active Pending
- 1987-07-27 EP EP19870904907 patent/EP0276272A1/en not_active Withdrawn
- 1987-07-27 WO PCT/GB1987/000531 patent/WO1988001118A2/en not_active Application Discontinuation
- 1987-07-27 AU AU77543/87A patent/AU592011B2/en not_active Ceased
Non-Patent Citations (1)
| Title |
|---|
| See references of WO8801118A2 * |
Also Published As
| Publication number | Publication date |
|---|---|
| AU7754387A (en) | 1988-02-24 |
| AU592011B2 (en) | 1989-12-21 |
| WO1988001118A3 (en) | 1988-05-19 |
| GB8618206D0 (en) | 1986-12-17 |
| GB2193863A (en) | 1988-02-17 |
| GB2193863B (en) | 1990-12-12 |
| JPH01500950A (en) | 1989-03-30 |
| WO1988001118A2 (en) | 1988-02-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| 17P | Request for examination filed |
Effective date: 19880325 |
|
| AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH DE FR IT LI LU NL SE |
|
| RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: SIEMENS PLESSEY ELECTRONIC SYSTEMS LIMITED |
|
| 17Q | First examination report despatched |
Effective date: 19910705 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
| 18D | Application deemed to be withdrawn |
Effective date: 19911116 |