WO1987000674A3 - Memoire a circuit integre a l'echelle d'une tranche - Google Patents

Memoire a circuit integre a l'echelle d'une tranche Download PDF

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Publication number
WO1987000674A3
WO1987000674A3 PCT/GB1986/000400 GB8600400W WO8700674A3 WO 1987000674 A3 WO1987000674 A3 WO 1987000674A3 GB 8600400 W GB8600400 W GB 8600400W WO 8700674 A3 WO8700674 A3 WO 8700674A3
Authority
WO
WIPO (PCT)
Prior art keywords
pct
modules
memory
read
transmit path
Prior art date
Application number
PCT/GB1986/000400
Other languages
English (en)
Other versions
WO1987000674A2 (fr
Inventor
Michael Brent
Neal Macdonald
Original Assignee
Anamartic Ltd
Michael Brent
Neal Macdonald
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB8517699A external-priority patent/GB2177825B/en
Application filed by Anamartic Ltd, Michael Brent, Neal Macdonald filed Critical Anamartic Ltd
Priority to AT86904285T priority Critical patent/ATE71762T1/de
Priority to DE8686904285T priority patent/DE3683477D1/de
Publication of WO1987000674A2 publication Critical patent/WO1987000674A2/fr
Priority to KR870700212A priority patent/KR880700422A/ko
Publication of WO1987000674A3 publication Critical patent/WO1987000674A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

Une mémoire à circuit intégré à l'échelle d'une tranche comprend quelques centaines de modules (10) qui peuvent être connectés dans une longue chaîne par des commandes envoyées aux modules le long d'un chemin de transmission établi par des entrées de modules (XINN, XINE, XINS, XINW) à partir de modules voisins et de sorties vers ces modules (XOUTN, XOUTE, XOUTS, XOUTW), seul l'un d'eux est validé par l'un des quatre signaux de sélection (SELN, SELE, SELS, SELW) agissant à la fois sur une logique d'un chemin de transmission (20) et sur une logique d'un chemin de réception (21) dans un chemin de retour. Chaque module comprend une logique de configuration (22) qui décode des commandes fournissant les signaux de sélection (SELN, etc), un signal de LECTURE et un signal d'ECRITURE. La logique de configuration (22) est adressée lorsqu'un bit est présenté à celle-ci par le chemin de transmission simultanément avec excitation d'un signal (CMND) qui est envoyé de manière générale à tous les modules. La logique de configuration d'adresse synchronise le bit le long d'un registre à décalage et la commande sélectionnée est déterminée par la position du bit au moment où le signal globale (CMND) est terminé. Chaque module comprend une unité de mémoire (23) contenant un compteur d'adresse à déroulement libre. Lorsque la commande ECRITURE apparaît, un flot de données sur le chemin de transmission est mémorisé dans la mémoire. Lorsque la commande LECTURE apparaît, le contenu de la mémoire est extrait de la mémoire et passe sur le chemin retour. La régénération de la mémoire s'effectue d'une manière conventionnelle sous la commande du compteur d'adresse à déroulement libre. De manière à éviter la présence d'un courant fort dans l'un quelconque des conducteurs de distribution d'alimentation sur la tranche, les cycles de comptage des compteurs d'adresse à déroulement libre sont alternés.
PCT/GB1986/000400 1985-07-12 1986-07-11 Memoire a circuit integre a l'echelle d'une tranche WO1987000674A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AT86904285T ATE71762T1 (de) 1985-07-12 1986-07-11 Scheibenbereichsschaltungsintegrierter speicher.
DE8686904285T DE3683477D1 (de) 1985-07-12 1986-07-11 Scheibenbereichsschaltungsintegrierter speicher.
KR870700212A KR880700422A (ko) 1985-07-12 1987-03-12 웨이퍼 규모의 집적회로 메모리

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB8517699 1985-07-12
GB8517699A GB2177825B (en) 1985-07-12 1985-07-12 Control system for chained circuit modules
GB08525324A GB2178204B (en) 1985-07-12 1985-10-15 Wafer-scale integrated circuit memory
GB8525324 1985-10-15

Publications (2)

Publication Number Publication Date
WO1987000674A2 WO1987000674A2 (fr) 1987-01-29
WO1987000674A3 true WO1987000674A3 (fr) 1987-03-26

Family

ID=26289520

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1986/000400 WO1987000674A2 (fr) 1985-07-12 1986-07-11 Memoire a circuit integre a l'echelle d'une tranche

Country Status (5)

Country Link
US (1) US5072424A (fr)
EP (1) EP0229144B1 (fr)
AT (1) ATE71762T1 (fr)
DE (1) DE3683477D1 (fr)
WO (1) WO1987000674A2 (fr)

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US5191224A (en) * 1987-04-22 1993-03-02 Hitachi, Ltd. Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein
GB8825780D0 (en) * 1988-11-03 1988-12-07 Microcomputer Tech Serv Digital computer
US5203005A (en) * 1989-05-02 1993-04-13 Horst Robert W Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement
GB9305801D0 (en) * 1993-03-19 1993-05-05 Deans Alexander R Semiconductor memory system
US6009501A (en) * 1997-06-18 1999-12-28 Micron Technology, Inc. Method and apparatus for local control signal generation in a memory device
US6032220A (en) * 1997-07-18 2000-02-29 Micron Technology, Inc. Memory device with dual timing and signal latching control
KR20050022798A (ko) * 2003-08-30 2005-03-08 주식회사 이즈텍 유전자 어휘 분류체계를 이용하여 바이오 칩을 분석하기위한 시스템 및 그 방법
US8375146B2 (en) * 2004-08-09 2013-02-12 SanDisk Technologies, Inc. Ring bus structure and its use in flash memory systems
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
KR101303518B1 (ko) 2005-09-02 2013-09-03 구글 인코포레이티드 Ｄｒａｍ 적층 방법 및 장치
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
WO2010144624A1 (fr) 2009-06-09 2010-12-16 Google Inc. Programmation de valeurs de résistance de terminaison dimm

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3913072A (en) * 1972-08-03 1975-10-14 Ivor Catt Digital integrated circuits

Family Cites Families (7)

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Publication number Priority date Publication date Assignee Title
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JPH0762958B2 (ja) * 1983-06-03 1995-07-05 株式会社日立製作所 Ｍｏｓ記憶装置
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Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
US3913072A (en) * 1972-08-03 1975-10-14 Ivor Catt Digital integrated circuits

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Volume 13, No. 8, January 1971, (New York, US) R. VEIT: "Increased Packing Density of Monolithic Storages", page 2436 *
PATENTS ABSTRACTS OF JAPAN, Volume 2, No. 156, (10217)(E-78) 26 December 1978, & JP, A, 53-126229 (Nippon Denki K.K.) 11 April 1978 *

Also Published As

Publication number Publication date
WO1987000674A2 (fr) 1987-01-29
US5072424A (en) 1991-12-10
ATE71762T1 (de) 1992-02-15
EP0229144A1 (fr) 1987-07-22
DE3683477D1 (de) 1992-02-27
EP0229144B1 (fr) 1992-01-15

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