WO1986007164A1 - Systeme d'affichage a laser - Google Patents

Systeme d'affichage a laser Download PDF

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Publication number
WO1986007164A1
WO1986007164A1 PCT/AU1986/000152 AU8600152W WO8607164A1 WO 1986007164 A1 WO1986007164 A1 WO 1986007164A1 AU 8600152 W AU8600152 W AU 8600152W WO 8607164 A1 WO8607164 A1 WO 8607164A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
computer
buffer
programme
laser
Prior art date
Application number
PCT/AU1986/000152
Other languages
English (en)
Inventor
Paul Stephen Mccloskey
Bruce Gilbert Williams
Cecil William George Langdown
Original Assignee
Lusher, Mark, Edwin, Fenn
Samrein Pty. Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lusher, Mark, Edwin, Fenn, Samrein Pty. Limited filed Critical Lusher, Mark, Edwin, Fenn
Publication of WO1986007164A1 publication Critical patent/WO1986007164A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/02—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes by tracing or scanning a light beam on a screen

Definitions

  • Known computer control laser display systems comprise a pair of mirrors mounted on precision galvanometers which deflect the beam in an x-y plane, in response to X, Y co-ordinates provided by the computer.
  • the laser beam can be made to trace a desired pattern on a screen. If the pattern is swept by the beam at a sufficiently high rate, the traced pattern will appear to be continuously illuminated to the human eye.
  • the laser can then be used in applications such as advertising, light shows and the production of special effects.
  • the computer is able to supply data to the data buffer at a rate which is sufficiently high that from time to time the data buffer is unable to accept any further information.
  • the data buffer is provided with a first signal output indicating that the buffer is no longer capable of accepting data and a second signal output indicating that the data buffer has attained or exceeded a predetermined degree of emptiness.
  • first and second signals produced by the data buffer are used to interrupt the operation of the computer to switch between first and second programmes running in the computer, the first programme being a programme to calculate and output data co-ordinates to the buffer this programme being initiated or resumed upon the occurrence of the second signal from the data buffer and being halted by the occurrence of the first signal from the data buffer, while the second programme is a programme which provides a user interface and allows generation storage and retrieval of images to be displayed, the second programme being initiated or recommenced by the occurrence of " the first signal and being halted by the occurrence of the second signal from the data buffer.
  • the data buffer comprises a First In First Out (FIFO) buffer having a Buffer Full signal as its first signal and a Buffer Half Empty signal as its second signal, such that when the Half Empty signal is active, the computer is interrupted and switches to the output programme which then proceeds to calculate co-ordinate data and output that data to the FIFO buffer, until such time as the full signal once again interrupts the processor causing the output programme to be terminated and the user interface programme to be recommenced.
  • FIFO First In First Out
  • This "spare" processor time is also used to perform housekeeping functions and to queue images to the output programme.
  • the present invention consists in an interface circuit for interfacing between a computer and the laser beam position control device comprising addressing means for addressing a plurality of programme modes of said computer and a first-in-first-out (FIFO) memory with two interrupt signals for interrupting programmes running in the computer, said memory adapted to receive laser beam position data from said computer, a first of said interrupts being generated when the FIFO memory is "nearly empty” and the other of said interrupts being generated when the FIFO memory is “full” and the interrupts being fed to the computer to cause the computer to switch between two programmes running to the computer.
  • FIFO first-in-first-out
  • Fig. 1 schematically illustrates a laser -display system in accordance with the present invention
  • Fig. 3 schematically illustrates a second embodiment of part of the buffer connecting the computer and digital to analogue converters of Fig. 1;
  • Fig. 4 is a circuit diagram of the interface circuit of the preferred embodiment.
  • Fig. 5 is a flow chart of a programme scheduling routine associated with interrupts generated by an output buffer in accordance with the present invention.
  • the laser beam produced by laser 19 is directed by laser control means 5.
  • the laser control means 5 comprises mirrors 17, 18 mounted on precision galvanometer mechanisms 21, 22.
  • a shutter 20 can also be induced to interrupt the beam.
  • two mirrors 17, 18 oscillating in orthogonal directions are provided to direct the beam in an X-Y plane.
  • the galvanometers 21, .22 are driven by analog voltage deflection signals 23, 24 which are amplified by amplifiers 15, 16. These analog deflection signals are obtained from two eight-bit digital to analog convertors 13, 14 which form part of the interface between a computer 10 and the laser control system 5.
  • the digital to analog convertors 13, 14, obtain the digital values from a first-in-first-out (FIFO) memory configured as two parallel FIFO buffers, which preferably also provides two extra bits, one for shutter control and the other for clock selection, such that the FIFO memory is in effect 18 bits wide.
  • the clock selection bit allows different channels on a programmable timer to be selected. These control the output clocking of the FIFO memory and hence the rate at which the galvanometers are updated with new position/co-ordinate values. Thus, different -parts of a complex image can be written at different rates giving an increased flexibility.
  • interrupts are communicated to the computer to cause the computer to switch between two programmes running in the computer, an application programme 43 typically written is BASIC (a language in which many programmers are fluent) , and a computation programme 42 written in machine language and used to calculate the data for the FIFO memory.
  • interrupt 34 causes the computer to switch to the application programme 43, for example to receive keyboard instructions from the operator or to accept preprogrammed instructions.
  • computer interrupt 34 causes the computer to switch to the computation programme to calculate more co-ordinate data for the laser control device.
  • the computation programme is written in machine language for rapid execution.
  • the use of the "full" interrupt 35 allows the machine language routine to execute without the normal practice of continually testing an interface to determine if it can accept data, a time consuming requirement of known laser display systems.
  • the machine language programme 42 performs some computations, adding offsets to various parts of images and performing the interpolations between images. It is relatively simple to add new computational functions to this programme.
  • the machine language programme is driven by tables held in memory and by images referenced by the tables.
  • An additional suite of functions can be included in machine language programmes to interface between the BASIC language application programme and the machine language programme described above.
  • These interface programmes convert data from the formats used by BASIC to formats that are much more efficient for the programmes that are updating the FIFO memory 13, 14, and make it much easier for the BASIC application programme to manipulate images in a form suited thereto.
  • the illustrated embodiment of a laser display system comprises a computer 10 in which is stored representations of images to be displayed by the laser display system, the computer including an output programme designed to output co-ordinate data, in the form of X co-ordinates and Y co-ordinates, defining the trajectory of the laser beam to be produced by the display system.
  • the X co-ordinates and Y co-ordinates produced by the computer 10 are respectively fed to an X co-ordinate buffer 11 and a Y co-ordinate buffer 12 which are parallel First In First Out buffers and which effectively form a single eighteen bit wide FIFO buffer.
  • the outputs of the FIFO buffer 11, 12 are fed to respective digital to analogue converters 13 and 14 which in turn produce signals to drive the X and Y galvanometer and mirror assemblies 17 and 18 respectively, the signal being amplified by amplifiers 15 and 16 before being applied to the galvanometers.
  • the laser 19 produces a beam which is directed at the mirror of the X co-ordinate mirror and galvanometer assembly 17 which generates a horizontal deflection of the beam. From the "X mirror” , the beam is deflected onto the mirror of the Y mirror and galvanometer assembly 18 which in turn produces a vertical deflection of the laser beam.
  • the laser beam may be interrupted by a gate 20 which is controlled by one bit of the co-ordinates generated at the output of the FIFO buffer, this gate being used to generate blank spots in the laser display.
  • a gate 20 which is controlled by one bit of the co-ordinates generated at the output of the FIFO buffer, this gate being used to generate blank spots in the laser display.
  • the use of output buffers enables the processor to output data at its own rate, independent of the rate at which the data is required by the laser control electronics and therefore overheads relating to interrupt processing are significantly reduced, leaving more time for tasks such as real-time recalculation of co-ordinates when moving an animated display for example, as well as allowing time for the processing of user inputs. Therefore, while the processor is outputing one display pattern, the user can be creating a new pattern on a video terminal and this new pattern can be displayed as soon as the creation is completed.
  • FIG. 2 a more detailed schematic illustration of one half of the data buffer of the preferred embodiment is shown.
  • the X buffer 11 of Figure 1 is realised using a pair of FIFO buffers 31 and 32 connected in series, each of the FIFO buffers having a status output which indicates when the buffer is full.
  • These status outputs are used to generate interrupts to the process 10, the status line from buffer 31 being used to indicate when the combined buffer is full and the status line from buffer 32 being inverted by a gate 33 to generate an interrupt when the combined buffer is less than half full.
  • Each of the interrupts causes the processor 10 to enter an interrupt service routine which is effectively a programme scheduling routine 41. ' This scheduling routine saves the current stack pointer for the programme that was running in the computer immediately prior to the interrupt, loads a new stack pointer relating to the programme that is to be resumed as a result of the interrupt and then executes a return from interrupt instruction.
  • the microprocessor used in the computer 10 is a Motorola 6809 (registered trade mark) , in which the programme counter is stored on the stack together with the remainder of the machine registers upon the occurrence of an interrupt and therefore by replacing the stack pointer and executing a return from interrupt instruction, the programme scheduling routine effectively switches operation of the computer from one programme to another.
  • the computer When the display system is first turned on, the computer is initialized and commences executing the real-time programme 42 which calculates and outputs the co-ordinates for the first image to be displayed.
  • This programme simply calculates each co-ordinate set and outputs the co-ordinates, one at a time, to a peripheral interface adaptor (PIA) which loads the data into the X and Y buffers respectively, while the programme goes on to calculate the next co-ordinate and in turn writes this new co-ordinate into the PIA.
  • PDA peripheral interface adaptor
  • the programme always assumes that data previously written to the PIA will have been loaded into the X and Y buffers by the time the next co- ordinate is written and therefore the programme is able to rapidly output a block of data which will fill the combined X buffers 31, 32 and the respective Y buffers, without the need to continuously check the status of the PIA.
  • the Buffer Full signal from the X buffer 31 will generate an interrupt which causes the programme scheduling routine 41 to run and this routine in turn halts operation of the real-time programme 42 and transfers operation to the user interface routine 43, thereby allowing the user to enter new images. edit old images or define sequences of images to be displayed.
  • the user interface routine 43 also queues images to be displayed such that the next image required by the output routine 42 is always available to it. Meanwhile, the FIFO buffers output their contents to the digital to analogue converters 13 and 14 at a relatively constant rate, as required by the display electronics, until shortly after the first part of the X buffer 31 empties, when the full signal of the second part of the X buffer 32 will change state, causing a Less Than Half Full interrupt to be generated. This interrupt once again causes the programme scheduling routine 41 to run in the computer 10 and this routine in turn switches control back to the co-ordinate calculating and output routine 42 which then commences to calculate the next sequence of output co-ordinates and output these to the FIFO buffers.
  • FIG. 5 A flow chart for the programme scheduling routine 41 is illustrated in Fig. 5.
  • an automatic interrupt sequence is initiated which pushes the current instruction register (return address) data register and status register contents onto the stack and then passes control to the routine described by the Fig. 5 flow chart.
  • This routine pops the various register contents saved by the processors interrupt sequence and saves these in a temporary storage reserved for the interrupted programme for this purpose.
  • the interrupt routine then pushes the instruction register valve and other saved register contents relating to a programme to be commenced as a result of the interrupt.
  • This data is retrieved from a second temporary register storage area associated with the second programme. In this manner, control is transferred from one programme to another, alternately, as the buffer empties and fills.
  • each shift register can be made one bit wider than required, the serial input for the additional bit being set when the register is being loaded and reset when the register is being unloaded such that transitions of this bit at the serial output indicate the empty and full state respectively.
  • the software required in computer 10 to operate with the buffer of Figure 3 is essentially the same as that previously described with reference to the buffer of Figure 2.
  • the interface circuit consists basically of a MC6840 timer chip (ICI), a MC6821 peripheral interface adaptor (PIA) chip (IC2), four AM2813 first-in-first-out (FIFO) memory chips (IC3-IC6) , and two DAC0800 digital to analog convertors (IC7 and IC8) which operate in conjunction with amplifiers, together with their associated circuitry (IC19a and b) .
  • ICI MC6840 timer chip
  • PDA peripheral interface adaptor
  • IC3-IC6 four AM2813 first-in-first-out (FIFO) memory chips
  • DAC0800 digital to analog convertors IC7 and IC8 which operate in conjunction with amplifiers, together with their associated circuitry (IC19a and b) .
  • Address decoding is carried out by IC10 a, b; ICll a, b; IC12 a, b, c, d and e.
  • Addresses FF74 to FF77 are used in controlling and setting up the PIA (IC2) as shown in Table 1.
  • the PIA (IC2) data direction registers A and B are set so that both peripheral interface ports A (PAO-7) and B (PBO-7) are used as output ports.
  • the control registers are set such that interrupt line CAl detects (with IC14 a and b) when the FIFO buffer (IC3, 4, 5 and 6) is full and interrupt CBl detects when the FIFO buffer (IC3, 4, 5 and 6) is "nearly empty". The nearly empty state is indicated in this embodiment when the buffer is less than half empty,
  • CB2 is set as a control signal and strobes the data when available into FIFO's IC3 and 5.
  • CA2 is set to control the *D' type flip-flop IC15 which via the FIFO data bit D8 controls: a) the FIFO output clock (IC3 and 4) , and b) the operation of a shutter (not shown) to control the laser output (IC5 and 6) .
  • the timer chip (ICI) is set to produce two frequencies one of which is selected by IC16 to control the output from the FIFO's (IC3, 4, 5 and 6).
  • the frequency selected is controlled by FIFO data bit 8 (IC3 and 4) and the 2:1 MUX chip IC16.
  • the output from the Timer No 2 output is used to control the FIFO .output when displaying images, with control being changed to the timer No 1 output for character display. Both the timer output frequencies have been selected to be less than the input strobe so that interrupt control can be achieved.
  • the FIFO memory chips (IC3, 4, 5 and 6) are connected as two serially connected pairs to provide two parallel 64 x 9 bit buffer memories.
  • the 9 bit consisting of 8 data bits + 1 bit (D8) used as a control function.
  • the control function associated with the second of the parallel buffer memory is used to control the speed at which the data bits are removed from the FIFO' s.
  • the control bit associated with the second of the parallel buffer memory can be used to control the laser output.
  • IC7 and IC8 are 8 bit high speed digital-to-analog convertors. IC7 controls the 'X' axis of the laser image whilst IC8 controls the 'Y' axis.
  • Operational amplifiers IC9 a and b convert the current output of the D/A convertors to + 8 volts output to drive the laser "X" and “Y” amplifier circuits respectively.
  • a reference voltage required by the D/A convertors is supplied by an 8 volt regulator IC17.
  • the D/A and amplifier circuits IC7 with IC9a and IC8 with IC9b are arranged to give + 8 volts when the input data are all ' 1' s and -8 volts when this data are all 'O's.
  • the output from the laser card is taken via a 9 pin "D" type connector to the laser unit.
  • the interface is designed for operation with a Hitachi Peach computer, with disk drives and digitiser.
  • the interface circuit can be repackaged to suit an Hitachi Si computer (a compatible upgrade of the MB 6890 computer) , or the interface circuit can be implemented by "black box" units containing their own micro processors, but co-ordinated by a central computer.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

Système de commande de laser comprenant un ordinateur (10), un tampon de sortie (11, 12) et un circuit de commande de laser (13, 14, 15, 16, 17, 18, 21, 22). Le circuit de commande de laser comprend des miroirs de déflexion de laser (17, 18) destinés à commander les coordonnées des X et des Y du rayon laser, les miroirs étant pivotés par des galvanomètres de précision (21, 22), qui sont à leur tour dirigés par des convertisseurs analogiques/numériques (13, 14). Les données pour les convertisseurs analogiques/numériques sont mémorisées dans des tampons premier-entré-premier-sorti (11, 12) aussi longtemps qu'on le désire, les tampons premier-entré-premier-sorti étant périodiquement remplis par un programme d'extraction fonctionnant dans l'ordinateur (10). Lorsque les tampons premier-entré-premier-sorti sont pleins, un interrupteur de programme arrête le programme d'extraction, permettant ainsi au processeur de poursuivre ses autres tâches jusqu'au moment où un autre interrupteur de programme est produit, ledit interrupteur de programme signalant que les tampons ont atteint un degré prédéterminé de vide, moment où le programme d'extraction est de nouveau mis en route.
PCT/AU1986/000152 1985-05-31 1986-05-29 Systeme d'affichage a laser WO1986007164A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
AUPH084385 1985-05-31
AUPH0843 1985-05-31
AUPH2414 1985-09-13
AUPH241485 1985-09-13

Publications (1)

Publication Number Publication Date
WO1986007164A1 true WO1986007164A1 (fr) 1986-12-04

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PCT/AU1986/000152 WO1986007164A1 (fr) 1985-05-31 1986-05-29 Systeme d'affichage a laser

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EP (1) EP0227702A4 (fr)
WO (1) WO1986007164A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0326158A2 (fr) * 1988-01-27 1989-08-02 Kabushiki Kaisha Toshiba Méthode et dispositif pour l'agrandissement de données d'affichage engendrées dans un système à ordinateur
EP0590807A2 (fr) * 1992-10-01 1994-04-06 Hudson Soft Co., Ltd. Appareil de traitement de données de sons et d'images
US8522489B2 (en) 2009-03-18 2013-09-03 Sdk, Llc Component for buildings

Citations (3)

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Publication number Priority date Publication date Assignee Title
US4213146A (en) * 1978-03-24 1980-07-15 Laser Video, Inc. Scanning system for light beam displays
US4532402A (en) * 1983-09-02 1985-07-30 Xrl, Inc. Method and apparatus for positioning a focused beam on an integrated circuit
EP0150521A2 (fr) * 1980-04-25 1985-08-07 Data General Corporation Système processeur de données à traitement d'interruptions

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US3898627A (en) * 1974-03-22 1975-08-05 Ibm Optical printer having serializing buffer for use with variable length binary words
US4003626A (en) * 1974-06-14 1977-01-18 Eastman Kodak Company Distortion correction apparatus for electro-optical reflectors which scan beams to produce images
US4484302A (en) * 1980-11-20 1984-11-20 International Business Machines Corporation Single screen display system with multiple virtual display having prioritized service programs and dedicated memory stacks
FR2496314A1 (fr) * 1980-12-12 1982-06-18 Texas Instruments France Procede et dispositif pour permettre l'echange d'information entre des systemes de traitement d'information a vitesses de traitement differentes
US4486854A (en) * 1981-10-15 1984-12-04 Codex Corporation First-in, first-out memory system

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US4213146A (en) * 1978-03-24 1980-07-15 Laser Video, Inc. Scanning system for light beam displays
EP0150521A2 (fr) * 1980-04-25 1985-08-07 Data General Corporation Système processeur de données à traitement d'interruptions
US4532402A (en) * 1983-09-02 1985-07-30 Xrl, Inc. Method and apparatus for positioning a focused beam on an integrated circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Journal of Physics, Part E: Scientific Instruments, Volume 17, 1984 (Great Britain), K.C.A. KRANE and J.V. SLERINS 'Microcomputer-Controlled Scanning of a Laser Beam at Constant Speed', pages 363 to 367 *
See also references of EP0227702A4 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0326158A2 (fr) * 1988-01-27 1989-08-02 Kabushiki Kaisha Toshiba Méthode et dispositif pour l'agrandissement de données d'affichage engendrées dans un système à ordinateur
EP0326158A3 (fr) * 1988-01-27 1990-11-07 Kabushiki Kaisha Toshiba Méthode et dispositif pour l'agrandissement de données d'affichage engendrées dans un système à ordinateur
US5138700A (en) * 1988-01-27 1992-08-11 Kabushiki Kaisha Toshiba Method and apparatus for magnifying display data generated in a computer system using an overhead projector
EP0590807A2 (fr) * 1992-10-01 1994-04-06 Hudson Soft Co., Ltd. Appareil de traitement de données de sons et d'images
EP0590807A3 (fr) * 1992-10-01 1996-06-05 Hudson Soft Co., Ltd. Appareil de traitement de données de sons et d'images
US8522489B2 (en) 2009-03-18 2013-09-03 Sdk, Llc Component for buildings

Also Published As

Publication number Publication date
EP0227702A4 (fr) 1990-07-03
EP0227702A1 (fr) 1987-07-08

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