WO1986001638A1 - Semiconductor integrated circuits gettered with phosphorus - Google Patents

Semiconductor integrated circuits gettered with phosphorus Download PDF

Info

Publication number
WO1986001638A1
WO1986001638A1 PCT/US1985/001512 US8501512W WO8601638A1 WO 1986001638 A1 WO1986001638 A1 WO 1986001638A1 US 8501512 W US8501512 W US 8501512W WO 8601638 A1 WO8601638 A1 WO 8601638A1
Authority
WO
WIPO (PCT)
Prior art keywords
phosphorus
gettered
integrated circuits
semiconductor integrated
top surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1985/001512
Other languages
English (en)
French (fr)
Inventor
John Vincent Dalton
Kenneth Jeffrey Orlowsky
Ashok Kumar Sinha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Priority to KR1019860700222A priority Critical patent/KR930010983B1/ko
Priority to DE8585904051T priority patent/DE3581285D1/de
Publication of WO1986001638A1 publication Critical patent/WO1986001638A1/en
Anticipated expiration legal-status Critical
Priority to SG835/91A priority patent/SG83591G/en
Priority to HK448/92A priority patent/HK44892A/xx
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/06—Gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/061—Gettering-armorphous layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Bipolar Transistors (AREA)
PCT/US1985/001512 1984-08-21 1985-08-06 Semiconductor integrated circuits gettered with phosphorus Ceased WO1986001638A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019860700222A KR930010983B1 (ko) 1984-08-21 1985-08-06 반도체 집적회로 제조방법
DE8585904051T DE3581285D1 (de) 1984-08-21 1985-08-06 Mit phosphor gegetterte integrierte halbleiterschaltungen.
SG835/91A SG83591G (en) 1984-08-21 1991-10-11 Semiconductor integrated circuits gettered with phosphorus
HK448/92A HK44892A (en) 1984-08-21 1992-06-18 Semiconductor integrated circuits gettered with phosphorus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/642,932 US4589928A (en) 1984-08-21 1984-08-21 Method of making semiconductor integrated circuits having backside gettered with phosphorus
US642,932 1984-08-21

Publications (1)

Publication Number Publication Date
WO1986001638A1 true WO1986001638A1 (en) 1986-03-13

Family

ID=24578648

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1985/001512 Ceased WO1986001638A1 (en) 1984-08-21 1985-08-06 Semiconductor integrated circuits gettered with phosphorus

Country Status (9)

Country Link
US (1) US4589928A (https=)
EP (1) EP0192668B1 (https=)
JP (1) JPS61503064A (https=)
KR (1) KR930010983B1 (https=)
CA (1) CA1226073A (https=)
DE (1) DE3581285D1 (https=)
HK (1) HK44892A (https=)
SG (1) SG83591G (https=)
WO (1) WO1986001638A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2731841A1 (fr) * 1995-03-07 1996-09-20 Nippon Denso Co Transistors a effet de champ du type a grille isolee et son procede de fabrication
EP0376479B1 (en) * 1988-11-28 1999-06-02 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device having a phospho silicate glass layer as an interlayer insulating layer
US5925911A (en) * 1995-04-26 1999-07-20 Nippondenso Co., Ltd. Semiconductor device in which defects due to LOCOS or heat treatment are suppressed

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3585286D1 (de) * 1985-06-17 1992-03-05 Sony Corp Herstellungsverfahren fuer halbleiteranordnungen.
US5084413A (en) * 1986-04-15 1992-01-28 Matsushita Electric Industrial Co., Ltd. Method for filling contact hole
US4732865A (en) * 1986-10-03 1988-03-22 Tektronix, Inc. Self-aligned internal mobile ion getter for multi-layer metallization on integrated circuits
US4966865A (en) * 1987-02-05 1990-10-30 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
US4753709A (en) * 1987-02-05 1988-06-28 Texas Instuments Incorporated Method for etching contact vias in a semiconductor device
US4795722A (en) * 1987-02-05 1989-01-03 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
US5244819A (en) * 1991-10-22 1993-09-14 Honeywell Inc. Method to getter contamination in semiconductor devices
US5223734A (en) * 1991-12-18 1993-06-29 Micron Technology, Inc. Semiconductor gettering process using backside chemical mechanical planarization (CMP) and dopant diffusion
US5229305A (en) * 1992-02-03 1993-07-20 Motorola, Inc. Method for making intrinsic gettering sites in bonded substrates
US5543335A (en) * 1993-05-05 1996-08-06 Ixys Corporation Advanced power device process for low drop
US5559052A (en) * 1994-12-29 1996-09-24 Lucent Technologies Inc. Integrated circuit fabrication with interlevel dielectric
US5573633A (en) * 1995-11-14 1996-11-12 International Business Machines Corporation Method of chemically mechanically polishing an electronic component
US6090707A (en) 1999-09-02 2000-07-18 Micron Technology, Inc. Method of forming a conductive silicide layer on a silicon comprising substrate and method of forming a conductive silicide contact
US6383924B1 (en) * 2000-12-13 2002-05-07 Micron Technology, Inc. Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials
US6958264B1 (en) * 2001-04-03 2005-10-25 Advanced Micro Devices, Inc. Scribe lane for gettering of contaminants on SOI wafers and gettering method
US7142577B2 (en) * 2001-05-16 2006-11-28 Micron Technology, Inc. Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon
US6898362B2 (en) * 2002-01-17 2005-05-24 Micron Technology Inc. Three-dimensional photonic crystal waveguide structure and method
US7132348B2 (en) * 2002-03-25 2006-11-07 Micron Technology, Inc. Low k interconnect dielectric using surface transformation
US6987037B2 (en) * 2003-05-07 2006-01-17 Micron Technology, Inc. Strained Si/SiGe structures by ion implantation
US7008854B2 (en) * 2003-05-21 2006-03-07 Micron Technology, Inc. Silicon oxycarbide substrates for bonded silicon on insulator
US7501329B2 (en) * 2003-05-21 2009-03-10 Micron Technology, Inc. Wafer gettering using relaxed silicon germanium epitaxial proximity layers
US7273788B2 (en) 2003-05-21 2007-09-25 Micron Technology, Inc. Ultra-thin semiconductors bonded on glass substrates
US7662701B2 (en) * 2003-05-21 2010-02-16 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US7439158B2 (en) * 2003-07-21 2008-10-21 Micron Technology, Inc. Strained semiconductor by full wafer bonding
US6929984B2 (en) * 2003-07-21 2005-08-16 Micron Technology Inc. Gettering using voids formed by surface transformation
US7153753B2 (en) * 2003-08-05 2006-12-26 Micron Technology, Inc. Strained Si/SiGe/SOI islands and processes of making same
JP4134199B2 (ja) * 2006-05-25 2008-08-13 エルピーダメモリ株式会社 半導体装置の製造方法
TWI355046B (en) * 2007-07-10 2011-12-21 Nanya Technology Corp Two bit memory structure and method of making the
US8541305B2 (en) * 2010-05-24 2013-09-24 Institute of Microelectronics, Chinese Academy of Sciences 3D integrated circuit and method of manufacturing the same
US8994118B2 (en) * 2013-04-04 2015-03-31 Monolith Semiconductor, Inc. Semiconductor devices comprising getter layers and methods of making and using the same
US9425153B2 (en) 2013-04-04 2016-08-23 Monolith Semiconductor Inc. Semiconductor devices comprising getter layers and methods of making and using the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984001052A1 (en) * 1982-09-03 1984-03-15 Ncr Co Process for forming a cmos structure
US4463491A (en) * 1982-04-23 1984-08-07 Gte Laboratories Incorporated Method of fabricating a monolithic integrated circuit structure

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US3740835A (en) * 1970-08-31 1973-06-26 Fairchild Camera Instr Co Method of forming semiconductor device contacts
NL7100275A (https=) * 1971-01-08 1972-07-11
US3997368A (en) * 1975-06-24 1976-12-14 Bell Telephone Laboratories, Incorporated Elimination of stacking faults in silicon devices: a gettering process
US4018626A (en) * 1975-09-10 1977-04-19 International Business Machines Corporation Impact sound stressing for semiconductor devices
FR2340619A1 (fr) * 1976-02-04 1977-09-02 Radiotechnique Compelec Perfectionnement au procede de fabrication de dispositifs semiconducteurs et dispositifs ainsi obtenus
US4053335A (en) * 1976-04-02 1977-10-11 International Business Machines Corporation Method of gettering using backside polycrystalline silicon
US4151631A (en) * 1976-09-22 1979-05-01 National Semiconductor Corporation Method of manufacturing Si gate MOS integrated circuit
US4114256A (en) * 1977-06-24 1978-09-19 Bell Telephone Laboratories, Incorporated Reliable metal-to-junction contacts in large-scale-integrated devices
US4131487A (en) * 1977-10-26 1978-12-26 Western Electric Company, Inc. Gettering semiconductor wafers with a high energy laser beam
DE2829983A1 (de) * 1978-07-07 1980-01-24 Siemens Ag Verfahren zum gettern von halbleiterbauelementen und integrierten halbleiterschaltkreisen
US4291322A (en) * 1979-07-30 1981-09-22 Bell Telephone Laboratories, Incorporated Structure for shallow junction MOS circuits
JPS5674939A (en) * 1979-11-22 1981-06-20 Toshiba Corp Preparation method of semiconductor integrated circuit
JPS5766673A (en) * 1980-10-09 1982-04-22 Toshiba Corp Manufacture of mos type semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4463491A (en) * 1982-04-23 1984-08-07 Gte Laboratories Incorporated Method of fabricating a monolithic integrated circuit structure
WO1984001052A1 (en) * 1982-09-03 1984-03-15 Ncr Co Process for forming a cmos structure

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
Extended Abstracts of the Journal of the Electrochemical Society, Volume 82-2 October 1982, Pennington, New Jersey, (US) J.M. ANDREWS et al.: "Gettering at Lower Temperatures by Phosphorus Diffusion and Back Surface Damage", pages 231-232, see page 231, column 1, paragraph 1 - column 2, paragraph 2 *
PATENTS ABSTRACTS OF JAPAN, Volume 6, No. 234, 20 November 1982, (E-143) (1112) & JP, A, 57134937 (Nippon Denki K.K.) 20 August 1982 *
PATENTS ABSTRACTS OF JAPAN, Volume 6, No. 95 (E-110) (973) & JP, A, 5728353 (T. Takaira) 16 February 1982 *
PATENTS ABSTRACTS OF JAPAN, Volume 7, No. 233, 15 October 1983, page 1378 & JP, A, 58121630 (Toshiba) 20 July 1983 *
PATENTS ABSTRACTS OF JAPAN, Volume 8, No. 268, 7 December 1984, (E-283) (1705) & JP, A, 59138338 (A. Shimizu) 8 August 1984 *
PATENTS ABSTRACTS OF JAPAN, Volume 9, No. 95 (E-310) (1818) & JP, A, 59222939 (Hitachi) 14 December 1984 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0376479B1 (en) * 1988-11-28 1999-06-02 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device having a phospho silicate glass layer as an interlayer insulating layer
FR2731841A1 (fr) * 1995-03-07 1996-09-20 Nippon Denso Co Transistors a effet de champ du type a grille isolee et son procede de fabrication
US5753943A (en) * 1995-03-07 1998-05-19 Nippondenso Co., Ltd. Insulated gate type field effect transistor and method of manufacturing the same
US6146947A (en) * 1995-03-07 2000-11-14 Nippondenso Co., Ltd. Insulated gate type field effect transistor and method of manufacturing the same
US5925911A (en) * 1995-04-26 1999-07-20 Nippondenso Co., Ltd. Semiconductor device in which defects due to LOCOS or heat treatment are suppressed

Also Published As

Publication number Publication date
HK44892A (en) 1992-06-26
JPH0528899B2 (https=) 1993-04-27
EP0192668B1 (en) 1991-01-09
SG83591G (en) 1991-11-22
CA1226073A (en) 1987-08-25
US4589928A (en) 1986-05-20
KR880700461A (ko) 1988-03-15
JPS61503064A (ja) 1986-12-25
EP0192668A1 (en) 1986-09-03
KR930010983B1 (ko) 1993-11-18
DE3581285D1 (de) 1991-02-14

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