WO1985003398A1 - Dispositif de prise d'images a semi-conducteur - Google Patents

Dispositif de prise d'images a semi-conducteur Download PDF

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Publication number
WO1985003398A1
WO1985003398A1 PCT/JP1985/000038 JP8500038W WO8503398A1 WO 1985003398 A1 WO1985003398 A1 WO 1985003398A1 JP 8500038 W JP8500038 W JP 8500038W WO 8503398 A1 WO8503398 A1 WO 8503398A1
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WIPO (PCT)
Prior art keywords
transfer
clock
imaging device
solid
ccd
Prior art date
Application number
PCT/JP1985/000038
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English (en)
Japanese (ja)
Inventor
Shoichi Tanaka
Original Assignee
Shoichi Tanaka
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59015950A external-priority patent/JPS60160271A/ja
Priority claimed from JP59034839A external-priority patent/JPS60210079A/ja
Priority claimed from JP59049685A external-priority patent/JPS60192471A/ja
Priority claimed from JP59069835A external-priority patent/JPS61105180A/ja
Priority claimed from JP59091417A external-priority patent/JPS60235591A/ja
Priority claimed from JP59095314A external-priority patent/JPS60239181A/ja
Priority claimed from JP59189970A external-priority patent/JPS6167376A/ja
Priority claimed from JP59211797A external-priority patent/JPS6190576A/ja
Application filed by Shoichi Tanaka filed Critical Shoichi Tanaka
Publication of WO1985003398A1 publication Critical patent/WO1985003398A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H04N25/625—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of smear

Definitions

  • Solid-state imaging device Solid-state imaging device.
  • the present invention relates to solid-state imaging device technology, and more particularly to improvements in CCD solid-state imaging devices.
  • a CCD area sensor in which a vertical CCD also serves as a pixel array is called a frame transfer CCD area sensor (abbreviated as an F T sensor).
  • An FT sensor including a buffer CCD for storing signal charges representing a one-field image between a vertical CCD and a horizontal CCD is called a buffer FT sensor.
  • An FT sensor without a CCD is called a full-frame FT sensor.
  • a CCD area sensor having a vertical CCD arranged independently of a pixel column is called an interline transfer CCD area sensor (IT sensor).
  • An IT sensor in which a transfer electrode (AT G) arranged between a pixel and a vertical CCD is connected to a transfer electrode (abbreviated as VTG) of the vertical CCD is called a common transfer electrode IT sensor.
  • CCDs are driven by 1, 2, 3, and 4 phase clock voltages, but it has been proposed to use more multi-phase clock voltages.
  • Japanese Patent Laid-Open No. 56-35067 subtracts a previously recorded one-line smearing from a one-line signal output later. Disclose things.
  • a first object of the present invention is to improve the SZN ratio of a solid-state imaging device. It is also important to improve the resolution.
  • a second object of the present invention is to improve the resolution of a solid-state imaging device.
  • the present invention discloses four independent inventions regarding a CCD area sensor. Each independent invention is explained-because it has a deep interrelationship and a synergistic effect can be created by implementing it in the background.
  • Independent invention 1 discloses a technique for driving a vertical CCD of a CCD area sensor by a CCD transfer method named continuous injection EZB transfer (abbreviated as CIE / B transfer) by the present inventor.
  • CIE / B transfer continuous injection EZB transfer
  • the feature of the above CIE / B transfer is that a different clock voltage is applied to each clock transfer electrode of the vertical CCD, and the empty potential well injected from the output end of the vertical CCD arrives at the opposite end from the above output end. Then, the next empty potential well is injected from the above output terminal.
  • Independent invention 2 discloses that in a CCD area sensor, a difference between a signal of a pixel output from a pixel of a part of the saturated pixel line and a pixel of the saturated pixel line is detected in advance.
  • the smearing reduction method of the independent invention 2 may be very effective.
  • Independent invention 3 discloses that in a CCD area sensor, a horizontal CCD is horizontally transferred at a low speed during a vertical blanking period (a period during which signal charges are not horizontally transmitted) to output smear noise charges.
  • the smear noise reduction technology disclosed in Independent Invention 2 is very effective, but has the problem of significantly increasing costs.
  • Independent invention 3 solves this problem.
  • Independent invention 4 discloses that in a PT sensor, two adjacent transfer electrodes are connected above a channel region of a vertical CCD or a channel region between vertical CCDs.
  • each of the clock transfer electrodes substantially constitutes one pixel, it is highly preferable that the light transmittance of each clock transfer electrode is equal. Since a complicated clock voltage is applied from a drive circuit having multiple electrodes, it is preferable that the line resistance of each clock transfer electrode be small in order to increase the operation speed.
  • Independent invention 4 manufactures a clock transmission electrode having a uniform light transmittance and a small line resistance. The basic features of each independent invention and its dependent inventions are described below. The specific features and effects of each invention are described below.
  • a two-dimensional array of multiple pixels a vertical CCD that also serves as a pixel column, or is arranged independently of the pixel column, and a horizontal CCD.
  • the above vertical CCD transfers the signal charge of the pixel column to a horizontal CCD.
  • the vertical CCD includes one or both of a directional transfer electrode (abbreviated as DVTG) and a non-directional transfer electrode (abbreviated as ND VTG), and A part or all of the above DVTG or NDVTG is a transfer electrode to which a transfer voltage is applied (abbreviated as a close transfer electrode), and a clock transfer close to the output end of the vertical CCD.
  • DVTG directional transfer electrode
  • ND VTG non-directional transfer electrode
  • a part or all of the above DVTG or NDVTG is a transfer electrode to which a transfer voltage is applied (abbreviated as a close transfer electrode), and a clock transfer close to the output end of the vertical CCD.
  • the transfer voltage and voltage are applied in order from the electrode, and the empty potential well injected from the output end of the vertical CCD arrives at the opposite end from the output end of the vertical CCD. Is injected from the output end of the vertical CCD.
  • the first feature is that the charge of the potential door created under the clock DVTG and the charge of the intermediate DC potential stirrer placed between two adjacent clocks DVTG are transferred independently.
  • the solid-state imaging device according to claim 1. (7) Equipped with N 'DVTG (abbreviated as NDVTG) which is a clock transfer electrode, and the electric charge of the 3 ⁇ 4-position parallel to the odd (even) -numbered clock VTG is reduced to 3'. 2.
  • NDVTG which is a clock transfer electrode
  • each clock transfer electrode of the vertical CCD is connected to an output contact of a shift register or an output contact of a buffer circuit controlled by the shift register.
  • the odd (even) number clock transfer electrode (specifying clock NDVTG or clock D VTG) of the vertical CCD and its even (odd) number clock transmission electrode are 10.
  • an interline transfer CCD sensor (hereinafter referred to as common transfer) in which a transfer electrode (hereinafter abbreviated as ATG) that electrically connects the pixel and the vertical CCD is connected to the clock transfer electrode of the vertical CCD.
  • ATG transfer electrode
  • Imaging device. (14) wherein each clock DVTG of the vertical CCD is connected to a one-phase or two-phase clock power supply via a sequential switch, and the sequential switch is controlled by a shift register.
  • Each clock transfer electrode of the vertical CCD is sequentially driven by a clock power supply via a switch, and the above clock DVTG or the odd (even) th clock ND VTG is set before the vertical transfer period.
  • the solid-state imaging device according to claim 1 wherein the solid-state imaging device is charged to a deep potential VH, and a voltage is applied to each clock transfer electrode only through the above-mentioned sequential switch during the next vertical transfer period.
  • the above clock DVTG or the odd (even) th clock NDVTG is applied with the deep potential VH or the read potential VR by the above clock power supply.
  • interline transfer CCD sensor (abbreviated as ⁇ ⁇ sensor), which performs frame accumulation operation at low illuminance and performs field accumulation operation at high illuminance 2.
  • ⁇ ⁇ sensor interline transfer CCD sensor
  • a solid-state imaging device that transfers signal charges to a horizontal CCD, the smearing voltage of a pixel row (abbreviated as a saturated pixel row) including a pixel that generates a saturated signal charge (abbreviated as a saturated pixel row) is recorded.
  • a solid-state imaging device characterized in that the stored smearing voltage is subtracted from a signal voltage generated from at least a part of the pixels of the saturated pixel row.
  • a feature of the present invention is that the above-mentioned smearing voltage is not subtracted from the signal generated from a part or all of the pixels generated from the pixels downstream from the saturated pixels in the saturated pixel row.
  • Item 13 The solid-state imaging device according to Item 1.
  • the horizontal CCD horizontally transfers the scan charges at the first speed during the vertical retrace period, and transfers the second charge during the horizontal scan.
  • Horizontal transfer at the speed, and the first speed above is the second A solid-state imaging device characterized in that the speed is 1 to 2 or less.
  • the solid-state imaging device described in Section 30 is characterized in that the smears reproduced from the digital memory are DZA-converted by the DZA converter of the successive-ratio AZD converter.
  • the present invention relates to a CCD area sensor, in which a different clock voltage is applied to each vertical transfer electrode of the vertical CCD, and an empty potential well injected from the output terminal of the vertical CCD is connected to the other end of the vertical CCD. Before arrival, the next empty potential well is injected again from the above output terminal, and the electric charges of all the electric potentials of the vertical CCD are independently transferred.
  • the above transfer is abbreviated as continuous injection ⁇ transfer (CI ⁇ transfer).
  • CI ⁇ transfer continuous injection ⁇ transfer
  • Each charge of the vertical CCD is transferred to the potential bowl under all directional transfer electrodes (DVTG) or the odd (even) number of non-directional transfer electrodes before performing the above-mentioned CI ⁇ / ⁇ transfer. (NDV TG) accumulated in the potential well.
  • NDVT G is a transfer electrode that has a constant channel potential below it and can transfer charges in either direction
  • DVT G is a potential obstacle with a shallow potential VL to the channel below it.
  • This is a transfer electrode in which a wall region and a potential well region waiting for a deep potential VH are formed.
  • a four-phase CCD has four types of NDVTG
  • a two-phase CCD has two types of DVTG.
  • the shallow potential VL is a larger potential in the negative direction in an N-channel CCD
  • the deep potential VH is a larger potential in the positive direction.
  • the number of transfer electrodes per pixel can be halved compared to a conventional vertical CCD driven by a two-phase or four-phase clock voltage. And the charge transfer capability can be reduced to two. It is known that a different voltage is applied to each transfer electrode of a CCD, and the electric charge under each DVTG or under an odd (even) NDVTG is independently transferred. And Thompset, Modern Science, Inc., Charge Transfer Devices, pp. 36-37 and 228-229. However, in the above prior art, one empty potential well (potential well holding no charge) is reversely transferred from the output end of the vertical CCD to the opposite end, so that the entire charge is shifted by one potential well pitch. Only till each.
  • each clock transfer electrode receives a different clock voltage E.
  • An empty potential well is injected from the output end of the vertical CCD, and the next empty potential bowl is injected from the output end before the injected empty potential bowl arrives at the opposite end.
  • a one-phase, two-phase, or four-phase clock voltage is applied to each clog transfer electrode.
  • Empty potential well When arriving at the opposite end of the direct CCD or arriving at the black and slow transfer electrodes one bit downstream, empty potential wells between each signal charge well (potential well holding signal charge) Is arranged. Therefore, after the empty potential well arrives at the opposite end, the vertical CCD can be driven with the conventional one-phase, two-phase or four-phase clock voltage.
  • An important advantage of the present invention is that it can independently transfer the charge in all potential wells that a vertical CCD can make.
  • two empty potential wells are injected from the output of the vertical CCD during one horizontal retrace period.
  • signal charges of two adjacent pixel rows can be output independently in one horizontal scanning period.
  • injecting an empty potential well is equivalent to outputting the charge of one potential well of the vertical CCD from its output terminal.
  • two adjacent potential wells in a vertical CCD transfer charge for the same pixel. This effectively doubles the dynamic range of vertical CCD.
  • the vertical CCD is provided with a clock DVTG, and the charge in the potential well under each clock DVTG is transferred independently.
  • one D VTG is arranged per pixel.
  • the vertical CCD of the IT sensor comprises two DVTGs per pixel.
  • the signal charges of one pixel are transferred between two adjacent potential wells. Alternatively, transfer the signal charge in the odd (even) number potential well and transfer the noise charge (especially the smear noise charge) in the even (odd) number potential well. That is, 2. It is possible to read out the charges in the pixel row, or to double the charge transfer capability of the vertical CCD, or to transfer the signal charges and noise charges separately.
  • the odd (even) potential wells transfer signal charge, and the non-transferred charge in the even (odd) potential well adjacent upstream It is also possible to collect. As a result, transfer efficiency is improved.
  • an intermediate DC potential can be applied to an intermediate channel region between adjacent binary clocks D VTG.
  • This embodiment is particularly preferable for an FT sensor.
  • an ND VTG having an intermediate DC potential is arranged on the above-mentioned intermediate channel region. Since this ND VTG has a constant voltage, it can be made very thin and has high blue sensitivity.
  • the vertical CCD has a bulk channel, and the surface of the exposed intermediate channel region is implanted with a constant intermediate potential applied to the underlying bulk channel region. The exposed intermediate channel region has a high blue sensitivity.
  • the vertical CCD includes a clock D VTG and an intermediate DC potential well and an intermediate DC potential barrier created in an intermediate channel region between the clocks DVTG.
  • the intermediate DC potential bowl and the intermediate DC potential barrier can be provided by arranging the DVTG to which the intermediate DC potential is applied above the intermediate channel region between the clock DVTGs, or by exposing the intermediate bulk channel region. Created by performing two ion implantations on the surface. When this embodiment is applied to an FT sensor, the sound sensitivity is improved.
  • an odd-numbered stirrer door is created below the odd-numbered clock ND VTG, and a potential barrier is created below the even-numbered clock MD VTG.
  • two clock VTGs are arranged per pixel.
  • the interlaced operation can be performed by reversing the positions of the upper well and the potential barrier every field period, and the number of vertical pixels is equivalently doubled.
  • one ND VTG can be arranged per pixel.
  • an interlace operation can be performed by transferring signal charges of different pixel rows for each field period.
  • 2 NDVTG per pixel the signal charges of 2 pixel rows are read out in parallel, and other dependent inventions 3 explain.
  • the implemented charge transfer method can be implemented.
  • each clock electrode of the vertical CCD is connected to an output contact of a shift register for generating a vertical transfer clock voltage or an output contact of a current amplification buffer circuit controlled by the above-mentioned output contact.
  • the above buffer circuit is generally a source follower circuit or a common-source inverter circuit and has a small output resistance.
  • CIE / / B transfer C CD area sensor (hereinafter as (Kooite 2 EZB transfer sensor comprises a clock ND VTG.
  • each clock ND VTG's respective inverters constituting the two-phase shift register Connect it to the output contact or to the output contact of the buffer ⁇ circuit controlled by the output contact described above, which will generate the vertical cut-off voltage of the 2 E / B transfer sensor.
  • Each clock ND VTG may be connected to the output contact of the odd (even) number inverter of the register.
  • each clock D VTG is composed of two inverters constituting a two-phase shift register. Connected to the output contact of the odd (even) numbered inverter or to the output contact of the buffer circuit controlled by the above output contact. In this way, the vertical clock voltage of one EZB transfer sensor can be generated.
  • each clock DVTG is directly or directly connected to the output contact of one of the four types of inverters that constitute the four-phase shift register. It can be connected via a buffer circuit.
  • the clock DVTG may be connected directly to the output contact of one of the three types of inverters constituting the three-phase shift register or via a buffer circuit. That is, the wording of claim 11 means that each clock DVTG is connected to one output contact per transfer stage of the shift register. Of course, each clock DVTG means the clock DVTG of each row. In claim 10, the clock ND VTG is connected to one output contact per 1/2 transfer stage of the shift register. In claim 9, a two-phase shift register is particularly preferred because it is simple in structure and operation and can increase the pixel density in the vertical direction.
  • the inverter (shifted output inverter) of the shift register connected to the clock DVTG or the buffer inverter constituting the buffer circuit performs a ratioless operation. Since the ratio inverter has a charge period for charging the above output contacts all at once before the evaluation period for logically discharging its output contacts, the clock DVTG above the empty potential well of the vertical CCD is Before the charge is transferred to the empty potential well, the above-mentioned empty potential well is changed from the shallow potential VL to the deep potential VH. As a result, 1 EZB transfer operation is very stable.
  • the odd (even) clock transfer electrode and the even (odd) clock transfer electrode can be connected directly by different shift registers or by a buffer circuit. Is driven through.
  • the clock transmitting electrode is connected to one output contact per transfer stage of the & shift register. In this way, the vertical clock voltage required for 1EB transfer or 2EZB transfer can be generated.
  • shift registers having a small number of transfer stages can be arranged on both sides of the imaging area, the vertical dimension of one transfer stage of the shift register can be doubled. Then, the clock power frequency of each shift register can be reduced.
  • each clock DVTG is connected to a one-phase or two-phase clock power supply via a switch in sequence.
  • the above-mentioned sequential switch is a switch that operates sequentially from the downstream side.
  • This EZB transfer sensor is called a clock line driven 1 E / B transfer sensor-and the EZB transfer sensor in claim 9 is called a shift register driven EB transfer sensor.
  • two adjacent clocks of the vertical CCD, DVTG are each connected to the first, second, and second phase clock power supplies via sequential switches, and The switches operate simultaneously. In this way, the number of transfer stages of the shift register for sequentially driving the switches can be reduced to half of the vertical CCD DVTGG. In addition, the operation of the switch can be performed easily.
  • a predetermined potential is applied to each clock transfer electrode before performing vertical transfer. You. Then, each clock transfer electrode is cut off from the power supply line, and thereafter connected to the clock power supply via the switch in order. This makes it very easy to control the potential of the clock transfer electrode (clock DVTG or clock NDVTG).
  • the vertical CCI] clock DVTG is sequentially connected to the clock power supply line via a switch.
  • a CIEB transfer sensor is called a clock line drive 1 ⁇ /// transfer sensor. In this 1 ⁇ . / ⁇ transfer sensor, all clock DVTGs have a deep potential V ⁇ before performing vertical transfer.
  • the CI EZB feed sensor connected to the clock power line is called the clock line driven 2 EZB transfer sensor.
  • the odd (even) clock NDVT G becomes the deep potential VH
  • the even (odd) clock ND VTG becomes the shallow potential.
  • VL the voltage waveform of the vertical transfer port of the clock line drive 2 EZB transfer sensor and the J voltage voltage become complicated.
  • the clock-line driven E / B transfer sensor has the ability to increase the output resistance of the shift register compared to the shift register-driven E / B transfer sensor disclosed in claim 9, but instead uses a channel resistance, which is a transmission switch and has a smaller sequential switch.
  • the initial potential setting of the clock transfer electrodes performed before the above vertical transfer is performed by connecting each of the block transfer electrodes to the reset power supply line via a dedicated reset switch.
  • the readout voltage VR can be applied to the fixed clock transfer electrode by the circuit means for resetting and / or resetting the clock transfer electrode.
  • the initial potential setting of the clock transfer electrode is performed before performing the above vertical transfer, and the vertical transfer is sequentially connected to each clock transfer electrode via a switch. This is performed by the clock power supply line.
  • all necessary sequential switches are all turned on by the shift register.
  • the potential setting technology of the present invention is also applied to the transfer of signal charges from pixels to vertical CCDs by applying a read voltage VR to the required black transfer electrode in the common tiller electrode IT sensor. it can. That is, the necessary sequential switches may be turned on, and the read voltage VR may be applied to a predetermined clock line. According to the present invention, since each clock transfer electrode need only be connected to the clock line via a sequential switch controlled by the shift register, the circuit structure and the vertical transfer clock operation are simplified.
  • a vertical CCD A shift register that applies a clock voltage to the clock transfer electrode directly or through a buffer circuit, or a shift register that turns on the above-mentioned sequential switches in order is disposed on both sides of the imaging unit.
  • the odd (even) clock transfer electrodes are connected directly or indirectly to a shift register located on the left or via a sequential switch controlled by the shift register described above. Connected to the clock line.
  • the right shift register controls the even (odd) number clock transfer electrodes. This makes the shift register design easier.
  • one vertical scan line driving one row of clock transfer electrodes of each vertical CCD is driven from both sides.
  • the above one vertical scanning line may be divided. In this way, the size of the switch or shift register or the buffer circuit can be reduced.
  • signal charge is output from all pixels during one field period, and signal charge output from odd (even) numbered pixels. Can be displayed. In this way, afterimages in the field can be reduced, and the dynamic range can be improved. Of course, it is also possible to take into account all the signal charges output at low illuminance.
  • the frame accumulation operation may be performed at low illuminance and the field accumulation operation may be performed at high illuminance.
  • this switching of the storage operation involves applying a read voltage V R to half or all of the clock transfer electrodes before starting the vertical transfer operation.
  • the vertical CCD has one potential well per pixel, and alternately stores signal charges and noise charges of odd (even) pixel rows in the above potential wells. And independently transfer the signal charge and the noise charge. Can do things. S / N ratio of the thus them if signal charges can be improved the S / N ratio particularly dark current and Sumeanoi _'s.
  • the noise charge remaining in the vertical CCD is cleared or relocated.
  • the smear noise charges of the adjacent signal charge well and the noise charge well become substantially equal, so that the smear noise can be removed by subtracting the voltages output from the two potential wells.
  • the above clearing can be performed by high-speed tilling of the vertical CCD during the vertical retrace or by transferring the residual noise charge to the drain adjacent to the vertical CCD. That is, in the CIE / B transfer sensor of the present invention, the potential well is substantially halved at the end of the vertical transfer, and as a result, the residual noise charge is transferred to the odd (even) number potential well at the next vertical transfer. Only exists. Thus, by removing or relocating this residual noise charge, and subtracting the output signals of two adjacent potential wells, the smear noise and residual noise charge can be removed.
  • the smear noise charge mixed into the signal charge is substantially constant .. Therefore, one pixel row (or saturated pixel) is provided during the vertical retrace period. The smear noise is significantly reduced by recording the smear noise charge of (1 'pixel row in the column) and subtracting the smear noise charge from the above-mentioned charge.
  • a vertical CCD of a CIEB vehicle transport sensor in which a vertical CC has one potential well per pixel and outputs signal charges of all pixels in one vertical transfer period, an odd (even) number CCD holding residual noise charge is provided. Potential wells and even-numbered potential wells that do not retain residual noise charge have significantly different smears charges. Therefore clay There was a drawback in that a vertical CCD per element had to have two potential wells, as shown in FIG. Also, in the conventional technology in which the smearing of one pixel row is stored and subtracted from the signal of each pixel row output later, if the smearing is large, the pixel receives strong light and generates a saturated signal charge and is output from a pixel (saturated pixel).
  • the present invention aims to remedy the above problems.
  • the present invention stores at least one pixel row of a saturated pixel column, and reads the above signal from signals generated from some pixels of the saturated pixel column. It is characterized in that the subtracted smears are subtracted, and the above-mentioned recorded smears are not subtracted from signals generated from other pixels of the saturated pixel sequence. This makes it possible to create a CIEZB transfer sensor that can output signal charges from all pixels in one field period. And it is possible to make a CCD area sensor whose maximum signal voltage does not decrease.
  • the smeared charges are mixed into the above potential well mainly when the potential well passes below or under a saturated pixel receiving strong light. Therefore, the recorded smear noise is subtracted from the signal generated from the potential bowl passing under or beside the saturated pixel, and the above-mentioned smear noise is subtracted from the signal generated from the other potential well of the saturated pixel column. Special features are not available.
  • the above stored memory noise is not subtracted from the signal generated from the saturated pixel. As a result, the maximum signal voltage does not decrease.
  • the above-described smear noise is not subtracted from the symbol “ ⁇ ” which is generated from some or all of the pixels downstream of the pixel in the pixel row.
  • a vertical CCD has one potential bowl per pixel, and each potential well transfers the signal charge of the pixel if it is different.
  • CI ⁇ ⁇ ⁇ Transfer sensor (CI ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ) ) Subtracts the stored smear noise from the signal charges of the odd (even) number pixels among the pixels downstream of the saturated pixel (abbreviated as “downstream pixels”).
  • the above-mentioned stored noise is not subtracted from signals generated from pixels in a pixel row having no saturated pixel (non-saturated pixel row). In this way, random noise can be reduced. However, since the unsaturated pixel row adjacent to the saturated pixel row may have smear noise, the above-described subtraction may be performed.
  • Independent Invention 3 Claim 2 9. 'The independent noise reduction technology of Independent Invention 2 effectively reduces the noise of the EZB transfer sensor of Independent Invention 1.
  • the problem of independent invention 2 is that it requires an expensive A / D converter and DZA converter that operate in the video band. As a result, the price of the solid-state imaging device increases and becomes very disadvantageous in terms of competition.
  • the present invention is characterized in that the horizontal CCD is driven at a low speed during the vertical flyback period, and the smear noise charges transferred from the vertical CCD are output at a low speed. In this way, the cost can be significantly reduced because a low-arrest AZD converter can be used.
  • an N-bit sequential ratio AZD converter is used.
  • the AZD converter is very inexpensive compared to the video band parallel AZD converter.
  • the smears of one horizontal pixel row are AZD-converted during a period equal to about 7 horizontal scanning periods in the vertical blanking period. You.
  • the smear noise reproduced from the digital memory is D / A-converted by the DZ converter in the successive approximation AZD converter during the vertical scanning period. In this way, the DZA converter can be omitted.
  • the EZB transfer sensor disclosed in the independent invention 1 can have substantially twice the vertical pixel density as the conventional one.
  • a new problem arises when the above E / B transfer is applied to a leading type of frame transfer sensor (FT sensor). That is, a vertical CCD generally includes a bulk channel and an overlapping transfer electrode arranged above the bulk channel.
  • FT sensor leading type of frame transfer sensor
  • a vertical CCD generally includes a bulk channel and an overlapping transfer electrode arranged above the bulk channel.
  • each transfer electrode substantially constitutes one pixel.
  • the light transmittance of all transfer electrodes that generate the same color signal must be equal.
  • each of the close transfer electrodes is connected to a shift register, a buffer circuit controlled by the above shift register, or a cross switch via a sequential switch.
  • the confection vertical transfer rate depends on the charge / discharge rate of each vertical scan line, and the above charge / discharge rate is the sum of the resistance of the shift register or buffer circuit / sequential switch and the resistance of the vertical scan line, and the vertical Depends on the product of scanning line capacitance. As a result, it is very important to reduce the line resistance of the vertical scanning lines.
  • vertical CCD transfer electrodes with low line resistance generally have poor light transmittance (particularly poor blue sensitivity).
  • An object of the present invention is to improve the above question.
  • the present invention connects two adjacent transfer electrodes of a vertical CCD above the channel region of the vertical CCD or above the channel stop region between the vertical CCDs, thereby forming substantially one transfer electrode. It is characterized in that a thick film is given to the first transfer electrode of the upper self and a thin film is given to the second transfer electrode.
  • a thick film is given to the first transfer electrode of the upper self and a thin film is given to the second transfer electrode.
  • the second transfer electrode has a high line resistance.
  • the equivalent line resistance of the second transfer electrode can be reduced.
  • the above-mentioned equivalent transfer electrodes formed by two transfer electrodes have the same equivalent ratio.
  • the thickness of the second transfer electrode can be made as thin as possible. .
  • the first and second transfer electrodes are connected via a third electrode (eg, aluminum) or directly above the channel stop region.
  • a third electrode eg, aluminum
  • the low resistance first transfer electrode has a greater vertical width at the side of the channel stop region than above the channel region. In this way, the connection area is increased and the line resistance is reduced.
  • a directional transfer electrode DVT G
  • a predetermined ion can be implanted into the channel region using the first or second transfer electrode as a mask.
  • FIGS. 4, 5, and 6 disclose that a shift register (SR) driven 1 E / B transfer sensor can use a dynamic shift register (DSR). This fact is important. That is.
  • DSR dynamic shift register
  • the inventor reserves a claim regarding the EZB transfer sensor structure using DSR.
  • the EZB transfer type CCD area sensor of the present invention is suitable for a single color TV camera or a magnetic camera which independently outputs two adjacent pixels in one horizontal period. is there. This fact is important. Because the conventional single-chip CCD color TV camera has a small number of horizontal pixels, the brightness or color signal resolution was poor. Conventional C C
  • the resolution for a moving subject was poor because one frame image was composed by shooting for two field periods.
  • the present invention since two adjacent pixel rows can be output independently during one horizontal scanning period, this problem is solved.
  • methods such as increasing the number of horizontal transfer stages of the vertical CCD to two or doubling the number of vertical CCDs have been implemented. ⁇
  • two adjacent pixel rows these methods leads to bad results in the structure and fabricating process and S New ratio
  • the inventor reserves a complaint regarding the EZB transfer CCD area sensor that performs the ZH output operation.
  • the conventional EZ B transfer is an N-phase clock transfer method in which each clock voltage is substantially symmetrical. Since the addition of N is inversely proportional to the transfer speed, signals of one pixel row or more in one horizontal blanking period It could not be used for vertical CCD of CCD area sensor which needs to output electric charge.
  • the CI EZB transfer method of the present invention is the same as the conventional EZB transfer method in using a very large number of clock phases, but the above-described clock and signal are output until the signal charge of the first half pixel row of the CCD is output.
  • the voltage is an asymmetrical clock voltage, and subsequently, a one-, two-, or four-phase clock voltage is used.
  • the CCD signal charges that are input all at once before transfer are output in order. Therefore, the CI EZB transfer method of the present invention can also be applied to an SPS type CCD structure output CCD or CCD line sensor.
  • a vertical CCD having the same number of VTGs can secure twice the number of vertical pixels as compared with the conventional case.
  • 0 directivity 0
  • PB potential barrier
  • PW potential well
  • NDVTG non-directional VTG
  • the CI EZB transfer method of the present invention using DVTG is called 1 EZB transfer, and that using NDVT G is called 2 ENO B transfer.
  • the shallow potential VL is a potential that does not accumulate signal charges
  • the deep potential VH is a potential that accumulates signal charges. That is, in an N-channel CCD, the shallow potential VL is a more negative clock voltage, and the deep potential VH is a more positive clock voltage.
  • the present invention relates to an IT sensor It can be used for the vertical CCD of an interline transfer area sensor or a full frame transfer type FT sensor (frame transfer area sensor), but a normal FT sensor with a buffer CCD (accumulated CCD) between the vertical CCD and the horizontal G CD It can be applied to vertical CCDs.
  • Independent invention 2 (claim 25) is extremely effective in suppressing the unique smear noise pattern of independent invention 1 (claim 1) .By using both together, an area sensor having a large dynamic range and a small smear noise is manufactured. it can.
  • Independent invention 3 (claim 29) is a drawback of independent invention 2 because it suppresses the complexity of the circuit and increases the cost, so that by implementing independent inventions 1, 2, and 3 together, A high area sensor can be manufactured.
  • Independent Invention 1 1 When manufacturing an EZB transfer type FT sensor using the conventional two-layer electrode technology, the pixel sensitivity of odd (even) rows is different from the pixel sensitivity of even rows, resulting in large pattern noise.
  • Independent Investigation 1 (Claim 3 2), the above-mentioned disadvantages can be improved and a FT sensor with good performance can be manufactured.
  • FIG. 1 and FIG. 2 are block circuit diagrams of an embodiment of the continuous injection E / B transfer sensor disclosed in the independent invention 1.
  • vertical scanning lines 3 arranged in the imaging area 1 in the horizontal direction are driven by shift registers (abbreviated to VSRs) 2 A and 2 B that generate a vertical transfer cut-off voltage.
  • VSRs shift registers
  • the question of the shift register and a vertical scanning line, so that you can place Batsufuainba one motor current amplification is of course, less Te smell, c vertical for explaining an embodiment of driving directly the vertical scanning lines 3 by shift.
  • Torejisuta Since Run 3 is generally integrated with the vertical G CD transfer electrode, The same sign.
  • FIG. 1 and FIG. 2 are block circuit diagrams of an embodiment of the continuous injection E / B transfer sensor disclosed in the independent invention 1.
  • VSRs shift registers
  • each vertical scanning line 3 is driven by shift registers 2A and 2B, so that its charging and discharging become faster.
  • 2A and 2B operate the same. 3 may be divided in half.
  • the horizontal CCD 5A is connected to the vertical CCD or buffer CCD by the transfer electrode 4A.
  • the horizontal CCD 5B is connected to the horizontal CCD 5A by the transfer electrode 4B.
  • the odd (even) th vertical scanning line 3A is connected to the output contact of the shift register 2A, respectively, and the even (odd) vertical scanning line 3B is connected to the output contact of the shift register 2B. Connected to each other.
  • the pixel, the buffer CCD, and the vertical CCD are omitted. In FIG.
  • FIG. 3B 3Z has a deep potential VH and 3Y has a shallow potential VL. And Q 2 is tilled below 3 Z.
  • Figure 3C 37, and 3 become shallow potential, 3Y and 4A become deep potential VH, Q2 is transferred to horizontal CCD 5A, and Q3 is transferred below 3Y.
  • FIG. 3 F operation from Figure 3 D is is the vertical transfer independently. Vertical scan line 3 (A to Z) is connected to each output contact of shift register 2A.
  • the above vertical transfer can be performed by alternately injecting the transfer pulse information, the shallow potential VL and the deep potential VH, from the input terminal 2C of the shift register 2A. It is understood.
  • Fig. 3 (A to F) it is understood that the next empty PW is injected every time the empty potential well (PW) represented by 0 is reversely transferred by 2 PW pitches.
  • FIG. 4 (A to F) illustrates one EZB transfer operation having the structure of FIG. Figure 4 (A to F) has the same operational state as Figure 3 (A to F). However, in Fig. 4 (A to F), shift registers 2A and 2B alternately have a deep potential VI-I.
  • the above operation of 2A and 2B can be easily made by making the output inverter of the shift register a dynamic type, especially a ratioless type.
  • the charging operation of one shift register preferably begins earlier than the evaluation (discharge) operation of the other shift register.
  • the clock operation shown in FIG. 3 (A to F) and FIG. 4 (A to F) is also possible in the embodiment using the dynamic type, especially the ratio type buffer inverter.
  • the charging operation of the inverter is a quick operation that applies a deep potential VH to its output contact
  • the discharging operation is a clock operation that applies a shallow potential VL to its output contact. It can be seen that the 1 E / Bg transmission of the present invention can be implemented by a very simple mouth and speed operation.
  • FIG. 5 is an equivalent circuit diagram of one embodiment of the shift register of FIG.
  • the shift register in Fig. 3 can also have basically the same structure as in Fig. 5.
  • the vertical scanning lines 3Z, 3Y and 3X are the output of the shift register 2 2.2 ⁇ and the output of the inverter 11 1.
  • 1 1 A is the charging switch This is a dynamic inverter with 8 A switch, 9 A evaluation switch and 1, 0 A discharge switch.
  • connection inverter 11B for connecting the binary output inverter has a discharge switch 10B, an evaluation switch 9B, and a charge switch 8B. 11A and 11B are alternately connected by connection switches 7A and 7B.
  • FIG. 6 is an operation diagram of one embodiment of the two-phase shift registers 2A and 2B of FIG.
  • 14 is an operation diagram of 2 A
  • 14 ′ is an operation diagram of 2 B.
  • the clock voltages V ⁇ and V 2 ′ are applied to 2 B, and the clock voltages V 1 and V 2 are applied to 2 A.
  • 14 P indicates the charge state of the output contact 12 1
  • H indicates the hold state
  • E indicates the evaluation (discharge) state.
  • P 'of 14' indicates the state of charge of the output contact 12 'of 2B
  • H' indicates the holding state
  • E ' indicates the evaluation state.
  • the operation of the MOS two-phase shift register is well known and will not be described in detail.
  • E operates later than P '
  • E' operates later than P.
  • FIG. 6 by arranging P. ⁇ , ⁇ during one horizontal retrace period, signal charges of one pixel row can be transferred to the horizontal CCD.
  • FIG. 5 by blocking 1 OA and conducting 8 A, a deep potential VH can be applied to each DVTG.
  • FIG. 7 shows an embodiment in which the vertical scanning line 3Z is connected to the output contact of the buffer inverter 15 driven by the shift register 2A.
  • the transfer lock shown in FIG. 3 (A to F) and FIG. 4 (A to F) is generated by the dynamic disconnector 15. For example, in FIG. 6, the charge switch 15 A conducts and the discharge switch 15 C shuts off during the P period. During the H period, 15 A and 15 C cut off.
  • FIG. 8 shows a modification of FIG. 7.
  • the connection switch 16 operates in the same manner as the discharge switch i 5 C of FIG.
  • FIG. 9 is an operation diagram for explaining the frame 10, and is an operation diagram of the shift register 2A of the 2E./Bfe transmission sensor having the structure of FIG. Shift register 2A is configured by alternately connecting output inverters 11 1 and output inverters 11B. And vertical running Line 3 (from Z to W) is connected to the output contacts 12 A and 12 B of each output inverter.
  • the output contacts of the two-phase shift register 2A change as shown in Fig.
  • FIG. 10 (A to H) is an operation diagram showing a 2EZB transfer sensor having the structure of FIG.
  • shift registers 2A and 2B drives ND VTG 3 (Z, X, V), and 2B drives ND VTG 3 (Y, W, U).
  • the signal charges Q 1, Q 2, and Q 3 can be transferred independently by alternately applying a pulse operation to 2 A and 2 B.
  • shift registers 11A and 11B can be constituted by two-phase static shift registers. Of course, the use of four shift registers is also possible.
  • inverters 11 and 11B alternately perform evaluation (discharge) operation E and hold operation H. Therefore, shift register 2A has a two-phase dynamics (especially ratio) format. You can do it.
  • Figure 10 illustrates two-phase dynamics (especially ratio) format. You can do it.
  • Shift register 2A that drives the odd (even) ND VTG of A (H) and shift register 2B that drives the even (odd) ND VTG Since the holding operation H and the evaluation operation E are performed alternately, a dynamic (particularly ratio) shift register can be used.
  • 2 B are shift register comprises a mosquito inverter output ratioless form, c can be configured, however, the vertical scanning line potential change of the output contacts of the charging operation period P To prevent transmission, the switch connecting the shift register and the vertical scan line during the charging period P is shut off.
  • Figure 11A (A to C) is an operation diagram showing the residual charge QNR of the 1 E / B transfer IT sensor.
  • each potential well 3 ( ⁇ 'to S ') Is in the state of Fig. 11A. That is, the residual charges QN'R (1 to 4) are accumulated in PW3Z ', 3X'.3V', and 3T ', respectively.
  • QNR 4 are vertically transferred by 1 PW pitch. This vertical tilling is performed by applying a deep potential VH to PW3Y ', 3W', 3U ', 3S, and a shallow potential VL to PW3X', 3T '. . In this clock operation, for example, in FIG.
  • FIG. 11C shows the above state.
  • Fig. I1 (D to F) is an operation diagram illustrating the use of the above-described smear noise subtraction technique for the 2EZB transfer sensor.
  • Figure 11D shows the arrangement of the first residual charge during the vertical retrace period.
  • FIG. 11E shows a state in which the odd (even) -numbered residual charges are transferred by the i potential well (PW) pitch.
  • FIG. 11F shows a state in which signal charges 1., Q 2, and Q 3 are transferred from the pixel to the potential wells 3 Z ′ .3 V ′ and 3 R ′ of the vertical CCD 6.
  • the basic operation is the same as the above 1 EZB transfer IT sensor.
  • the residual charge is drained from the vertical CCD 6 during the vertical retrace period, and the charge of the two adjacent potential wells is subtracted. May be.
  • FIG. 12 is a cross-sectional view of one embodiment showing the intermediate potential 1 transfer sensor disclosed in claim 5.
  • New tau form the substrate (4 X 1 0 4] ⁇ atom / CC) 2 0 P-type Ueru region (2 X on the 1 0 [15] atom CC 32 is created.
  • ⁇ indicates the exponential term.
  • an N-type bulk channel region (1 X 10 [16] atom ZCC) 22 is created. Boron ions are implanted into a part of the surface of the region 22 to form a potential barrier region 3.
  • a DVT G 37 A.37 B is formed on the surface of the region 22 via the insulating film 36.
  • the N T DVTG 3 5 with a DC voltage on the ⁇ to two D VT G 3 7 A, 3 7 intermediate Chiyan'ne Le regions 2 2 A during B is made.
  • FIG. 13 is a channel potential diagram of FIG. An intermediate potential VM is applied to the intermediate channel region 22A.
  • the unclocked ND VTG 35 can be very thin, thus improving the blue sensitivity of the 1E ZB transfer FT sensor.
  • the potential barrier region is formed by implanting polon ions on the surface of the intermediate channel region 22 A, the above-mentioned ND VTG 35 can be omitted. Its sensitivity is further improved. Ion implantation into the surface of the intermediate channel region 22 A and ion implantation into the potential barrier region below the DVTG can be performed by the same process.
  • the shift register driving EZB transfer sensor of the present invention can be used for vertical transfer between the FT sensor and IT sensor, and the above vertical transfer implements a non-interlaced output method or a two-pixel line reading interlace output method. It is understood that is possible. In addition, it is possible to switch between interlaced non-interlaced systems, and to switch between frame storage mode and Z-field storage mode.
  • One-pixel row reading and interlacing in which one or both of the ftCCDs are used to transfer signal charges in one pixel row, are also possible. It is also possible to perform 2-pixel line reading and interlacing when the smearing is small, and use the low noise technology of claims 2-3 and 24 when the smearing is large.
  • FIG. 14 is an equivalent circuit of the first embodiment to explain the clock line drive 1 EZ B transfer sensor
  • FIG. 15 is a clock line 2 ⁇ ′
  • FIG. 7 is a waveform diagram of two-phase clock voltages V 1 and V 2 applied to the channel 2.
  • Fig. 14, Fig. 1
  • Reference numeral 5 denotes a drive circuit for a black line drive 1 ⁇ / ⁇ transfer sensor.
  • the vertical scanning line 3 ( ⁇ to V) connected to the vertical CCD DVTG is connected to the clock lines 2 ⁇ and 2 ⁇ by the switches 16 (V to ⁇ ) sequentially.
  • the switches By inputting the transfer pulse information to the input terminal 2X of the shift register 2, the switches are sequentially turned on in order from 16Z, 16Y.
  • the T1 period is a non-transfer period, and signal charges are accumulated in each potential well of the vertical CCD.
  • V1 has a shallow potential V
  • V2 has a deep potential VH.
  • 16- ⁇ , ⁇ 6 ⁇ conducts, and is transferred to horizontal CCD 5 A via Q 1. Transit 4 ⁇ .
  • V2 becomes a deep potential VH.
  • V1 becomes the deep potential VH
  • V2 becomes the shallow potential V.
  • Q2 is transferred from below DVTGG3Y to below DVTG3Z.
  • V 1 and V 2 become the deep potential VH.
  • V1 becomes the shallow potential VL
  • V2 becomes the deep potential VH.
  • 16W.16X conducts.
  • Q 3 is transferred from below DVT G 3 X to below DVT G 3 Y.
  • V2 becomes a deep potential VH.
  • V1 is deep potential VH
  • V2 is shallow potential during t7 period Becomes VL.
  • V1 becomes the deep potential VH
  • V2 becomes the shallow potential VL
  • Q3,04 ⁇ 1 DVT G pitch one potential well pitch
  • V2 becomes a deep potential VH. Then, 16 U and 16 V conduct. As a result, Q4, Q5 and Q6 are transferred by one DVTG pitch. In this way, continuous injection type 1 EZB tilling can be performed very easily.
  • the ability to simultaneously apply (change) the clock pulse voltage V1 and sequentially turn on the switches during the periods L1, t5, and t9 greatly simplifies the transfer operation. Furthermore, the ability to conduct two adjacent switches at the same time greatly simplifies the transfer operation and reduces the size of the shift register.
  • T 1 is a vertical retrace interval
  • t 1 to t 4 are arranged within one horizontal retrace interval.
  • FIG. 17 is a cross-sectional view of one embodiment illustrating the intermediate potential type IEZB transfer sensor disclosed in claim 6.
  • FIG. 17 is basically the same as FIG. However, a potential barrier region 34 is added below the DC electrode 35 by ion implantation, so that an intermediate potential barrier region 22C and an intermediate potential well region 22B are formed in the intermediate channel region.
  • This CCD structure is known as a one-phase CCD.
  • FIG. 18 is a potential diagram of FIG.
  • FIG. 19 is a modified embodiment of FIG.
  • FIG. 20 is the potential diagram of FIG. Fig. 21 shows the driving circuit of a 1 / E / B transfer sensor with a CCD having the CCD structure shown in Figs. 17 and 19.
  • FIG. 22 is connected to the clock line 2Y of FIG. Fig. 22 shows the clock of Fig. 21.
  • FIG. 6 is a waveform diagram of a clock voltage V1 applied to a clock line 2Y. This is basically the same as FIG. In the non-transfer period ⁇ 1, the intermediate potential VM is applied to all the D VTGs, and the potential well P WV below the DVTG and the potential well PWM in the intermediate channel region have the intermediate potential VM ′. Then, charges are accumulated or transferred to all potential wells of the vertical CCD.
  • FIG. 23 shows the operation of the vertical D6 of the clock line drive type 1 EB transfer sensor of FIGS. 21 and 22.
  • DC transfer electrodes 3Y.3W, 3U are arranged between DVT G3Z, 3X, 3V, 3T, and electric charges Q1 to Q7 are stored under them. Since all sequential switches conduct during T1, the intermediate potential VM can be applied to D VTG by 2Y as in Figs. 14, 15, and 16. In the IT sensor, a deep potential VH or a read potential VR may be applied. Then, at the end of the T 1 period, all sequential switches are turned off, and each DVTG with VM has a floating potential.
  • Figure 23A illustrates this situation.
  • FIG. 23B shows the state during the period t1, V1 becomes the shallow potential VL, I6Z conducts, and Q1 is fed to the horizontal CCD 5A via 4A.
  • Figure 23C shows the state during t2, V1 goes to deep potential VH, and Q2 is transferred from below 3Y to below 3Z.
  • Figure 23D shows the state during the t3 period, V1 becomes the shallow potential VL, and Q2 is transferred to 5A.
  • Figure 23E shows the state during the t4 period, V1 becomes the shallow potential VL, and 16X becomes conductive. As a result, Q 3 is transferred from below 3 X to below 3 Y.
  • FIG. 23F shows the state during period t5, where V 1 is at the deep potential VH, and Q 3 and Q 4 are transferred by one potential well pitch.
  • FIG. 23G to FIG. 23L show the state from the period t6 to the period tl1.
  • the vertical CCD outputs one row of signal charges during the periods t2, t3 ', and t4, and outputs the next one row of signal charges during the periods t5, t6, and t7.
  • This transfer method has the feature of being very simple. It is a great advantage that the charge of one potential well can be transferred by one potential well pitch by sequentially turning on the switch one value during 1: 4, t7 and t10 periods. Then, the structures of Fig. 17 and Fig. 19 improve the blue sensitivity of the FT sensor.
  • the intermediate DC transfer electrode 35 can be made very thin.
  • solid-state imaging device 1 A Is assumed to be an IT sensor that outputs one pixel row during one horizontal scan period by the conventional two-phase clock transfer method.
  • the IT sensor 1A has an imaging area 1 and a horizontal CCD 5. The description of the pixel column and the vertical CCD is omitted.
  • the signal charge QS output from the horizontal CCD 5 during the vertical scanning period is converted into a signal voltage VS by the amplifier 92, and the VS is input to the comparator 93 and the subtraction circuit 100.
  • the smearing charge QNS output from the horizontal CCD 5 during the vertical retrace period is converted to a smearing voltage VNS at 92, and the VNS is stored in the digital memory 97 via the AZD converter 96. At least a smear noise voltage for one pixel row for a saturated pixel column is stored, but a smear noise voltage for one pixel row or more for all pixel columns may be stored.
  • the digital memory 97 sends the scan voltage VNS to the switch circuit 99 via the DZA converter 98.
  • the switch circuit 990 transmits the smearing voltage VNS output from the D / A converter 98 to the arithmetic circuit 100 under specific conditions.
  • the smear noise voltage is not subtracted from the signal voltage generated from 91 A.
  • the signal voltage of 91 A does not decrease.
  • the smear noise voltage is not subtracted from the signal voltage generated from the unsaturated pixel column 91F. As a result, the random noise of the signal voltage of 91 F is reduced.
  • the smear noise voltage is not calculated from the signal charge generated from the downstream region 91C.
  • the result No charge The signal charge of 9 1 C has no negative smear.
  • the specific operation will be described below.
  • the signal voltage VS output from the comparator 92 is compared with the saturation signal voltage VS max by the comparator 93. 93 outputs 0 when VSVS max. 93 sends a logical signal VC to AND circuits 95A and 95E and an inverter 95B.
  • 95 A sends the AND signal of the output signal VM of the line memory 94 and the output signal VC of 93 to the line memory 94.
  • the line memory 94 is driven in synchronization with the horizontal CCD 5.
  • the line memory 94 outputs 0 for the signal voltages in the areas 91 A and 9.1 B.
  • Inverter 95B outputs 1 only for the signal voltage in area 91A. Therefore, the NOR circuit 95C receiving logic signals from 94 and 95B outputs 0 to the OR circuit 95D only for the signal voltage in the region 91B.
  • the switch circuit 99 controlled by 95D sends the screen noise reproduced from 7 to the arithmetic circuit 100 only for the signal voltage of the upstream area 91B. That is, the smear noise voltage is subtracted only from the signal voltage in the region 91B.
  • each of the memory cells in line memory 94 is reset to one. The circuit shown in Fig.
  • the solid-state imaging device 1A is an EZB tiller-type IT sensor and the residual charge of the vertical CCD is cleared during the vertical retrace period.
  • the downstream region 9 The odd (even) -th potential well P of 1 C has a residual charge, and the even (odd:)-th potential well has no residual charge. Therefore, the lock VX input to the AND circuit 95 may be set to 1 when the signal charge of the odd (even) th potential well is output.
  • the switch circuit 99 becomes conductive, and the subtraction circuit i 00 substantially performs the subtraction, and the smear noise of 91 C is canceled. Since the signal VC is input to the AND circuit 95E, the switch circuit 99 is cut off when the signal voltage of the area 91A is output. In the above-described embodiment in which two pixel rows are independently output during one horizontal scanning period, a 2 f horizontal CCD is generally used. Therefore, the symbol voltage of the two horizontal CCDs output from the area 91 C is used. Of which, horizontal C including residual charge It is also possible to design the switch circuit 99 and the AND circuit 95E so that the scan voltage is subtracted from the CD signal voltage. In order to compensate for the delay of the control signal by the logic circuit of FIG.
  • FIG. 25 is a block diagram of a block diagram of an embodiment of the independent invention 3 of the successive approximation ratio AZD converter.
  • the SMNS output EVNS output from the amplifier 92 in FIG. 24 is compared with the reference voltage VRX by the comparator 102.
  • the output signal of 102 is input to the serial ratio register 103, and the output signal of 103 is sent to the D / A converter 105 via the switching circuit 104.
  • the output signal of the DZA converter 105 is fed back to the comparator 102 via the switching circuit 101.
  • Circuits 101 and 104 when used as AZD converters, connect 108 and 107 and connect 109 to I10. Then, when used as a DZA converter, 108 and 105 are connected, and 112 and 110 are connected.
  • 97 is a digital memory. Send the signal voltage to 102.
  • the horizontal CC outputs one pixel of smearing charge during about 7 horizontal scanning periods.
  • the successive ratio type A-ZD converter shown in Fig. 25 produces a 6-bit digital signal.
  • FIG. 24 is a cross-sectional view of one embodiment showing the independent invention 4.
  • a P-type well region (2 ⁇ 10 [15] atoms ZC C) 32 is arranged on an N-type substrate (4 ⁇ 10 ⁇ 14 ⁇ atoms / CC) 20 .
  • An N-type bulk channel region (10 [1 6 ⁇ atoms / CC) 22 is disposed thereon. Polon ions are implanted into the surface of the first region 22 A of the N-type bulk channel region 22 to form a potential barrier region 3.
  • the channel region 22B other than the potential barrier region 34 is a potential well region.
  • a P-type channel stop region (4 X 10 M 7] atom CC) 23 is created.
  • a silicon oxide film 36 C and a silicon nitride film 36 ⁇ are formed on the surfaces of the regions 22 and 23.
  • a second transfer electrode 37 ( ⁇ , ⁇ , C) of about 1 micron is formed on this by the doped silicon.
  • the above-mentioned second transfer electrode has a branch electrode 37 X extending vertically above the channel stop region 23. Then, the second transfer electrode is oxidized to form a silicon oxide film 36 ⁇ on the surface thereof. Then, the oxide film on the branch electrode 37X is etched, and the branch electrode 37X is exposed. Then, a first transfer electrode 35 (A, B, C) having a thickness of about 0.6 ⁇ m is formed by the polysilicon doped with phosphorus. The first transfer electrode is connected to the first transfer electrode on the exposed surface and side surface of the branch transfer electrode 37X.
  • FIG. 27 is a cross-sectional view in a direction perpendicular to FIG. 26, and FIG. 28 is a plan view of one embodiment of FIGS. 25 and 26. The description of the above embodiment is added below.
  • an output inverter of an odd (even) number feed stage and an output inverter of an even (odd) number transfer stage alternately perform a charge operation and a logic discharge (evaluation) operation alternately.
  • the shift register may be designed so that the charging operation of one of the output converters always precedes the evaluation operation of the other.
  • This 1 shift register driven 1 E / B transfer area sensor requires one transfer stage (two inverters) of shift register per DVTG of vertical CCD, and thus has the disadvantage that the vertical pixel row pitch cannot be reduced.
  • the output inverter of the shift register 2A can have a ratioless dynamic structure, which saves power consumption and eliminates the manufacturing process compared to the CMOS shift register of the 2E / B transfer area sensor. become.
  • the output inverter of the CMOS shift register consumes a considerable amount of transient current. Furthermore, during the precharge period P of the above-mentioned ratio output inverter, the next evaluation (discharge) operation is performed after the vertical scanning line having the shallow potential VL is charged again to the deep potential VH. Becomes stable.
  • the structure of the above-mentioned ratio dynamic shift register is basically the same as the shift register 2A or 2B in FIG. 5, and each output contact 12A of the shift register is sequentially connected to each vertical scanning line. .
  • the output voltage from each transfer stage of the 1st shift register is the odd voltage of the vertical CCD.
  • the clock voltage output from each transfer stage of the second shift register is applied to the (even) th clock DVTG, and the even (odd) clock DVTG of the vertical CCD.
  • one transfer stage is composed of two inverters in a two-phase shift register, and the clock voltage is output from the output contact of one of the inverters (called the output inverter 1).
  • the above two shift registers are dynamic shift registers in which the output inverter alternately performs a charging operation, a holding operation, and a discharging operation.
  • the output inverter is preferably a ratio inverter capable of reducing the output resistance.
  • each output contact of the first and second shift registers outputs VH first.
  • the output inverters of the first and second shift registers alternately perform charging and evaluation operations.
  • the charging operation of the output inverter of one shift register always precedes the evaluation operation of the output inverter of the other shift register.
  • a shallow potential from the input terminal 2 C of each shift register VL is input in order.
  • This 2-shift register driven 1E ZB transfer area sensor has high integration, low power consumption and simple manufacturing process. (Additional explanation for Fig. 9)
  • This 1 shift register drive type 2 E / B transfer sensor outputs the clock voltage output from the 1 /-transfer stage of the 2-phase shift register, that is, the clock voltage output from the output contact of each inverter. Is applied to each clock ND V TG of the vertical CCD. The odd (even) output contacts of the shift register output VL first, and the even output contacts output VH.
  • VL and VH are alternately input from the input terminals of the shift register, and the odd (even) -numbered inverter 11A and the even (odd) -numbered inverter 11B of the shift register are alternately logically connected.
  • the discharging operation and the holding operation are performed.
  • Each inverter of this shift register performs a logical discharge operation and a holding operation, and is preferably a static inverter (especially CMOS) which does not require a charging operation.
  • the odd (even) clock ND VTG of the vertical CCD is the first shift.
  • the clock voltage output from each transfer stage of the register is applied.
  • the even (f) -th clock NDVT.G is applied with the clock voltage output from each transfer stage of the second shift register.
  • one transfer stage is composed of, for example, two inverters in a two-phase shift register.
  • each transfer stage of the I shift register outputs VL
  • each transfer stage of the second shift register outputs V ⁇ .
  • the output inverters of the first and second shift registers perform the holding operation and the discharging operation alternately.
  • FIG. 16 A to L
  • Fig. 16 (A to L) explains the vertical tilling operation of the two-clock-line-driven 1 EZB transfer sensor in Figs. 14 and 15 .
  • Shift register 2 has one output contact per transfer stage, and is preferably a two-phase shift register.
  • each output contact of the shift register 2 outputs VH, all the sequential switches 16 (Z to V) conduct, and the clock lines 27 and 2 Y 'become VH, and each vertical switch becomes VH.
  • Scan line 3 (from Z to V) becomes VH, and signal charges Q1 to Q5 are accumulated under each clock DVTG 3 (from Z to V).
  • the read electrodes VR are applied to the clock lines 2Z 'and 2Y' during the period T1.
  • each output contact of the shift register becomes VL, and each sequential switch 16 (from Z to V) is shut off.
  • Shift register 2 has i output contacts per transfer stage. Then, during the T1 period before the vertical transfer is performed, each output contact of the shift register 2 becomes VH, each switch 16 (Z, X, VT) is sequentially turned on, and the clock line 2 2 is connected to the intermediate potential VM. become. Then, as explained in Fig. 23 ⁇ , each signal charge Q1 to Q7 is arranged between the potential bowl door under each clock D VTG (3Z, 3X.3V, 3T) and between them. Is accumulated in the intermediate DC potential well.
  • clock line 2Y goes to VL, and each clock DV TG goes to VL. Thereafter, each output contact of the shift register goes to VL, and each switch is turned off sequentially.
  • the charge switch of the output inverter of the shift register should be made conductive, and the potential of the vertical scanning line should be controlled via the above-mentioned charge switch.
  • FIG. 5 Another mode of operation of the shift register of FIG. 5 is described with reference to FIG. P is the period during which the charge switch 8A or 8B conducts and the discharge switches 10A, 10B are shut off, and E is the period during which the charge switch is shut off and the discharge switch conducts.
  • the retention period is the period during which the charge and discharge switches are cut off.
  • the preceding connection switches 7A and 7B conduct during the charging period P to input the logic information, but these can be implemented separately.
  • the feature of this embodiment is that the output inverter 11 A operates in the order of P, ⁇ , ⁇ , and the inverter 11 18 operates in the order of £, 11,?.
  • Shift register 2 ⁇ has a 180 ° phase difference from shift register 2 ⁇ .
  • FIG. 30 is an equivalent circuit diagram of one embodiment of the shift register of FIG. 4 (A to F) or FIG. 9 or FIG. 10 (A to L) or FIG. 14 or FIG.
  • FIG. 31 is an equivalent circuit diagram showing a modified embodiment of the two-phase ratioless dynamic shift register of FIG.
  • the principle of this well-known two-phase shift register is basically the same as that of the two-phase shift register shown in FIG. 5, and the description of its operation is omitted. If this two-phase ratio-less dynamic shift register is used without the first switch, the shift register can be made smaller and the pixel density can be improved.
  • FIG. 33 shows a block circuit of a frame transfer area sensor that drives a vertical CCD by two-shift register driving 1 EZB transfer of FIG.
  • a vertical CCD also serving as a pixel column and a horizontal CCD 5
  • a storage area 4C constituted by a buffer CCD is arranged.
  • a transfer gate 4A is arranged between the storage area 4G and the horizontal CCD 5.
  • the vertical CCD in the image section 1 transfers signal charges during the vertical blanking period by the 1 EZB transfer method described in Fig.
  • the buffer CCD of the storage unit 4C temporarily stores signal charges received from the vertical CCD.
  • the above buffer CCD is driven by shift registers 2D and 2E having the same structure as shift registers 2A and 2B. However, the shift registers 2D and 2E have the same initial state as FIG. Then, in the first half of the subsequent high-speed transfer period, the buffer CCD performs a 2 CD clock transfer. This two-phase clock transfer can be easily implemented by injecting the shallow potential VL into the shift register 2D (or 2E) and the deep potential VH into the shift register 2E (or the shift register 2D).
  • FIG. 34 is a transmission state diagram showing a part of the first half of the high-speed transfer period of the buffer CGD, and the operation proceeds from FIG.
  • 3 4 (H from E) is a transfer state diagram showing a part of a period of the second half of the high-speed transfer period of the operation is 3 4 3 4 you proceed to H n that is, the shift register from E
  • the transfer pulse information to be injected into 2D (or 2E) from the shallow potential VL to the deep potential VH in the latter half of the high-speed transfer period
  • the signal below each D VT G that composes Charge can be stored become.
  • the vertical transfer of the vertical CCD and the transfer from the buffer CCD to the horizontal CCD are the 1 E / B transfer described so far, and detailed description is omitted.
  • each DVTG (directional transfer electrode) placed on the potential wells 3Z, 3X, 3V, and 3T of the buffer CCD 6C is a two-phase CM0S shift.
  • the potential wells 3Y, 3W, 3U of the buffer CCD are driven by the two-phase CMOS shift register 2E. 2 F .2 G is its input.
  • the potential well number of the buffer CCD overlaps with that of the vertical CCD.
  • FIG. 35 is a transfer state diagram of the two-shift register drive 1 EZB-transfer FT area sensor of FIGS. 33 and 34 (A to H).
  • tO represents the first state of the vertical scanning period
  • t1 to 1: 5 represent the first half of the high-speed transfer period
  • t6 to t9 represent the second half.
  • the vertical CCD and the buffer CCD have NDVTG, and their CMOS shift registers use the one shift register two EZB transfer method disclosed in FIG.
  • the CVIOS shift register has the disadvantage that the manufacturing process is complicated, the yield is poor, and the transient current is large because a small output inverter charges and discharges a large vertical scanning line capacitance.
  • Conclusion (4) The power consumption increases, and the dark current increases due to the rise in the temperature of the sop.
  • FIG. To H can use the 2 shift register 2 E / B transfer method. That is, a vertical CCD composed of NDVTG is driven by two CM0S shift registers described in FIG. 10 ( ⁇ to H), and similarly, a buffer CCD is also composed of two CMOS shifts. Driven by an external register. Then, in the first half of the high-speed transfer period, the shallow potential VL and the deep potential VH are alternately injected from the input terminal of each shift register that drives the buffer CCD, and the buffer CCD is driven substantially by a four-phase clock.
  • the input terminal of the first shift register for driving the buffer CCD starts.
  • the shallow potential VL is injected
  • the deep potential VH is injected from the input terminal of the second shift register that drives the buffer CCD.
  • the buffer CCD outputs the signal charges to the horizontal CCD by the two-shift register driving two EZB transfer method for each horizontal scanning period in the next vertical scanning period.
  • the 2-shift register driving 2 EZB transfer accordion imager of the present invention includes two CMOS shift registers, and each shift register has an odd (even) number.
  • the invertor becomes the output inverter, and the description of the above embodiment is added below.
  • the CCD channel is N-shaped, and the shallow potential VL is, for example, 0 V, the deep potential VH is, for example, +7 V, and the 'deepest readout voltage VR is +12 V.
  • the above VL.VH.VM is the relative potential of the same part.
  • the shallow potential VL of the transfer electrode and the shallow potential VL of the potential well are different levels of potential.
  • VD in Fig. 5 is the higher power supply
  • VS is the lower power supply.
  • VLL, VLH, VM, VHL, and VHH in Figs. 12, 17, and 19 are the potentials of the respective channel regions.
  • ⁇ in FIG. 35 represents a potential well having a deep potential VH, and a potential well without a symbol is a potential well having a shallow potential VL.
  • Shift register drive 1 An embodiment using a ratioless dynamic shift register in the E / B transfer method. Reduce power consumption and simplify the process.
  • (B) Application of interline transfer CCD area sensor to vertical CCD. It improves the dynamic range of a vertical CCD and enables many applications such as smearing charge transfer.
  • (C) application to a CCD area sensor that outputs two adjacent pixel rows during one horizontal scanning period.
  • the EZB transfer method of the present invention the structure of a vertical CCD with two adjacent pixel rows and a ZH output can be extremely simplified, and a dynamic range can be secured.
  • This embodiment is particularly effective for a single color TV camera using an IT sensor or a still camera for outputting frame images.
  • D used as accordion imager 1 EZB tilling area sensor n 2 shift register drive type 1 E, ZBfe transmitter.
  • Cordion imager simplifies the manufacturing process of shift register, and Reduce its power consumption.
  • the clock line drive 1 EZB transfer accumulator-de-on-measure makes the load capacity of the shift register extremely small, making it easy to manufacture and advantageous for high-speed transfer.
  • Register drive 2 EZB ⁇ transfer accord — Deon imager has higher pixel row density than 1 shift register drive accordion demagnifier. As a result, the output inverter can be designed to be large and the input voltage of the output converter can be changed quickly, so that the transient current is small.
  • FIG. 1 is a block diagram of an embodiment of a 1-shift register driven CIE / Bfe transmission area sensor of independent invention 1 according to an embodiment.
  • vertical scanning lines 3 are arranged on both sides of an imaging area 1. It is driven by shift register 2 A.2B.
  • FIG. 2 is a block diagram of a two-shift register-driven GI EZB transfer area sensor according to an embodiment of the present invention. The odd (even) number of vertical scanning lines 3A are different from the even (odd) number of vertical scanning lines 3B. It is driven by shift registers 2A and 2B.
  • Figure 3 is a vertical transfer state diagram of a 1 shift register drive type 1 EZB transfer area sensor, in which transfer pulse information VL or VH is injected from input terminal 2-C of shift register 2A. This means that the signal charge Q (2 to 6) of the potential well 3 (U to Y) is transferred.
  • Fig. 4 is a vertical transfer state diagram of a 2-shift register driven 1 E / B transfer area sensor, in which transfer pulse information is alternately injected from the input terminals of shift registers 2A and 2B. Indicates that signal charge Q (2 to 6) of potential well 3 (U to Y) is transferred.
  • FIG. 5 is an equivalent circuit diagram of one embodiment of the shift register 2A.2B of FIG.
  • FIG. 6 is a clock voltage diagram of the shift register 2A.2B in FIG. 7 and 8 are equivalent circuit diagrams of a buffer circuit of a shift register driving type CIE ZB transfer area sensor according to an embodiment.
  • Fig. 9 is an equivalent circuit diagram of one embodiment of a 1 shift register drive type 2 EZ transmission area sensor.Each output inverter 1 1 A.1 1B of shift register 2 ⁇ output contact 1 2 ⁇ . The potential change of the vertical scanning line 3 (from W) connected to 1 2 B is also shown.
  • Figure 10 (A to H) shows 2-shift register drive type
  • FIG. 2 is a vertical transfer state diagram of the EZB transfer area sensor, showing a potential well P or a potential barrier.
  • FIG. 9 is the same as in FIG. 0 (A to H).
  • Fig. 11 (A to C) is a relocation diagram of the residual charge of the 1 EZBfe transmission IT sensor. It shows that the residual noise charge can be offset by calculating the charge of the adjacent two potential wells.
  • Fig. 11 (D to F) is a residual charge relocation diagram of the 2E / B transfer IT sensor, showing that residual noise charges can be offset by subtraction of adjacent two potential wells.
  • Figure 12 shows a non-directional transfer electrode 35 with an intermediate potential VM.
  • FIG. 5 is a cross-sectional view of one embodiment of an EZB transfer area sensor provided between the DVT G and the vertical CCD.
  • the vertical CCD is a shift register driven type 1 EB transfer technology described above or a cross-sectional view described later. 'Sound line drive type 1 Transferred by EZB transfer technology.
  • FIG. 13 is a channel potential diagram of the vertical CCD of FIG.
  • FIG. 14 is a diagram showing one driving circuit of one clock of the two clock line driving type 1 E / B transfer area sensor.
  • FIG. 15 is a waveform diagram of the clock voltages V 1 and V 2 of FIG.
  • FIG. 16 (from A to L) is a vertical transfer breakdown diagram of the vertical CCD 6 driven by the drive circuit of FIG. 14, and shows the signal charge Q (1 to 6) of the potential well 3 (from Z to U). ) Are transferred in order.
  • FIG. 13 is a channel potential diagram of the vertical CCD of FIG.
  • FIG. 14 is a diagram showing one driving circuit of one clock of the two clock line driving type 1 E / B transfer area sensor.
  • FIG. 15 is a waveform diagram of the clock voltages V 1 and V 2
  • FIG. 17 is a cross-sectional view of one embodiment of a 1 EZB transfer area sensor in which directional transfer electrodes 3 Y and 3 W having an intermediate potential are arranged between clocks DVTG 3 Y. (Intermediate electrode)
  • the channel region 22A below 3Y and 3W is composed of a medium potential well region 22B and a medium potential barrier region 22C.
  • FIG. 18 is a channel potential diagram of the vertical CCD of FIG.
  • FIG. 19 is a cross-sectional view of one embodiment showing a modification of the vertical CCD of FIG. 17.
  • FIG. 20 is a channel potential diagram of the vertical CCD of FIG.
  • FIG. 21 is a driving circuit diagram of one embodiment of a 1-clock line driving type 1 EZB transfer error sensor, and shows a driving circuit of the vertical CCD described in FIGS. 17 and 19.
  • FIG. 22 is a waveform diagram of the clock voltage V1 in FIG.
  • FIG. 23 (from A to L) is a vertical transfer state diagram of the vertical CCD 6 driven by the drive circuit in FIG. 21.
  • the signal charge Q (from l to 8) of the potential 3 (from Z to D) is shown.
  • FIG. 24 is an equivalent circuit diagram of one embodiment representing the technique of the independent 1H storage partial subtraction technique of the independent invention 2.
  • FIG. 24 is an equivalent circuit diagram of one embodiment representing the technique of the independent 1H storage partial subtraction technique of the independent invention 2.
  • FIG. 25 is an equivalent circuit diagram of one embodiment of the smearing memory circuit of the independent invention 3.
  • FIG. 26 is a cross-sectional view of one embodiment of the two-electrode-coupled FT sensor according to Independent Invention 4, showing the channel region 22 of the vertical CCD.
  • FIG. 27 shows a cross section perpendicular to the cross section of m 26, and shows the channel regions 22 B of a plurality of vertical CCDs arranged in parallel.
  • Figure 28 shows one implementation of the vertical CCD shown in Figures 26 and 27. It is an example top view.
  • FIG. 29 is a clock voltage diagram showing another operation example of the shift register of FIG.
  • FIG. 30 is an equivalent circuit diagram of one embodiment of the shift register used in the 2-shift register driving 2 E / B transfer method of FIG.
  • FIG. 31 is an equivalent circuit diagram of the shift register used in the 2-shift register driving 1 EZB transfer method of FIG. 4 (A to F).
  • FIG. 32 is a clock voltage diagram of the shift register of FIG.
  • FIG. 33 is an equivalent circuit diagram of an embodiment of an accordion imager using a 2-shift register driven 1EB transfer method.
  • FIG. 34 (A to H) is a transfer state diagram showing the operation of the buffer CCD of FIG. 33 and the shift register that drives it.
  • FIG. 35 is a transfer state diagram showing the operation of the accordion imager of FIGS. 33 and 34 (A to H).

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  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

Capteur de surface à CCD. L'invention vise à résoudre le problème posé par le fait que la fonction de transfert de charges de l'élément CCD vertical (6) limite les performances du capteur de surface à CCD. Dans le capteur de surface à CCD ci-décrit, la caractéristique fondamentale est que les électrodes de transfert des impulsions de synchronisation (3) (Z à U) de l'élément CCD vertical (6) sont commandées par des tensions de synchronisation différentes afin de transférer de manière indépendante les charges de signaux des puits de potentiel pleins de l'élément CCD vertical (6), que le puits de potentiel vide est injecté à partir du terminal de sortie de l'élément CCD vertical (6), et que le puits de potentiel suivant est injecté à partir dudit terminal de sortie avant que le puits de potentiel vide injecté au préalable n'atteigne l'extrémité opposée du terminal de sortie de l'élément CCD vertical (6).
PCT/JP1985/000038 1984-01-30 1985-01-30 Dispositif de prise d'images a semi-conducteur WO1985003398A1 (fr)

Applications Claiming Priority (16)

Application Number Priority Date Filing Date Title
JP59015950A JPS60160271A (ja) 1984-01-30 1984-01-30 Ｃｃｄエリアセンサ
JP59/15950 1984-01-30
JP59/34839 1984-02-25
JP59034839A JPS60210079A (ja) 1984-02-25 1984-02-25 固体エリアセンサの電荷転送方法
JP59/49685 1984-03-14
JP59049685A JPS60192471A (ja) 1984-03-14 1984-03-14 固体エリアセンサ
JP59069835A JPS61105180A (ja) 1984-04-06 1984-04-06 固体エリアセンサ
JP59/69835 1984-04-06
JP59091417A JPS60235591A (ja) 1984-05-08 1984-05-08 固体撮像装置
JP59/91417 1984-05-08
JP59095314A JPS60239181A (ja) 1984-05-12 1984-05-12 固体撮像装置
JP59/95314 1984-05-12
JP59189970A JPS6167376A (ja) 1984-09-10 1984-09-10 固体撮像装置
JP59/189970 1984-09-10
JP59211797A JPS6190576A (ja) 1984-10-09 1984-10-09 固体撮像素子
JP59/211797 1984-10-09

Publications (1)

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WO1985003398A1 true WO1985003398A1 (fr) 1985-08-01

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5187912A (fr) * 1975-01-30 1976-07-31 Sony Corp
JPS5264219A (en) * 1975-11-20 1977-05-27 Rca Corp Method of reducing effect of smear charge signal for charge coupled image pickup device
JPS59167186A (ja) * 1983-03-11 1984-09-20 Shoichi Tanaka 固体撮像装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5187912A (fr) * 1975-01-30 1976-07-31 Sony Corp
JPS5264219A (en) * 1975-11-20 1977-05-27 Rca Corp Method of reducing effect of smear charge signal for charge coupled image pickup device
JPS59167186A (ja) * 1983-03-11 1984-09-20 Shoichi Tanaka 固体撮像装置

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