WO1985003398A1 - Solid state pick-up device - Google Patents

Solid state pick-up device Download PDF

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Publication number
WO1985003398A1
WO1985003398A1 PCT/JP1985/000038 JP8500038W WO8503398A1 WO 1985003398 A1 WO1985003398 A1 WO 1985003398A1 JP 8500038 W JP8500038 W JP 8500038W WO 8503398 A1 WO8503398 A1 WO 8503398A1
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WO
WIPO (PCT)
Prior art keywords
transfer
clock
imaging device
solid
ccd
Prior art date
Application number
PCT/JP1985/000038
Other languages
French (fr)
Japanese (ja)
Inventor
Shoichi Tanaka
Original Assignee
Shoichi Tanaka
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59015950A external-priority patent/JPS60160271A/en
Priority claimed from JP59034839A external-priority patent/JPS60210079A/en
Priority claimed from JP59049685A external-priority patent/JPS60192471A/en
Priority claimed from JP59069835A external-priority patent/JPS61105180A/en
Priority claimed from JP59091417A external-priority patent/JPS60235591A/en
Priority claimed from JP59095314A external-priority patent/JPS60239181A/en
Priority claimed from JP59189970A external-priority patent/JPS6167376A/en
Priority claimed from JP59211797A external-priority patent/JPS6190576A/en
Application filed by Shoichi Tanaka filed Critical Shoichi Tanaka
Publication of WO1985003398A1 publication Critical patent/WO1985003398A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H04N25/625—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of smear

Definitions

  • Solid-state imaging device Solid-state imaging device.
  • the present invention relates to solid-state imaging device technology, and more particularly to improvements in CCD solid-state imaging devices.
  • a CCD area sensor in which a vertical CCD also serves as a pixel array is called a frame transfer CCD area sensor (abbreviated as an F T sensor).
  • An FT sensor including a buffer CCD for storing signal charges representing a one-field image between a vertical CCD and a horizontal CCD is called a buffer FT sensor.
  • An FT sensor without a CCD is called a full-frame FT sensor.
  • a CCD area sensor having a vertical CCD arranged independently of a pixel column is called an interline transfer CCD area sensor (IT sensor).
  • An IT sensor in which a transfer electrode (AT G) arranged between a pixel and a vertical CCD is connected to a transfer electrode (abbreviated as VTG) of the vertical CCD is called a common transfer electrode IT sensor.
  • CCDs are driven by 1, 2, 3, and 4 phase clock voltages, but it has been proposed to use more multi-phase clock voltages.
  • Japanese Patent Laid-Open No. 56-35067 subtracts a previously recorded one-line smearing from a one-line signal output later. Disclose things.
  • a first object of the present invention is to improve the SZN ratio of a solid-state imaging device. It is also important to improve the resolution.
  • a second object of the present invention is to improve the resolution of a solid-state imaging device.
  • the present invention discloses four independent inventions regarding a CCD area sensor. Each independent invention is explained-because it has a deep interrelationship and a synergistic effect can be created by implementing it in the background.
  • Independent invention 1 discloses a technique for driving a vertical CCD of a CCD area sensor by a CCD transfer method named continuous injection EZB transfer (abbreviated as CIE / B transfer) by the present inventor.
  • CIE / B transfer continuous injection EZB transfer
  • the feature of the above CIE / B transfer is that a different clock voltage is applied to each clock transfer electrode of the vertical CCD, and the empty potential well injected from the output end of the vertical CCD arrives at the opposite end from the above output end. Then, the next empty potential well is injected from the above output terminal.
  • Independent invention 2 discloses that in a CCD area sensor, a difference between a signal of a pixel output from a pixel of a part of the saturated pixel line and a pixel of the saturated pixel line is detected in advance.
  • the smearing reduction method of the independent invention 2 may be very effective.
  • Independent invention 3 discloses that in a CCD area sensor, a horizontal CCD is horizontally transferred at a low speed during a vertical blanking period (a period during which signal charges are not horizontally transmitted) to output smear noise charges.
  • the smear noise reduction technology disclosed in Independent Invention 2 is very effective, but has the problem of significantly increasing costs.
  • Independent invention 3 solves this problem.
  • Independent invention 4 discloses that in a PT sensor, two adjacent transfer electrodes are connected above a channel region of a vertical CCD or a channel region between vertical CCDs.
  • each of the clock transfer electrodes substantially constitutes one pixel, it is highly preferable that the light transmittance of each clock transfer electrode is equal. Since a complicated clock voltage is applied from a drive circuit having multiple electrodes, it is preferable that the line resistance of each clock transfer electrode be small in order to increase the operation speed.
  • Independent invention 4 manufactures a clock transmission electrode having a uniform light transmittance and a small line resistance. The basic features of each independent invention and its dependent inventions are described below. The specific features and effects of each invention are described below.
  • a two-dimensional array of multiple pixels a vertical CCD that also serves as a pixel column, or is arranged independently of the pixel column, and a horizontal CCD.
  • the above vertical CCD transfers the signal charge of the pixel column to a horizontal CCD.
  • the vertical CCD includes one or both of a directional transfer electrode (abbreviated as DVTG) and a non-directional transfer electrode (abbreviated as ND VTG), and A part or all of the above DVTG or NDVTG is a transfer electrode to which a transfer voltage is applied (abbreviated as a close transfer electrode), and a clock transfer close to the output end of the vertical CCD.
  • DVTG directional transfer electrode
  • ND VTG non-directional transfer electrode
  • a part or all of the above DVTG or NDVTG is a transfer electrode to which a transfer voltage is applied (abbreviated as a close transfer electrode), and a clock transfer close to the output end of the vertical CCD.
  • the transfer voltage and voltage are applied in order from the electrode, and the empty potential well injected from the output end of the vertical CCD arrives at the opposite end from the output end of the vertical CCD. Is injected from the output end of the vertical CCD.
  • the first feature is that the charge of the potential door created under the clock DVTG and the charge of the intermediate DC potential stirrer placed between two adjacent clocks DVTG are transferred independently.
  • the solid-state imaging device according to claim 1. (7) Equipped with N 'DVTG (abbreviated as NDVTG) which is a clock transfer electrode, and the electric charge of the 3 ⁇ 4-position parallel to the odd (even) -numbered clock VTG is reduced to 3'. 2.
  • NDVTG which is a clock transfer electrode
  • each clock transfer electrode of the vertical CCD is connected to an output contact of a shift register or an output contact of a buffer circuit controlled by the shift register.
  • the odd (even) number clock transfer electrode (specifying clock NDVTG or clock D VTG) of the vertical CCD and its even (odd) number clock transmission electrode are 10.
  • an interline transfer CCD sensor (hereinafter referred to as common transfer) in which a transfer electrode (hereinafter abbreviated as ATG) that electrically connects the pixel and the vertical CCD is connected to the clock transfer electrode of the vertical CCD.
  • ATG transfer electrode
  • Imaging device. (14) wherein each clock DVTG of the vertical CCD is connected to a one-phase or two-phase clock power supply via a sequential switch, and the sequential switch is controlled by a shift register.
  • Each clock transfer electrode of the vertical CCD is sequentially driven by a clock power supply via a switch, and the above clock DVTG or the odd (even) th clock ND VTG is set before the vertical transfer period.
  • the solid-state imaging device according to claim 1 wherein the solid-state imaging device is charged to a deep potential VH, and a voltage is applied to each clock transfer electrode only through the above-mentioned sequential switch during the next vertical transfer period.
  • the above clock DVTG or the odd (even) th clock NDVTG is applied with the deep potential VH or the read potential VR by the above clock power supply.
  • interline transfer CCD sensor (abbreviated as ⁇ ⁇ sensor), which performs frame accumulation operation at low illuminance and performs field accumulation operation at high illuminance 2.
  • ⁇ ⁇ sensor interline transfer CCD sensor
  • a solid-state imaging device that transfers signal charges to a horizontal CCD, the smearing voltage of a pixel row (abbreviated as a saturated pixel row) including a pixel that generates a saturated signal charge (abbreviated as a saturated pixel row) is recorded.
  • a solid-state imaging device characterized in that the stored smearing voltage is subtracted from a signal voltage generated from at least a part of the pixels of the saturated pixel row.
  • a feature of the present invention is that the above-mentioned smearing voltage is not subtracted from the signal generated from a part or all of the pixels generated from the pixels downstream from the saturated pixels in the saturated pixel row.
  • Item 13 The solid-state imaging device according to Item 1.
  • the horizontal CCD horizontally transfers the scan charges at the first speed during the vertical retrace period, and transfers the second charge during the horizontal scan.
  • Horizontal transfer at the speed, and the first speed above is the second A solid-state imaging device characterized in that the speed is 1 to 2 or less.
  • the solid-state imaging device described in Section 30 is characterized in that the smears reproduced from the digital memory are DZA-converted by the DZA converter of the successive-ratio AZD converter.
  • the present invention relates to a CCD area sensor, in which a different clock voltage is applied to each vertical transfer electrode of the vertical CCD, and an empty potential well injected from the output terminal of the vertical CCD is connected to the other end of the vertical CCD. Before arrival, the next empty potential well is injected again from the above output terminal, and the electric charges of all the electric potentials of the vertical CCD are independently transferred.
  • the above transfer is abbreviated as continuous injection ⁇ transfer (CI ⁇ transfer).
  • CI ⁇ transfer continuous injection ⁇ transfer
  • Each charge of the vertical CCD is transferred to the potential bowl under all directional transfer electrodes (DVTG) or the odd (even) number of non-directional transfer electrodes before performing the above-mentioned CI ⁇ / ⁇ transfer. (NDV TG) accumulated in the potential well.
  • NDVT G is a transfer electrode that has a constant channel potential below it and can transfer charges in either direction
  • DVT G is a potential obstacle with a shallow potential VL to the channel below it.
  • This is a transfer electrode in which a wall region and a potential well region waiting for a deep potential VH are formed.
  • a four-phase CCD has four types of NDVTG
  • a two-phase CCD has two types of DVTG.
  • the shallow potential VL is a larger potential in the negative direction in an N-channel CCD
  • the deep potential VH is a larger potential in the positive direction.
  • the number of transfer electrodes per pixel can be halved compared to a conventional vertical CCD driven by a two-phase or four-phase clock voltage. And the charge transfer capability can be reduced to two. It is known that a different voltage is applied to each transfer electrode of a CCD, and the electric charge under each DVTG or under an odd (even) NDVTG is independently transferred. And Thompset, Modern Science, Inc., Charge Transfer Devices, pp. 36-37 and 228-229. However, in the above prior art, one empty potential well (potential well holding no charge) is reversely transferred from the output end of the vertical CCD to the opposite end, so that the entire charge is shifted by one potential well pitch. Only till each.
  • each clock transfer electrode receives a different clock voltage E.
  • An empty potential well is injected from the output end of the vertical CCD, and the next empty potential bowl is injected from the output end before the injected empty potential bowl arrives at the opposite end.
  • a one-phase, two-phase, or four-phase clock voltage is applied to each clog transfer electrode.
  • Empty potential well When arriving at the opposite end of the direct CCD or arriving at the black and slow transfer electrodes one bit downstream, empty potential wells between each signal charge well (potential well holding signal charge) Is arranged. Therefore, after the empty potential well arrives at the opposite end, the vertical CCD can be driven with the conventional one-phase, two-phase or four-phase clock voltage.
  • An important advantage of the present invention is that it can independently transfer the charge in all potential wells that a vertical CCD can make.
  • two empty potential wells are injected from the output of the vertical CCD during one horizontal retrace period.
  • signal charges of two adjacent pixel rows can be output independently in one horizontal scanning period.
  • injecting an empty potential well is equivalent to outputting the charge of one potential well of the vertical CCD from its output terminal.
  • two adjacent potential wells in a vertical CCD transfer charge for the same pixel. This effectively doubles the dynamic range of vertical CCD.
  • the vertical CCD is provided with a clock DVTG, and the charge in the potential well under each clock DVTG is transferred independently.
  • one D VTG is arranged per pixel.
  • the vertical CCD of the IT sensor comprises two DVTGs per pixel.
  • the signal charges of one pixel are transferred between two adjacent potential wells. Alternatively, transfer the signal charge in the odd (even) number potential well and transfer the noise charge (especially the smear noise charge) in the even (odd) number potential well. That is, 2. It is possible to read out the charges in the pixel row, or to double the charge transfer capability of the vertical CCD, or to transfer the signal charges and noise charges separately.
  • the odd (even) potential wells transfer signal charge, and the non-transferred charge in the even (odd) potential well adjacent upstream It is also possible to collect. As a result, transfer efficiency is improved.
  • an intermediate DC potential can be applied to an intermediate channel region between adjacent binary clocks D VTG.
  • This embodiment is particularly preferable for an FT sensor.
  • an ND VTG having an intermediate DC potential is arranged on the above-mentioned intermediate channel region. Since this ND VTG has a constant voltage, it can be made very thin and has high blue sensitivity.
  • the vertical CCD has a bulk channel, and the surface of the exposed intermediate channel region is implanted with a constant intermediate potential applied to the underlying bulk channel region. The exposed intermediate channel region has a high blue sensitivity.
  • the vertical CCD includes a clock D VTG and an intermediate DC potential well and an intermediate DC potential barrier created in an intermediate channel region between the clocks DVTG.
  • the intermediate DC potential bowl and the intermediate DC potential barrier can be provided by arranging the DVTG to which the intermediate DC potential is applied above the intermediate channel region between the clock DVTGs, or by exposing the intermediate bulk channel region. Created by performing two ion implantations on the surface. When this embodiment is applied to an FT sensor, the sound sensitivity is improved.
  • an odd-numbered stirrer door is created below the odd-numbered clock ND VTG, and a potential barrier is created below the even-numbered clock MD VTG.
  • two clock VTGs are arranged per pixel.
  • the interlaced operation can be performed by reversing the positions of the upper well and the potential barrier every field period, and the number of vertical pixels is equivalently doubled.
  • one ND VTG can be arranged per pixel.
  • an interlace operation can be performed by transferring signal charges of different pixel rows for each field period.
  • 2 NDVTG per pixel the signal charges of 2 pixel rows are read out in parallel, and other dependent inventions 3 explain.
  • the implemented charge transfer method can be implemented.
  • each clock electrode of the vertical CCD is connected to an output contact of a shift register for generating a vertical transfer clock voltage or an output contact of a current amplification buffer circuit controlled by the above-mentioned output contact.
  • the above buffer circuit is generally a source follower circuit or a common-source inverter circuit and has a small output resistance.
  • CIE / / B transfer C CD area sensor (hereinafter as (Kooite 2 EZB transfer sensor comprises a clock ND VTG.
  • each clock ND VTG's respective inverters constituting the two-phase shift register Connect it to the output contact or to the output contact of the buffer ⁇ circuit controlled by the output contact described above, which will generate the vertical cut-off voltage of the 2 E / B transfer sensor.
  • Each clock ND VTG may be connected to the output contact of the odd (even) number inverter of the register.
  • each clock D VTG is composed of two inverters constituting a two-phase shift register. Connected to the output contact of the odd (even) numbered inverter or to the output contact of the buffer circuit controlled by the above output contact. In this way, the vertical clock voltage of one EZB transfer sensor can be generated.
  • each clock DVTG is directly or directly connected to the output contact of one of the four types of inverters that constitute the four-phase shift register. It can be connected via a buffer circuit.
  • the clock DVTG may be connected directly to the output contact of one of the three types of inverters constituting the three-phase shift register or via a buffer circuit. That is, the wording of claim 11 means that each clock DVTG is connected to one output contact per transfer stage of the shift register. Of course, each clock DVTG means the clock DVTG of each row. In claim 10, the clock ND VTG is connected to one output contact per 1/2 transfer stage of the shift register. In claim 9, a two-phase shift register is particularly preferred because it is simple in structure and operation and can increase the pixel density in the vertical direction.
  • the inverter (shifted output inverter) of the shift register connected to the clock DVTG or the buffer inverter constituting the buffer circuit performs a ratioless operation. Since the ratio inverter has a charge period for charging the above output contacts all at once before the evaluation period for logically discharging its output contacts, the clock DVTG above the empty potential well of the vertical CCD is Before the charge is transferred to the empty potential well, the above-mentioned empty potential well is changed from the shallow potential VL to the deep potential VH. As a result, 1 EZB transfer operation is very stable.
  • the odd (even) clock transfer electrode and the even (odd) clock transfer electrode can be connected directly by different shift registers or by a buffer circuit. Is driven through.
  • the clock transmitting electrode is connected to one output contact per transfer stage of the & shift register. In this way, the vertical clock voltage required for 1EB transfer or 2EZB transfer can be generated.
  • shift registers having a small number of transfer stages can be arranged on both sides of the imaging area, the vertical dimension of one transfer stage of the shift register can be doubled. Then, the clock power frequency of each shift register can be reduced.
  • each clock DVTG is connected to a one-phase or two-phase clock power supply via a switch in sequence.
  • the above-mentioned sequential switch is a switch that operates sequentially from the downstream side.
  • This EZB transfer sensor is called a clock line driven 1 E / B transfer sensor-and the EZB transfer sensor in claim 9 is called a shift register driven EB transfer sensor.
  • two adjacent clocks of the vertical CCD, DVTG are each connected to the first, second, and second phase clock power supplies via sequential switches, and The switches operate simultaneously. In this way, the number of transfer stages of the shift register for sequentially driving the switches can be reduced to half of the vertical CCD DVTGG. In addition, the operation of the switch can be performed easily.
  • a predetermined potential is applied to each clock transfer electrode before performing vertical transfer. You. Then, each clock transfer electrode is cut off from the power supply line, and thereafter connected to the clock power supply via the switch in order. This makes it very easy to control the potential of the clock transfer electrode (clock DVTG or clock NDVTG).
  • the vertical CCI] clock DVTG is sequentially connected to the clock power supply line via a switch.
  • a CIEB transfer sensor is called a clock line drive 1 ⁇ /// transfer sensor. In this 1 ⁇ . / ⁇ transfer sensor, all clock DVTGs have a deep potential V ⁇ before performing vertical transfer.
  • the CI EZB feed sensor connected to the clock power line is called the clock line driven 2 EZB transfer sensor.
  • the odd (even) clock NDVT G becomes the deep potential VH
  • the even (odd) clock ND VTG becomes the shallow potential.
  • VL the voltage waveform of the vertical transfer port of the clock line drive 2 EZB transfer sensor and the J voltage voltage become complicated.
  • the clock-line driven E / B transfer sensor has the ability to increase the output resistance of the shift register compared to the shift register-driven E / B transfer sensor disclosed in claim 9, but instead uses a channel resistance, which is a transmission switch and has a smaller sequential switch.
  • the initial potential setting of the clock transfer electrodes performed before the above vertical transfer is performed by connecting each of the block transfer electrodes to the reset power supply line via a dedicated reset switch.
  • the readout voltage VR can be applied to the fixed clock transfer electrode by the circuit means for resetting and / or resetting the clock transfer electrode.
  • the initial potential setting of the clock transfer electrode is performed before performing the above vertical transfer, and the vertical transfer is sequentially connected to each clock transfer electrode via a switch. This is performed by the clock power supply line.
  • all necessary sequential switches are all turned on by the shift register.
  • the potential setting technology of the present invention is also applied to the transfer of signal charges from pixels to vertical CCDs by applying a read voltage VR to the required black transfer electrode in the common tiller electrode IT sensor. it can. That is, the necessary sequential switches may be turned on, and the read voltage VR may be applied to a predetermined clock line. According to the present invention, since each clock transfer electrode need only be connected to the clock line via a sequential switch controlled by the shift register, the circuit structure and the vertical transfer clock operation are simplified.
  • a vertical CCD A shift register that applies a clock voltage to the clock transfer electrode directly or through a buffer circuit, or a shift register that turns on the above-mentioned sequential switches in order is disposed on both sides of the imaging unit.
  • the odd (even) clock transfer electrodes are connected directly or indirectly to a shift register located on the left or via a sequential switch controlled by the shift register described above. Connected to the clock line.
  • the right shift register controls the even (odd) number clock transfer electrodes. This makes the shift register design easier.
  • one vertical scan line driving one row of clock transfer electrodes of each vertical CCD is driven from both sides.
  • the above one vertical scanning line may be divided. In this way, the size of the switch or shift register or the buffer circuit can be reduced.
  • signal charge is output from all pixels during one field period, and signal charge output from odd (even) numbered pixels. Can be displayed. In this way, afterimages in the field can be reduced, and the dynamic range can be improved. Of course, it is also possible to take into account all the signal charges output at low illuminance.
  • the frame accumulation operation may be performed at low illuminance and the field accumulation operation may be performed at high illuminance.
  • this switching of the storage operation involves applying a read voltage V R to half or all of the clock transfer electrodes before starting the vertical transfer operation.
  • the vertical CCD has one potential well per pixel, and alternately stores signal charges and noise charges of odd (even) pixel rows in the above potential wells. And independently transfer the signal charge and the noise charge. Can do things. S / N ratio of the thus them if signal charges can be improved the S / N ratio particularly dark current and Sumeanoi _'s.
  • the noise charge remaining in the vertical CCD is cleared or relocated.
  • the smear noise charges of the adjacent signal charge well and the noise charge well become substantially equal, so that the smear noise can be removed by subtracting the voltages output from the two potential wells.
  • the above clearing can be performed by high-speed tilling of the vertical CCD during the vertical retrace or by transferring the residual noise charge to the drain adjacent to the vertical CCD. That is, in the CIE / B transfer sensor of the present invention, the potential well is substantially halved at the end of the vertical transfer, and as a result, the residual noise charge is transferred to the odd (even) number potential well at the next vertical transfer. Only exists. Thus, by removing or relocating this residual noise charge, and subtracting the output signals of two adjacent potential wells, the smear noise and residual noise charge can be removed.
  • the smear noise charge mixed into the signal charge is substantially constant .. Therefore, one pixel row (or saturated pixel) is provided during the vertical retrace period. The smear noise is significantly reduced by recording the smear noise charge of (1 'pixel row in the column) and subtracting the smear noise charge from the above-mentioned charge.
  • a vertical CCD of a CIEB vehicle transport sensor in which a vertical CC has one potential well per pixel and outputs signal charges of all pixels in one vertical transfer period, an odd (even) number CCD holding residual noise charge is provided. Potential wells and even-numbered potential wells that do not retain residual noise charge have significantly different smears charges. Therefore clay There was a drawback in that a vertical CCD per element had to have two potential wells, as shown in FIG. Also, in the conventional technology in which the smearing of one pixel row is stored and subtracted from the signal of each pixel row output later, if the smearing is large, the pixel receives strong light and generates a saturated signal charge and is output from a pixel (saturated pixel).
  • the present invention aims to remedy the above problems.
  • the present invention stores at least one pixel row of a saturated pixel column, and reads the above signal from signals generated from some pixels of the saturated pixel column. It is characterized in that the subtracted smears are subtracted, and the above-mentioned recorded smears are not subtracted from signals generated from other pixels of the saturated pixel sequence. This makes it possible to create a CIEZB transfer sensor that can output signal charges from all pixels in one field period. And it is possible to make a CCD area sensor whose maximum signal voltage does not decrease.
  • the smeared charges are mixed into the above potential well mainly when the potential well passes below or under a saturated pixel receiving strong light. Therefore, the recorded smear noise is subtracted from the signal generated from the potential bowl passing under or beside the saturated pixel, and the above-mentioned smear noise is subtracted from the signal generated from the other potential well of the saturated pixel column. Special features are not available.
  • the above stored memory noise is not subtracted from the signal generated from the saturated pixel. As a result, the maximum signal voltage does not decrease.
  • the above-described smear noise is not subtracted from the symbol “ ⁇ ” which is generated from some or all of the pixels downstream of the pixel in the pixel row.
  • a vertical CCD has one potential bowl per pixel, and each potential well transfers the signal charge of the pixel if it is different.
  • CI ⁇ ⁇ ⁇ Transfer sensor (CI ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ) ) Subtracts the stored smear noise from the signal charges of the odd (even) number pixels among the pixels downstream of the saturated pixel (abbreviated as “downstream pixels”).
  • the above-mentioned stored noise is not subtracted from signals generated from pixels in a pixel row having no saturated pixel (non-saturated pixel row). In this way, random noise can be reduced. However, since the unsaturated pixel row adjacent to the saturated pixel row may have smear noise, the above-described subtraction may be performed.
  • Independent Invention 3 Claim 2 9. 'The independent noise reduction technology of Independent Invention 2 effectively reduces the noise of the EZB transfer sensor of Independent Invention 1.
  • the problem of independent invention 2 is that it requires an expensive A / D converter and DZA converter that operate in the video band. As a result, the price of the solid-state imaging device increases and becomes very disadvantageous in terms of competition.
  • the present invention is characterized in that the horizontal CCD is driven at a low speed during the vertical flyback period, and the smear noise charges transferred from the vertical CCD are output at a low speed. In this way, the cost can be significantly reduced because a low-arrest AZD converter can be used.
  • an N-bit sequential ratio AZD converter is used.
  • the AZD converter is very inexpensive compared to the video band parallel AZD converter.
  • the smears of one horizontal pixel row are AZD-converted during a period equal to about 7 horizontal scanning periods in the vertical blanking period. You.
  • the smear noise reproduced from the digital memory is D / A-converted by the DZ converter in the successive approximation AZD converter during the vertical scanning period. In this way, the DZA converter can be omitted.
  • the EZB transfer sensor disclosed in the independent invention 1 can have substantially twice the vertical pixel density as the conventional one.
  • a new problem arises when the above E / B transfer is applied to a leading type of frame transfer sensor (FT sensor). That is, a vertical CCD generally includes a bulk channel and an overlapping transfer electrode arranged above the bulk channel.
  • FT sensor leading type of frame transfer sensor
  • a vertical CCD generally includes a bulk channel and an overlapping transfer electrode arranged above the bulk channel.
  • each transfer electrode substantially constitutes one pixel.
  • the light transmittance of all transfer electrodes that generate the same color signal must be equal.
  • each of the close transfer electrodes is connected to a shift register, a buffer circuit controlled by the above shift register, or a cross switch via a sequential switch.
  • the confection vertical transfer rate depends on the charge / discharge rate of each vertical scan line, and the above charge / discharge rate is the sum of the resistance of the shift register or buffer circuit / sequential switch and the resistance of the vertical scan line, and the vertical Depends on the product of scanning line capacitance. As a result, it is very important to reduce the line resistance of the vertical scanning lines.
  • vertical CCD transfer electrodes with low line resistance generally have poor light transmittance (particularly poor blue sensitivity).
  • An object of the present invention is to improve the above question.
  • the present invention connects two adjacent transfer electrodes of a vertical CCD above the channel region of the vertical CCD or above the channel stop region between the vertical CCDs, thereby forming substantially one transfer electrode. It is characterized in that a thick film is given to the first transfer electrode of the upper self and a thin film is given to the second transfer electrode.
  • a thick film is given to the first transfer electrode of the upper self and a thin film is given to the second transfer electrode.
  • the second transfer electrode has a high line resistance.
  • the equivalent line resistance of the second transfer electrode can be reduced.
  • the above-mentioned equivalent transfer electrodes formed by two transfer electrodes have the same equivalent ratio.
  • the thickness of the second transfer electrode can be made as thin as possible. .
  • the first and second transfer electrodes are connected via a third electrode (eg, aluminum) or directly above the channel stop region.
  • a third electrode eg, aluminum
  • the low resistance first transfer electrode has a greater vertical width at the side of the channel stop region than above the channel region. In this way, the connection area is increased and the line resistance is reduced.
  • a directional transfer electrode DVT G
  • a predetermined ion can be implanted into the channel region using the first or second transfer electrode as a mask.
  • FIGS. 4, 5, and 6 disclose that a shift register (SR) driven 1 E / B transfer sensor can use a dynamic shift register (DSR). This fact is important. That is.
  • DSR dynamic shift register
  • the inventor reserves a claim regarding the EZB transfer sensor structure using DSR.
  • the EZB transfer type CCD area sensor of the present invention is suitable for a single color TV camera or a magnetic camera which independently outputs two adjacent pixels in one horizontal period. is there. This fact is important. Because the conventional single-chip CCD color TV camera has a small number of horizontal pixels, the brightness or color signal resolution was poor. Conventional C C
  • the resolution for a moving subject was poor because one frame image was composed by shooting for two field periods.
  • the present invention since two adjacent pixel rows can be output independently during one horizontal scanning period, this problem is solved.
  • methods such as increasing the number of horizontal transfer stages of the vertical CCD to two or doubling the number of vertical CCDs have been implemented. ⁇
  • two adjacent pixel rows these methods leads to bad results in the structure and fabricating process and S New ratio
  • the inventor reserves a complaint regarding the EZB transfer CCD area sensor that performs the ZH output operation.
  • the conventional EZ B transfer is an N-phase clock transfer method in which each clock voltage is substantially symmetrical. Since the addition of N is inversely proportional to the transfer speed, signals of one pixel row or more in one horizontal blanking period It could not be used for vertical CCD of CCD area sensor which needs to output electric charge.
  • the CI EZB transfer method of the present invention is the same as the conventional EZB transfer method in using a very large number of clock phases, but the above-described clock and signal are output until the signal charge of the first half pixel row of the CCD is output.
  • the voltage is an asymmetrical clock voltage, and subsequently, a one-, two-, or four-phase clock voltage is used.
  • the CCD signal charges that are input all at once before transfer are output in order. Therefore, the CI EZB transfer method of the present invention can also be applied to an SPS type CCD structure output CCD or CCD line sensor.
  • a vertical CCD having the same number of VTGs can secure twice the number of vertical pixels as compared with the conventional case.
  • 0 directivity 0
  • PB potential barrier
  • PW potential well
  • NDVTG non-directional VTG
  • the CI EZB transfer method of the present invention using DVTG is called 1 EZB transfer, and that using NDVT G is called 2 ENO B transfer.
  • the shallow potential VL is a potential that does not accumulate signal charges
  • the deep potential VH is a potential that accumulates signal charges. That is, in an N-channel CCD, the shallow potential VL is a more negative clock voltage, and the deep potential VH is a more positive clock voltage.
  • the present invention relates to an IT sensor It can be used for the vertical CCD of an interline transfer area sensor or a full frame transfer type FT sensor (frame transfer area sensor), but a normal FT sensor with a buffer CCD (accumulated CCD) between the vertical CCD and the horizontal G CD It can be applied to vertical CCDs.
  • Independent invention 2 (claim 25) is extremely effective in suppressing the unique smear noise pattern of independent invention 1 (claim 1) .By using both together, an area sensor having a large dynamic range and a small smear noise is manufactured. it can.
  • Independent invention 3 (claim 29) is a drawback of independent invention 2 because it suppresses the complexity of the circuit and increases the cost, so that by implementing independent inventions 1, 2, and 3 together, A high area sensor can be manufactured.
  • Independent Invention 1 1 When manufacturing an EZB transfer type FT sensor using the conventional two-layer electrode technology, the pixel sensitivity of odd (even) rows is different from the pixel sensitivity of even rows, resulting in large pattern noise.
  • Independent Investigation 1 (Claim 3 2), the above-mentioned disadvantages can be improved and a FT sensor with good performance can be manufactured.
  • FIG. 1 and FIG. 2 are block circuit diagrams of an embodiment of the continuous injection E / B transfer sensor disclosed in the independent invention 1.
  • vertical scanning lines 3 arranged in the imaging area 1 in the horizontal direction are driven by shift registers (abbreviated to VSRs) 2 A and 2 B that generate a vertical transfer cut-off voltage.
  • VSRs shift registers
  • the question of the shift register and a vertical scanning line, so that you can place Batsufuainba one motor current amplification is of course, less Te smell, c vertical for explaining an embodiment of driving directly the vertical scanning lines 3 by shift.
  • Torejisuta Since Run 3 is generally integrated with the vertical G CD transfer electrode, The same sign.
  • FIG. 1 and FIG. 2 are block circuit diagrams of an embodiment of the continuous injection E / B transfer sensor disclosed in the independent invention 1.
  • VSRs shift registers
  • each vertical scanning line 3 is driven by shift registers 2A and 2B, so that its charging and discharging become faster.
  • 2A and 2B operate the same. 3 may be divided in half.
  • the horizontal CCD 5A is connected to the vertical CCD or buffer CCD by the transfer electrode 4A.
  • the horizontal CCD 5B is connected to the horizontal CCD 5A by the transfer electrode 4B.
  • the odd (even) th vertical scanning line 3A is connected to the output contact of the shift register 2A, respectively, and the even (odd) vertical scanning line 3B is connected to the output contact of the shift register 2B. Connected to each other.
  • the pixel, the buffer CCD, and the vertical CCD are omitted. In FIG.
  • FIG. 3B 3Z has a deep potential VH and 3Y has a shallow potential VL. And Q 2 is tilled below 3 Z.
  • Figure 3C 37, and 3 become shallow potential, 3Y and 4A become deep potential VH, Q2 is transferred to horizontal CCD 5A, and Q3 is transferred below 3Y.
  • FIG. 3 F operation from Figure 3 D is is the vertical transfer independently. Vertical scan line 3 (A to Z) is connected to each output contact of shift register 2A.
  • the above vertical transfer can be performed by alternately injecting the transfer pulse information, the shallow potential VL and the deep potential VH, from the input terminal 2C of the shift register 2A. It is understood.
  • Fig. 3 (A to F) it is understood that the next empty PW is injected every time the empty potential well (PW) represented by 0 is reversely transferred by 2 PW pitches.
  • FIG. 4 (A to F) illustrates one EZB transfer operation having the structure of FIG. Figure 4 (A to F) has the same operational state as Figure 3 (A to F). However, in Fig. 4 (A to F), shift registers 2A and 2B alternately have a deep potential VI-I.
  • the above operation of 2A and 2B can be easily made by making the output inverter of the shift register a dynamic type, especially a ratioless type.
  • the charging operation of one shift register preferably begins earlier than the evaluation (discharge) operation of the other shift register.
  • the clock operation shown in FIG. 3 (A to F) and FIG. 4 (A to F) is also possible in the embodiment using the dynamic type, especially the ratio type buffer inverter.
  • the charging operation of the inverter is a quick operation that applies a deep potential VH to its output contact
  • the discharging operation is a clock operation that applies a shallow potential VL to its output contact. It can be seen that the 1 E / Bg transmission of the present invention can be implemented by a very simple mouth and speed operation.
  • FIG. 5 is an equivalent circuit diagram of one embodiment of the shift register of FIG.
  • the shift register in Fig. 3 can also have basically the same structure as in Fig. 5.
  • the vertical scanning lines 3Z, 3Y and 3X are the output of the shift register 2 2.2 ⁇ and the output of the inverter 11 1.
  • 1 1 A is the charging switch This is a dynamic inverter with 8 A switch, 9 A evaluation switch and 1, 0 A discharge switch.
  • connection inverter 11B for connecting the binary output inverter has a discharge switch 10B, an evaluation switch 9B, and a charge switch 8B. 11A and 11B are alternately connected by connection switches 7A and 7B.
  • FIG. 6 is an operation diagram of one embodiment of the two-phase shift registers 2A and 2B of FIG.
  • 14 is an operation diagram of 2 A
  • 14 ′ is an operation diagram of 2 B.
  • the clock voltages V ⁇ and V 2 ′ are applied to 2 B, and the clock voltages V 1 and V 2 are applied to 2 A.
  • 14 P indicates the charge state of the output contact 12 1
  • H indicates the hold state
  • E indicates the evaluation (discharge) state.
  • P 'of 14' indicates the state of charge of the output contact 12 'of 2B
  • H' indicates the holding state
  • E ' indicates the evaluation state.
  • the operation of the MOS two-phase shift register is well known and will not be described in detail.
  • E operates later than P '
  • E' operates later than P.
  • FIG. 6 by arranging P. ⁇ , ⁇ during one horizontal retrace period, signal charges of one pixel row can be transferred to the horizontal CCD.
  • FIG. 5 by blocking 1 OA and conducting 8 A, a deep potential VH can be applied to each DVTG.
  • FIG. 7 shows an embodiment in which the vertical scanning line 3Z is connected to the output contact of the buffer inverter 15 driven by the shift register 2A.
  • the transfer lock shown in FIG. 3 (A to F) and FIG. 4 (A to F) is generated by the dynamic disconnector 15. For example, in FIG. 6, the charge switch 15 A conducts and the discharge switch 15 C shuts off during the P period. During the H period, 15 A and 15 C cut off.
  • FIG. 8 shows a modification of FIG. 7.
  • the connection switch 16 operates in the same manner as the discharge switch i 5 C of FIG.
  • FIG. 9 is an operation diagram for explaining the frame 10, and is an operation diagram of the shift register 2A of the 2E./Bfe transmission sensor having the structure of FIG. Shift register 2A is configured by alternately connecting output inverters 11 1 and output inverters 11B. And vertical running Line 3 (from Z to W) is connected to the output contacts 12 A and 12 B of each output inverter.
  • the output contacts of the two-phase shift register 2A change as shown in Fig.
  • FIG. 10 (A to H) is an operation diagram showing a 2EZB transfer sensor having the structure of FIG.
  • shift registers 2A and 2B drives ND VTG 3 (Z, X, V), and 2B drives ND VTG 3 (Y, W, U).
  • the signal charges Q 1, Q 2, and Q 3 can be transferred independently by alternately applying a pulse operation to 2 A and 2 B.
  • shift registers 11A and 11B can be constituted by two-phase static shift registers. Of course, the use of four shift registers is also possible.
  • inverters 11 and 11B alternately perform evaluation (discharge) operation E and hold operation H. Therefore, shift register 2A has a two-phase dynamics (especially ratio) format. You can do it.
  • Figure 10 illustrates two-phase dynamics (especially ratio) format. You can do it.
  • Shift register 2A that drives the odd (even) ND VTG of A (H) and shift register 2B that drives the even (odd) ND VTG Since the holding operation H and the evaluation operation E are performed alternately, a dynamic (particularly ratio) shift register can be used.
  • 2 B are shift register comprises a mosquito inverter output ratioless form, c can be configured, however, the vertical scanning line potential change of the output contacts of the charging operation period P To prevent transmission, the switch connecting the shift register and the vertical scan line during the charging period P is shut off.
  • Figure 11A (A to C) is an operation diagram showing the residual charge QNR of the 1 E / B transfer IT sensor.
  • each potential well 3 ( ⁇ 'to S ') Is in the state of Fig. 11A. That is, the residual charges QN'R (1 to 4) are accumulated in PW3Z ', 3X'.3V', and 3T ', respectively.
  • QNR 4 are vertically transferred by 1 PW pitch. This vertical tilling is performed by applying a deep potential VH to PW3Y ', 3W', 3U ', 3S, and a shallow potential VL to PW3X', 3T '. . In this clock operation, for example, in FIG.
  • FIG. 11C shows the above state.
  • Fig. I1 (D to F) is an operation diagram illustrating the use of the above-described smear noise subtraction technique for the 2EZB transfer sensor.
  • Figure 11D shows the arrangement of the first residual charge during the vertical retrace period.
  • FIG. 11E shows a state in which the odd (even) -numbered residual charges are transferred by the i potential well (PW) pitch.
  • FIG. 11F shows a state in which signal charges 1., Q 2, and Q 3 are transferred from the pixel to the potential wells 3 Z ′ .3 V ′ and 3 R ′ of the vertical CCD 6.
  • the basic operation is the same as the above 1 EZB transfer IT sensor.
  • the residual charge is drained from the vertical CCD 6 during the vertical retrace period, and the charge of the two adjacent potential wells is subtracted. May be.
  • FIG. 12 is a cross-sectional view of one embodiment showing the intermediate potential 1 transfer sensor disclosed in claim 5.
  • New tau form the substrate (4 X 1 0 4] ⁇ atom / CC) 2 0 P-type Ueru region (2 X on the 1 0 [15] atom CC 32 is created.
  • ⁇ indicates the exponential term.
  • an N-type bulk channel region (1 X 10 [16] atom ZCC) 22 is created. Boron ions are implanted into a part of the surface of the region 22 to form a potential barrier region 3.
  • a DVT G 37 A.37 B is formed on the surface of the region 22 via the insulating film 36.
  • the N T DVTG 3 5 with a DC voltage on the ⁇ to two D VT G 3 7 A, 3 7 intermediate Chiyan'ne Le regions 2 2 A during B is made.
  • FIG. 13 is a channel potential diagram of FIG. An intermediate potential VM is applied to the intermediate channel region 22A.
  • the unclocked ND VTG 35 can be very thin, thus improving the blue sensitivity of the 1E ZB transfer FT sensor.
  • the potential barrier region is formed by implanting polon ions on the surface of the intermediate channel region 22 A, the above-mentioned ND VTG 35 can be omitted. Its sensitivity is further improved. Ion implantation into the surface of the intermediate channel region 22 A and ion implantation into the potential barrier region below the DVTG can be performed by the same process.
  • the shift register driving EZB transfer sensor of the present invention can be used for vertical transfer between the FT sensor and IT sensor, and the above vertical transfer implements a non-interlaced output method or a two-pixel line reading interlace output method. It is understood that is possible. In addition, it is possible to switch between interlaced non-interlaced systems, and to switch between frame storage mode and Z-field storage mode.
  • One-pixel row reading and interlacing in which one or both of the ftCCDs are used to transfer signal charges in one pixel row, are also possible. It is also possible to perform 2-pixel line reading and interlacing when the smearing is small, and use the low noise technology of claims 2-3 and 24 when the smearing is large.
  • FIG. 14 is an equivalent circuit of the first embodiment to explain the clock line drive 1 EZ B transfer sensor
  • FIG. 15 is a clock line 2 ⁇ ′
  • FIG. 7 is a waveform diagram of two-phase clock voltages V 1 and V 2 applied to the channel 2.
  • Fig. 14, Fig. 1
  • Reference numeral 5 denotes a drive circuit for a black line drive 1 ⁇ / ⁇ transfer sensor.
  • the vertical scanning line 3 ( ⁇ to V) connected to the vertical CCD DVTG is connected to the clock lines 2 ⁇ and 2 ⁇ by the switches 16 (V to ⁇ ) sequentially.
  • the switches By inputting the transfer pulse information to the input terminal 2X of the shift register 2, the switches are sequentially turned on in order from 16Z, 16Y.
  • the T1 period is a non-transfer period, and signal charges are accumulated in each potential well of the vertical CCD.
  • V1 has a shallow potential V
  • V2 has a deep potential VH.
  • 16- ⁇ , ⁇ 6 ⁇ conducts, and is transferred to horizontal CCD 5 A via Q 1. Transit 4 ⁇ .
  • V2 becomes a deep potential VH.
  • V1 becomes the deep potential VH
  • V2 becomes the shallow potential V.
  • Q2 is transferred from below DVTGG3Y to below DVTG3Z.
  • V 1 and V 2 become the deep potential VH.
  • V1 becomes the shallow potential VL
  • V2 becomes the deep potential VH.
  • 16W.16X conducts.
  • Q 3 is transferred from below DVT G 3 X to below DVT G 3 Y.
  • V2 becomes a deep potential VH.
  • V1 is deep potential VH
  • V2 is shallow potential during t7 period Becomes VL.
  • V1 becomes the deep potential VH
  • V2 becomes the shallow potential VL
  • Q3,04 ⁇ 1 DVT G pitch one potential well pitch
  • V2 becomes a deep potential VH. Then, 16 U and 16 V conduct. As a result, Q4, Q5 and Q6 are transferred by one DVTG pitch. In this way, continuous injection type 1 EZB tilling can be performed very easily.
  • the ability to simultaneously apply (change) the clock pulse voltage V1 and sequentially turn on the switches during the periods L1, t5, and t9 greatly simplifies the transfer operation. Furthermore, the ability to conduct two adjacent switches at the same time greatly simplifies the transfer operation and reduces the size of the shift register.
  • T 1 is a vertical retrace interval
  • t 1 to t 4 are arranged within one horizontal retrace interval.
  • FIG. 17 is a cross-sectional view of one embodiment illustrating the intermediate potential type IEZB transfer sensor disclosed in claim 6.
  • FIG. 17 is basically the same as FIG. However, a potential barrier region 34 is added below the DC electrode 35 by ion implantation, so that an intermediate potential barrier region 22C and an intermediate potential well region 22B are formed in the intermediate channel region.
  • This CCD structure is known as a one-phase CCD.
  • FIG. 18 is a potential diagram of FIG.
  • FIG. 19 is a modified embodiment of FIG.
  • FIG. 20 is the potential diagram of FIG. Fig. 21 shows the driving circuit of a 1 / E / B transfer sensor with a CCD having the CCD structure shown in Figs. 17 and 19.
  • FIG. 22 is connected to the clock line 2Y of FIG. Fig. 22 shows the clock of Fig. 21.
  • FIG. 6 is a waveform diagram of a clock voltage V1 applied to a clock line 2Y. This is basically the same as FIG. In the non-transfer period ⁇ 1, the intermediate potential VM is applied to all the D VTGs, and the potential well P WV below the DVTG and the potential well PWM in the intermediate channel region have the intermediate potential VM ′. Then, charges are accumulated or transferred to all potential wells of the vertical CCD.
  • FIG. 23 shows the operation of the vertical D6 of the clock line drive type 1 EB transfer sensor of FIGS. 21 and 22.
  • DC transfer electrodes 3Y.3W, 3U are arranged between DVT G3Z, 3X, 3V, 3T, and electric charges Q1 to Q7 are stored under them. Since all sequential switches conduct during T1, the intermediate potential VM can be applied to D VTG by 2Y as in Figs. 14, 15, and 16. In the IT sensor, a deep potential VH or a read potential VR may be applied. Then, at the end of the T 1 period, all sequential switches are turned off, and each DVTG with VM has a floating potential.
  • Figure 23A illustrates this situation.
  • FIG. 23B shows the state during the period t1, V1 becomes the shallow potential VL, I6Z conducts, and Q1 is fed to the horizontal CCD 5A via 4A.
  • Figure 23C shows the state during t2, V1 goes to deep potential VH, and Q2 is transferred from below 3Y to below 3Z.
  • Figure 23D shows the state during the t3 period, V1 becomes the shallow potential VL, and Q2 is transferred to 5A.
  • Figure 23E shows the state during the t4 period, V1 becomes the shallow potential VL, and 16X becomes conductive. As a result, Q 3 is transferred from below 3 X to below 3 Y.
  • FIG. 23F shows the state during period t5, where V 1 is at the deep potential VH, and Q 3 and Q 4 are transferred by one potential well pitch.
  • FIG. 23G to FIG. 23L show the state from the period t6 to the period tl1.
  • the vertical CCD outputs one row of signal charges during the periods t2, t3 ', and t4, and outputs the next one row of signal charges during the periods t5, t6, and t7.
  • This transfer method has the feature of being very simple. It is a great advantage that the charge of one potential well can be transferred by one potential well pitch by sequentially turning on the switch one value during 1: 4, t7 and t10 periods. Then, the structures of Fig. 17 and Fig. 19 improve the blue sensitivity of the FT sensor.
  • the intermediate DC transfer electrode 35 can be made very thin.
  • solid-state imaging device 1 A Is assumed to be an IT sensor that outputs one pixel row during one horizontal scan period by the conventional two-phase clock transfer method.
  • the IT sensor 1A has an imaging area 1 and a horizontal CCD 5. The description of the pixel column and the vertical CCD is omitted.
  • the signal charge QS output from the horizontal CCD 5 during the vertical scanning period is converted into a signal voltage VS by the amplifier 92, and the VS is input to the comparator 93 and the subtraction circuit 100.
  • the smearing charge QNS output from the horizontal CCD 5 during the vertical retrace period is converted to a smearing voltage VNS at 92, and the VNS is stored in the digital memory 97 via the AZD converter 96. At least a smear noise voltage for one pixel row for a saturated pixel column is stored, but a smear noise voltage for one pixel row or more for all pixel columns may be stored.
  • the digital memory 97 sends the scan voltage VNS to the switch circuit 99 via the DZA converter 98.
  • the switch circuit 990 transmits the smearing voltage VNS output from the D / A converter 98 to the arithmetic circuit 100 under specific conditions.
  • the smear noise voltage is not subtracted from the signal voltage generated from 91 A.
  • the signal voltage of 91 A does not decrease.
  • the smear noise voltage is not subtracted from the signal voltage generated from the unsaturated pixel column 91F. As a result, the random noise of the signal voltage of 91 F is reduced.
  • the smear noise voltage is not calculated from the signal charge generated from the downstream region 91C.
  • the result No charge The signal charge of 9 1 C has no negative smear.
  • the specific operation will be described below.
  • the signal voltage VS output from the comparator 92 is compared with the saturation signal voltage VS max by the comparator 93. 93 outputs 0 when VSVS max. 93 sends a logical signal VC to AND circuits 95A and 95E and an inverter 95B.
  • 95 A sends the AND signal of the output signal VM of the line memory 94 and the output signal VC of 93 to the line memory 94.
  • the line memory 94 is driven in synchronization with the horizontal CCD 5.
  • the line memory 94 outputs 0 for the signal voltages in the areas 91 A and 9.1 B.
  • Inverter 95B outputs 1 only for the signal voltage in area 91A. Therefore, the NOR circuit 95C receiving logic signals from 94 and 95B outputs 0 to the OR circuit 95D only for the signal voltage in the region 91B.
  • the switch circuit 99 controlled by 95D sends the screen noise reproduced from 7 to the arithmetic circuit 100 only for the signal voltage of the upstream area 91B. That is, the smear noise voltage is subtracted only from the signal voltage in the region 91B.
  • each of the memory cells in line memory 94 is reset to one. The circuit shown in Fig.
  • the solid-state imaging device 1A is an EZB tiller-type IT sensor and the residual charge of the vertical CCD is cleared during the vertical retrace period.
  • the downstream region 9 The odd (even) -th potential well P of 1 C has a residual charge, and the even (odd:)-th potential well has no residual charge. Therefore, the lock VX input to the AND circuit 95 may be set to 1 when the signal charge of the odd (even) th potential well is output.
  • the switch circuit 99 becomes conductive, and the subtraction circuit i 00 substantially performs the subtraction, and the smear noise of 91 C is canceled. Since the signal VC is input to the AND circuit 95E, the switch circuit 99 is cut off when the signal voltage of the area 91A is output. In the above-described embodiment in which two pixel rows are independently output during one horizontal scanning period, a 2 f horizontal CCD is generally used. Therefore, the symbol voltage of the two horizontal CCDs output from the area 91 C is used. Of which, horizontal C including residual charge It is also possible to design the switch circuit 99 and the AND circuit 95E so that the scan voltage is subtracted from the CD signal voltage. In order to compensate for the delay of the control signal by the logic circuit of FIG.
  • FIG. 25 is a block diagram of a block diagram of an embodiment of the independent invention 3 of the successive approximation ratio AZD converter.
  • the SMNS output EVNS output from the amplifier 92 in FIG. 24 is compared with the reference voltage VRX by the comparator 102.
  • the output signal of 102 is input to the serial ratio register 103, and the output signal of 103 is sent to the D / A converter 105 via the switching circuit 104.
  • the output signal of the DZA converter 105 is fed back to the comparator 102 via the switching circuit 101.
  • Circuits 101 and 104 when used as AZD converters, connect 108 and 107 and connect 109 to I10. Then, when used as a DZA converter, 108 and 105 are connected, and 112 and 110 are connected.
  • 97 is a digital memory. Send the signal voltage to 102.
  • the horizontal CC outputs one pixel of smearing charge during about 7 horizontal scanning periods.
  • the successive ratio type A-ZD converter shown in Fig. 25 produces a 6-bit digital signal.
  • FIG. 24 is a cross-sectional view of one embodiment showing the independent invention 4.
  • a P-type well region (2 ⁇ 10 [15] atoms ZC C) 32 is arranged on an N-type substrate (4 ⁇ 10 ⁇ 14 ⁇ atoms / CC) 20 .
  • An N-type bulk channel region (10 [1 6 ⁇ atoms / CC) 22 is disposed thereon. Polon ions are implanted into the surface of the first region 22 A of the N-type bulk channel region 22 to form a potential barrier region 3.
  • the channel region 22B other than the potential barrier region 34 is a potential well region.
  • a P-type channel stop region (4 X 10 M 7] atom CC) 23 is created.
  • a silicon oxide film 36 C and a silicon nitride film 36 ⁇ are formed on the surfaces of the regions 22 and 23.
  • a second transfer electrode 37 ( ⁇ , ⁇ , C) of about 1 micron is formed on this by the doped silicon.
  • the above-mentioned second transfer electrode has a branch electrode 37 X extending vertically above the channel stop region 23. Then, the second transfer electrode is oxidized to form a silicon oxide film 36 ⁇ on the surface thereof. Then, the oxide film on the branch electrode 37X is etched, and the branch electrode 37X is exposed. Then, a first transfer electrode 35 (A, B, C) having a thickness of about 0.6 ⁇ m is formed by the polysilicon doped with phosphorus. The first transfer electrode is connected to the first transfer electrode on the exposed surface and side surface of the branch transfer electrode 37X.
  • FIG. 27 is a cross-sectional view in a direction perpendicular to FIG. 26, and FIG. 28 is a plan view of one embodiment of FIGS. 25 and 26. The description of the above embodiment is added below.
  • an output inverter of an odd (even) number feed stage and an output inverter of an even (odd) number transfer stage alternately perform a charge operation and a logic discharge (evaluation) operation alternately.
  • the shift register may be designed so that the charging operation of one of the output converters always precedes the evaluation operation of the other.
  • This 1 shift register driven 1 E / B transfer area sensor requires one transfer stage (two inverters) of shift register per DVTG of vertical CCD, and thus has the disadvantage that the vertical pixel row pitch cannot be reduced.
  • the output inverter of the shift register 2A can have a ratioless dynamic structure, which saves power consumption and eliminates the manufacturing process compared to the CMOS shift register of the 2E / B transfer area sensor. become.
  • the output inverter of the CMOS shift register consumes a considerable amount of transient current. Furthermore, during the precharge period P of the above-mentioned ratio output inverter, the next evaluation (discharge) operation is performed after the vertical scanning line having the shallow potential VL is charged again to the deep potential VH. Becomes stable.
  • the structure of the above-mentioned ratio dynamic shift register is basically the same as the shift register 2A or 2B in FIG. 5, and each output contact 12A of the shift register is sequentially connected to each vertical scanning line. .
  • the output voltage from each transfer stage of the 1st shift register is the odd voltage of the vertical CCD.
  • the clock voltage output from each transfer stage of the second shift register is applied to the (even) th clock DVTG, and the even (odd) clock DVTG of the vertical CCD.
  • one transfer stage is composed of two inverters in a two-phase shift register, and the clock voltage is output from the output contact of one of the inverters (called the output inverter 1).
  • the above two shift registers are dynamic shift registers in which the output inverter alternately performs a charging operation, a holding operation, and a discharging operation.
  • the output inverter is preferably a ratio inverter capable of reducing the output resistance.
  • each output contact of the first and second shift registers outputs VH first.
  • the output inverters of the first and second shift registers alternately perform charging and evaluation operations.
  • the charging operation of the output inverter of one shift register always precedes the evaluation operation of the output inverter of the other shift register.
  • a shallow potential from the input terminal 2 C of each shift register VL is input in order.
  • This 2-shift register driven 1E ZB transfer area sensor has high integration, low power consumption and simple manufacturing process. (Additional explanation for Fig. 9)
  • This 1 shift register drive type 2 E / B transfer sensor outputs the clock voltage output from the 1 /-transfer stage of the 2-phase shift register, that is, the clock voltage output from the output contact of each inverter. Is applied to each clock ND V TG of the vertical CCD. The odd (even) output contacts of the shift register output VL first, and the even output contacts output VH.
  • VL and VH are alternately input from the input terminals of the shift register, and the odd (even) -numbered inverter 11A and the even (odd) -numbered inverter 11B of the shift register are alternately logically connected.
  • the discharging operation and the holding operation are performed.
  • Each inverter of this shift register performs a logical discharge operation and a holding operation, and is preferably a static inverter (especially CMOS) which does not require a charging operation.
  • the odd (even) clock ND VTG of the vertical CCD is the first shift.
  • the clock voltage output from each transfer stage of the register is applied.
  • the even (f) -th clock NDVT.G is applied with the clock voltage output from each transfer stage of the second shift register.
  • one transfer stage is composed of, for example, two inverters in a two-phase shift register.
  • each transfer stage of the I shift register outputs VL
  • each transfer stage of the second shift register outputs V ⁇ .
  • the output inverters of the first and second shift registers perform the holding operation and the discharging operation alternately.
  • FIG. 16 A to L
  • Fig. 16 (A to L) explains the vertical tilling operation of the two-clock-line-driven 1 EZB transfer sensor in Figs. 14 and 15 .
  • Shift register 2 has one output contact per transfer stage, and is preferably a two-phase shift register.
  • each output contact of the shift register 2 outputs VH, all the sequential switches 16 (Z to V) conduct, and the clock lines 27 and 2 Y 'become VH, and each vertical switch becomes VH.
  • Scan line 3 (from Z to V) becomes VH, and signal charges Q1 to Q5 are accumulated under each clock DVTG 3 (from Z to V).
  • the read electrodes VR are applied to the clock lines 2Z 'and 2Y' during the period T1.
  • each output contact of the shift register becomes VL, and each sequential switch 16 (from Z to V) is shut off.
  • Shift register 2 has i output contacts per transfer stage. Then, during the T1 period before the vertical transfer is performed, each output contact of the shift register 2 becomes VH, each switch 16 (Z, X, VT) is sequentially turned on, and the clock line 2 2 is connected to the intermediate potential VM. become. Then, as explained in Fig. 23 ⁇ , each signal charge Q1 to Q7 is arranged between the potential bowl door under each clock D VTG (3Z, 3X.3V, 3T) and between them. Is accumulated in the intermediate DC potential well.
  • clock line 2Y goes to VL, and each clock DV TG goes to VL. Thereafter, each output contact of the shift register goes to VL, and each switch is turned off sequentially.
  • the charge switch of the output inverter of the shift register should be made conductive, and the potential of the vertical scanning line should be controlled via the above-mentioned charge switch.
  • FIG. 5 Another mode of operation of the shift register of FIG. 5 is described with reference to FIG. P is the period during which the charge switch 8A or 8B conducts and the discharge switches 10A, 10B are shut off, and E is the period during which the charge switch is shut off and the discharge switch conducts.
  • the retention period is the period during which the charge and discharge switches are cut off.
  • the preceding connection switches 7A and 7B conduct during the charging period P to input the logic information, but these can be implemented separately.
  • the feature of this embodiment is that the output inverter 11 A operates in the order of P, ⁇ , ⁇ , and the inverter 11 18 operates in the order of £, 11,?.
  • Shift register 2 ⁇ has a 180 ° phase difference from shift register 2 ⁇ .
  • FIG. 30 is an equivalent circuit diagram of one embodiment of the shift register of FIG. 4 (A to F) or FIG. 9 or FIG. 10 (A to L) or FIG. 14 or FIG.
  • FIG. 31 is an equivalent circuit diagram showing a modified embodiment of the two-phase ratioless dynamic shift register of FIG.
  • the principle of this well-known two-phase shift register is basically the same as that of the two-phase shift register shown in FIG. 5, and the description of its operation is omitted. If this two-phase ratio-less dynamic shift register is used without the first switch, the shift register can be made smaller and the pixel density can be improved.
  • FIG. 33 shows a block circuit of a frame transfer area sensor that drives a vertical CCD by two-shift register driving 1 EZB transfer of FIG.
  • a vertical CCD also serving as a pixel column and a horizontal CCD 5
  • a storage area 4C constituted by a buffer CCD is arranged.
  • a transfer gate 4A is arranged between the storage area 4G and the horizontal CCD 5.
  • the vertical CCD in the image section 1 transfers signal charges during the vertical blanking period by the 1 EZB transfer method described in Fig.
  • the buffer CCD of the storage unit 4C temporarily stores signal charges received from the vertical CCD.
  • the above buffer CCD is driven by shift registers 2D and 2E having the same structure as shift registers 2A and 2B. However, the shift registers 2D and 2E have the same initial state as FIG. Then, in the first half of the subsequent high-speed transfer period, the buffer CCD performs a 2 CD clock transfer. This two-phase clock transfer can be easily implemented by injecting the shallow potential VL into the shift register 2D (or 2E) and the deep potential VH into the shift register 2E (or the shift register 2D).
  • FIG. 34 is a transmission state diagram showing a part of the first half of the high-speed transfer period of the buffer CGD, and the operation proceeds from FIG.
  • 3 4 (H from E) is a transfer state diagram showing a part of a period of the second half of the high-speed transfer period of the operation is 3 4 3 4 you proceed to H n that is, the shift register from E
  • the transfer pulse information to be injected into 2D (or 2E) from the shallow potential VL to the deep potential VH in the latter half of the high-speed transfer period
  • the signal below each D VT G that composes Charge can be stored become.
  • the vertical transfer of the vertical CCD and the transfer from the buffer CCD to the horizontal CCD are the 1 E / B transfer described so far, and detailed description is omitted.
  • each DVTG (directional transfer electrode) placed on the potential wells 3Z, 3X, 3V, and 3T of the buffer CCD 6C is a two-phase CM0S shift.
  • the potential wells 3Y, 3W, 3U of the buffer CCD are driven by the two-phase CMOS shift register 2E. 2 F .2 G is its input.
  • the potential well number of the buffer CCD overlaps with that of the vertical CCD.
  • FIG. 35 is a transfer state diagram of the two-shift register drive 1 EZB-transfer FT area sensor of FIGS. 33 and 34 (A to H).
  • tO represents the first state of the vertical scanning period
  • t1 to 1: 5 represent the first half of the high-speed transfer period
  • t6 to t9 represent the second half.
  • the vertical CCD and the buffer CCD have NDVTG, and their CMOS shift registers use the one shift register two EZB transfer method disclosed in FIG.
  • the CVIOS shift register has the disadvantage that the manufacturing process is complicated, the yield is poor, and the transient current is large because a small output inverter charges and discharges a large vertical scanning line capacitance.
  • Conclusion (4) The power consumption increases, and the dark current increases due to the rise in the temperature of the sop.
  • FIG. To H can use the 2 shift register 2 E / B transfer method. That is, a vertical CCD composed of NDVTG is driven by two CM0S shift registers described in FIG. 10 ( ⁇ to H), and similarly, a buffer CCD is also composed of two CMOS shifts. Driven by an external register. Then, in the first half of the high-speed transfer period, the shallow potential VL and the deep potential VH are alternately injected from the input terminal of each shift register that drives the buffer CCD, and the buffer CCD is driven substantially by a four-phase clock.
  • the input terminal of the first shift register for driving the buffer CCD starts.
  • the shallow potential VL is injected
  • the deep potential VH is injected from the input terminal of the second shift register that drives the buffer CCD.
  • the buffer CCD outputs the signal charges to the horizontal CCD by the two-shift register driving two EZB transfer method for each horizontal scanning period in the next vertical scanning period.
  • the 2-shift register driving 2 EZB transfer accordion imager of the present invention includes two CMOS shift registers, and each shift register has an odd (even) number.
  • the invertor becomes the output inverter, and the description of the above embodiment is added below.
  • the CCD channel is N-shaped, and the shallow potential VL is, for example, 0 V, the deep potential VH is, for example, +7 V, and the 'deepest readout voltage VR is +12 V.
  • the above VL.VH.VM is the relative potential of the same part.
  • the shallow potential VL of the transfer electrode and the shallow potential VL of the potential well are different levels of potential.
  • VD in Fig. 5 is the higher power supply
  • VS is the lower power supply.
  • VLL, VLH, VM, VHL, and VHH in Figs. 12, 17, and 19 are the potentials of the respective channel regions.
  • ⁇ in FIG. 35 represents a potential well having a deep potential VH, and a potential well without a symbol is a potential well having a shallow potential VL.
  • Shift register drive 1 An embodiment using a ratioless dynamic shift register in the E / B transfer method. Reduce power consumption and simplify the process.
  • (B) Application of interline transfer CCD area sensor to vertical CCD. It improves the dynamic range of a vertical CCD and enables many applications such as smearing charge transfer.
  • (C) application to a CCD area sensor that outputs two adjacent pixel rows during one horizontal scanning period.
  • the EZB transfer method of the present invention the structure of a vertical CCD with two adjacent pixel rows and a ZH output can be extremely simplified, and a dynamic range can be secured.
  • This embodiment is particularly effective for a single color TV camera using an IT sensor or a still camera for outputting frame images.
  • D used as accordion imager 1 EZB tilling area sensor n 2 shift register drive type 1 E, ZBfe transmitter.
  • Cordion imager simplifies the manufacturing process of shift register, and Reduce its power consumption.
  • the clock line drive 1 EZB transfer accumulator-de-on-measure makes the load capacity of the shift register extremely small, making it easy to manufacture and advantageous for high-speed transfer.
  • Register drive 2 EZB ⁇ transfer accord — Deon imager has higher pixel row density than 1 shift register drive accordion demagnifier. As a result, the output inverter can be designed to be large and the input voltage of the output converter can be changed quickly, so that the transient current is small.
  • FIG. 1 is a block diagram of an embodiment of a 1-shift register driven CIE / Bfe transmission area sensor of independent invention 1 according to an embodiment.
  • vertical scanning lines 3 are arranged on both sides of an imaging area 1. It is driven by shift register 2 A.2B.
  • FIG. 2 is a block diagram of a two-shift register-driven GI EZB transfer area sensor according to an embodiment of the present invention. The odd (even) number of vertical scanning lines 3A are different from the even (odd) number of vertical scanning lines 3B. It is driven by shift registers 2A and 2B.
  • Figure 3 is a vertical transfer state diagram of a 1 shift register drive type 1 EZB transfer area sensor, in which transfer pulse information VL or VH is injected from input terminal 2-C of shift register 2A. This means that the signal charge Q (2 to 6) of the potential well 3 (U to Y) is transferred.
  • Fig. 4 is a vertical transfer state diagram of a 2-shift register driven 1 E / B transfer area sensor, in which transfer pulse information is alternately injected from the input terminals of shift registers 2A and 2B. Indicates that signal charge Q (2 to 6) of potential well 3 (U to Y) is transferred.
  • FIG. 5 is an equivalent circuit diagram of one embodiment of the shift register 2A.2B of FIG.
  • FIG. 6 is a clock voltage diagram of the shift register 2A.2B in FIG. 7 and 8 are equivalent circuit diagrams of a buffer circuit of a shift register driving type CIE ZB transfer area sensor according to an embodiment.
  • Fig. 9 is an equivalent circuit diagram of one embodiment of a 1 shift register drive type 2 EZ transmission area sensor.Each output inverter 1 1 A.1 1B of shift register 2 ⁇ output contact 1 2 ⁇ . The potential change of the vertical scanning line 3 (from W) connected to 1 2 B is also shown.
  • Figure 10 (A to H) shows 2-shift register drive type
  • FIG. 2 is a vertical transfer state diagram of the EZB transfer area sensor, showing a potential well P or a potential barrier.
  • FIG. 9 is the same as in FIG. 0 (A to H).
  • Fig. 11 (A to C) is a relocation diagram of the residual charge of the 1 EZBfe transmission IT sensor. It shows that the residual noise charge can be offset by calculating the charge of the adjacent two potential wells.
  • Fig. 11 (D to F) is a residual charge relocation diagram of the 2E / B transfer IT sensor, showing that residual noise charges can be offset by subtraction of adjacent two potential wells.
  • Figure 12 shows a non-directional transfer electrode 35 with an intermediate potential VM.
  • FIG. 5 is a cross-sectional view of one embodiment of an EZB transfer area sensor provided between the DVT G and the vertical CCD.
  • the vertical CCD is a shift register driven type 1 EB transfer technology described above or a cross-sectional view described later. 'Sound line drive type 1 Transferred by EZB transfer technology.
  • FIG. 13 is a channel potential diagram of the vertical CCD of FIG.
  • FIG. 14 is a diagram showing one driving circuit of one clock of the two clock line driving type 1 E / B transfer area sensor.
  • FIG. 15 is a waveform diagram of the clock voltages V 1 and V 2 of FIG.
  • FIG. 16 (from A to L) is a vertical transfer breakdown diagram of the vertical CCD 6 driven by the drive circuit of FIG. 14, and shows the signal charge Q (1 to 6) of the potential well 3 (from Z to U). ) Are transferred in order.
  • FIG. 13 is a channel potential diagram of the vertical CCD of FIG.
  • FIG. 14 is a diagram showing one driving circuit of one clock of the two clock line driving type 1 E / B transfer area sensor.
  • FIG. 15 is a waveform diagram of the clock voltages V 1 and V 2
  • FIG. 17 is a cross-sectional view of one embodiment of a 1 EZB transfer area sensor in which directional transfer electrodes 3 Y and 3 W having an intermediate potential are arranged between clocks DVTG 3 Y. (Intermediate electrode)
  • the channel region 22A below 3Y and 3W is composed of a medium potential well region 22B and a medium potential barrier region 22C.
  • FIG. 18 is a channel potential diagram of the vertical CCD of FIG.
  • FIG. 19 is a cross-sectional view of one embodiment showing a modification of the vertical CCD of FIG. 17.
  • FIG. 20 is a channel potential diagram of the vertical CCD of FIG.
  • FIG. 21 is a driving circuit diagram of one embodiment of a 1-clock line driving type 1 EZB transfer error sensor, and shows a driving circuit of the vertical CCD described in FIGS. 17 and 19.
  • FIG. 22 is a waveform diagram of the clock voltage V1 in FIG.
  • FIG. 23 (from A to L) is a vertical transfer state diagram of the vertical CCD 6 driven by the drive circuit in FIG. 21.
  • the signal charge Q (from l to 8) of the potential 3 (from Z to D) is shown.
  • FIG. 24 is an equivalent circuit diagram of one embodiment representing the technique of the independent 1H storage partial subtraction technique of the independent invention 2.
  • FIG. 24 is an equivalent circuit diagram of one embodiment representing the technique of the independent 1H storage partial subtraction technique of the independent invention 2.
  • FIG. 25 is an equivalent circuit diagram of one embodiment of the smearing memory circuit of the independent invention 3.
  • FIG. 26 is a cross-sectional view of one embodiment of the two-electrode-coupled FT sensor according to Independent Invention 4, showing the channel region 22 of the vertical CCD.
  • FIG. 27 shows a cross section perpendicular to the cross section of m 26, and shows the channel regions 22 B of a plurality of vertical CCDs arranged in parallel.
  • Figure 28 shows one implementation of the vertical CCD shown in Figures 26 and 27. It is an example top view.
  • FIG. 29 is a clock voltage diagram showing another operation example of the shift register of FIG.
  • FIG. 30 is an equivalent circuit diagram of one embodiment of the shift register used in the 2-shift register driving 2 E / B transfer method of FIG.
  • FIG. 31 is an equivalent circuit diagram of the shift register used in the 2-shift register driving 1 EZB transfer method of FIG. 4 (A to F).
  • FIG. 32 is a clock voltage diagram of the shift register of FIG.
  • FIG. 33 is an equivalent circuit diagram of an embodiment of an accordion imager using a 2-shift register driven 1EB transfer method.
  • FIG. 34 (A to H) is a transfer state diagram showing the operation of the buffer CCD of FIG. 33 and the shift register that drives it.
  • FIG. 35 is a transfer state diagram showing the operation of the accordion imager of FIGS. 33 and 34 (A to H).

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Abstract

A CCD area sensor. The object of the invention is to remove the problem which stems from the fact that the charge transfer function of the vertical CCD(6) restricts the performance of the CCD area sensor. According to the CCD area sensor of the present invention, the fundamental feature resides in that the clock transfer electrodes 3 (Z to U) of the vertical CCD(6) are driven by dissimilar clock voltages in order to independently transfer the signal charges of the whole potential wells of the vertical CCD(6), that the empty potential well is injected from the output terminal of the vertical CCD(6), and that the next empty potential well is injected from said output terminal before the empty potential well that was previously injected before reaches the opposite end of output terminal of the vertical CCD(6).

Description

明 細 書  Specification
固体撮像装置 . ' '  Solid-state imaging device.
「技術分野」  "Technical field"
本発明は固体撮像装置技術に関し、 特に C CD固体撮像装置の改良に関する。  The present invention relates to solid-state imaging device technology, and more particularly to improvements in CCD solid-state imaging devices.
「背景技術」  "Background technology"
C CDエリアセンサに関して、 多くの方式が周知である。 垂直 C CDが画素列 を兼ねる C CDエリアセンサはフレーム転送 C CDエリアセンサ（F Tセンサ と略称される。 ）と呼ばれる。 垂直 C C Dと水平 C C Dの間に 1 フィールド画 像を代表する信号電荷を蓄積するバッファ C CDを備える F Tセンサはバッファ F Tセンサと呼ばれる。 上記のバ'： ファ C CDを持たない F Tセンサはフルフ レーム F Tセンサと呼ばれる。 画素列と独立に配置された垂直 C CDを備える C CDエリアセンサはインタライン転送 C CDエリアセンサ（I Tセンサ）と呼 ばれる。 画素と垂直 C C Dの間に配置される転送電極（AT G)が垂直 C C Dの 転送電極（V T Gと略称される。 ）と接続される I Tセンサは共通転送電極 I T センサと呼ばれる。 一般に C CDは 1 , 2 , 3 ,4相クロヅク電圧で駆動される が、 より多相のクロック電圧を使用する事も提案されている。 更に C CDエリ ァセンサにおいて重要な問題であるスメァノィズを低減する為に、 特開 5 6— 3 5 0 6 7はあらかじめ記億された 1行のスメァノィズを後で出力される 1行 の信号から差し引く事を開示する。 特出 5 8— 4 1 2 1 1 .6 2 54 7 , 7 64 7 7 , 8 64 1 6 ,-9 1 9 6 7 , 2 0 7 9 9 1 , 2 3 2 1 34 , 24 0 644 , 24 9 7 54 ,特出 5 9— 1 5 9 5 0 , 34 8 3 9 , 4 9 6 84 , 4 9 6 8 5 , 6 9 8 3 5 , 9 1 4 1 7 , 9 53 1 4 , 1 0 1 4 6 5 , 1 8 9 9 7 0 , 2 1 1 7 9 7は本 発明の先行出願である。 日本国特許公開 5 9 - 6 6 2 7 7は本発明に関連する 先行出願であり、 クロック線駆動形 2 E/B転送形式を開示する。  Many schemes are known for CCD area sensors. A CCD area sensor in which a vertical CCD also serves as a pixel array is called a frame transfer CCD area sensor (abbreviated as an F T sensor). An FT sensor including a buffer CCD for storing signal charges representing a one-field image between a vertical CCD and a horizontal CCD is called a buffer FT sensor. Above: An FT sensor without a CCD is called a full-frame FT sensor. A CCD area sensor having a vertical CCD arranged independently of a pixel column is called an interline transfer CCD area sensor (IT sensor). An IT sensor in which a transfer electrode (AT G) arranged between a pixel and a vertical CCD is connected to a transfer electrode (abbreviated as VTG) of the vertical CCD is called a common transfer electrode IT sensor. In general, CCDs are driven by 1, 2, 3, and 4 phase clock voltages, but it has been proposed to use more multi-phase clock voltages. Further, in order to reduce smearing which is an important problem in a CCD area sensor, Japanese Patent Laid-Open No. 56-35067 subtracts a previously recorded one-line smearing from a one-line signal output later. Disclose things. Special feature 5 8— 4 1 2 1 1.6 2 54 7, 7 64 7 7, 8 64 16, -9 1 9 6 7, 2 0 7 9 9 1, 2 3 2 1 34, 24 0 644, 24 9 7 54, prominent 5 9-1 5 9 5 0, 34 8 3 9, 4 9 6 84, 4 9 6 8 5, 6 9 8 3 5, 9 1 4 1 7, 9 53 1 4, 1 0 1 4 6 5, 1 8 9 9 7 0, 2 1 1 7 9 7 are prior applications of the present invention. Japanese Patent Laid-Open Publication No. 59-66272 is a prior application related to the present invention, and discloses a clock line drive type 2 E / B transfer format.
Γ発明の開示」  ΓDisclosure of the invention '
上記の先行技術にも拘わらず、 撮像管または光学カメラとの競争に.おいて固体 撮像装置は多くの改良を必要としている。 SZN比の改善、 特にスメァノイズ に対する S ZN比の改善は非常に重要である。 本発明の第 1の目的は固体撮像 装置の S Z N比の改善である。 更に解像度の改善.も重要である。 本発明の第 2 の目的は固体撮像装置の解像度の改善である。 上記の目的を達成する為に本発 明は C C Dエリアセンサに関して、 4個の独立発明を開示する。 各独立発明は - 深い相互関係を持ち、 ー锗に実施する事によって相乗効果が発生するので、 一 锗に説明される。 Despite the prior art described above, solid-state imaging devices require many improvements in competition with imaging tubes or optical cameras. Improved SZN ratio, especially smear noise It is very important to improve the SZN ratio for A first object of the present invention is to improve the SZN ratio of a solid-state imaging device. It is also important to improve the resolution. A second object of the present invention is to improve the resolution of a solid-state imaging device. In order to achieve the above object, the present invention discloses four independent inventions regarding a CCD area sensor. Each independent invention is explained-because it has a deep interrelationship and a synergistic effect can be created by implementing it in the background.
各独: 3：発明の概要  Germany: 3: Summary of the Invention
独立発明 1は本発明者によって連続注入 E Z B転送（C I E /B転送と略称さ れる。 ）と命名された C C D転送法によって、 C C Dエリアセンサの垂直 C C Dを駆動する技術が開示される。 上記の C I E / B転送の特徵は垂直 C C Dの 各クロック転送電極に異なるクロック電圧を印加し、 そして垂直 C C Dの出力 端から注入された空の電位井戸が上記の出力端と反対端に到着する前に次の空 の電位井戸を上記の出力端から注入する事である。 独立発明 2は C C Dエリア センサにおいて、 あらかじめ飽和画素列のスメァノィズと飽和画素列の 1部の 画素から出力される信号の差を検出する事を開示する。 独立発明 1 において、 垂直 C C Dの各電位井戸のスメァノィズ.電荷は独特の分布を持つので、 独立発 明 2のスメァノィズ低减法は非常に有効であろ。 独立発明 3は C C Dエリアセ ンサにおいて、 水平 C C Dを垂直帰線期間（信号電荷を水平 ¾送しない期間）に 低速で水平転送して、 スメァノイズ電荷を出力すろ事を開示する。 独立発明 2 に開示されるスメァノイズ低減技術は非常に有効であるが、 コストが大幅に増 加する問題があった。 独立発明 3 .はこの問題を解決する。 独立発明 4は P Tセ ンサにおいて、 隣接する 2個の転送電極を垂直 C C Dのチヤンネル領域または 垂直 C C D間のチヤンネルスト .ソプ領域の上方で接続する事を開示する。 独^ 発明 1の F Tセンサにおいて、 各ク口ック転送電極が実質的に 1画素を構成す るので、 各クロック転送電極の光透過率が等しい事が非常に好ましく、 更にク 口ック転送電極が複維な駆動回路から複雑なクロック電圧を印加されるので、 ： 動作の高速化の為に各クロック転送電極のライン抵抗が小さい事が好ましい。 独立発明 4は均一な光透過率と小さなライン抵抗を持つクロック ¾送電極を製 造する。 各独 発明とその従属発明の基本的な特徵が以下に記載される。 各発 明の具体的な特徴と効果が以下に説明される。 Independent invention 1 discloses a technique for driving a vertical CCD of a CCD area sensor by a CCD transfer method named continuous injection EZB transfer (abbreviated as CIE / B transfer) by the present inventor. The feature of the above CIE / B transfer is that a different clock voltage is applied to each clock transfer electrode of the vertical CCD, and the empty potential well injected from the output end of the vertical CCD arrives at the opposite end from the above output end. Then, the next empty potential well is injected from the above output terminal. Independent invention 2 discloses that in a CCD area sensor, a difference between a signal of a pixel output from a pixel of a part of the saturated pixel line and a pixel of the saturated pixel line is detected in advance. In the independent invention 1, the smearing of each potential well of the vertical CCD. Since the electric charge has a unique distribution, the smearing reduction method of the independent invention 2 may be very effective. Independent invention 3 discloses that in a CCD area sensor, a horizontal CCD is horizontally transferred at a low speed during a vertical blanking period (a period during which signal charges are not horizontally transmitted) to output smear noise charges. The smear noise reduction technology disclosed in Independent Invention 2 is very effective, but has the problem of significantly increasing costs. Independent invention 3 solves this problem. Independent invention 4 discloses that in a PT sensor, two adjacent transfer electrodes are connected above a channel region of a vertical CCD or a channel region between vertical CCDs. In the FT sensor of the first invention, since each of the clock transfer electrodes substantially constitutes one pixel, it is highly preferable that the light transmittance of each clock transfer electrode is equal. Since a complicated clock voltage is applied from a drive circuit having multiple electrodes, it is preferable that the line resistance of each clock transfer electrode be small in order to increase the operation speed. Independent invention 4 manufactures a clock transmission electrode having a uniform light transmittance and a small line resistance. The basic features of each independent invention and its dependent inventions are described below. The specific features and effects of each invention are described below.
(1 )， 2次元配列された複数の画素と、 画素列を兼ねるかまたは画素列と独立 に配置された垂直 C C Dと、 水平 C C Dを備え、 上記の垂直 C C Dは画素列の 信号電荷を水平 C C Dに転送する固体撮像装置において、 上記の垂直 C CDは 方向性転送電極（D V T Gと略称される。 ）と非方向性転送電極（ND V T Gと 略称される。 ）のどちらかまたは両方を備え、 そして上記の D V T Gまたは N D V T Gの一部または全部は転送ク口 'ソク電圧が印加される転送電極（ク口ッ ク転送電極と略称される。 ）であり、 そして垂直 C C Dの出力端に近いクロッ ク転送電極から順番に転送クロ、ゾク電圧が印加され、 そして垂直 C CDの出力 端から注入された空の電位井戸が垂直 C CDの出力端と反対端に到達する前に 次の空の電位井 Pが垂直 C C Dの出力端から注入される事を特徵とする固体撮 像装置。  (1) A two-dimensional array of multiple pixels, a vertical CCD that also serves as a pixel column, or is arranged independently of the pixel column, and a horizontal CCD. The above vertical CCD transfers the signal charge of the pixel column to a horizontal CCD. The vertical CCD includes one or both of a directional transfer electrode (abbreviated as DVTG) and a non-directional transfer electrode (abbreviated as ND VTG), and A part or all of the above DVTG or NDVTG is a transfer electrode to which a transfer voltage is applied (abbreviated as a close transfer electrode), and a clock transfer close to the output end of the vertical CCD. The transfer voltage and voltage are applied in order from the electrode, and the empty potential well injected from the output end of the vertical CCD arrives at the opposite end from the output end of the vertical CCD. Is injected from the output end of the vertical CCD. Solid-state imaging device.
(2) ,空の電位丼戸が垂直 C CDの出力端と反対端に到達した後で、 上記の垂 直 C C Dのクロック転送電極に 1相または 2相または 4相クロック電圧を印加 する事を特徴とォる第 1項記載の固体撮像装置- (2) Apply a one-phase, two-phase, or four-phase clock voltage to the vertical CCD clock transfer electrode after the empty potential bowl reaches the end opposite to the output end of the vertical CCD. Solid-state imaging device according to item 1
( 3 ) ,垂 i C C Dのすベての電位拌戸の電荷を互〔、に独 . に 送すろ事を特徵 とォる第 1項記載の固体撮像装置。 (3) The solid-state imaging device according to item 1, characterized in that the electric charges of all the potential stirring doors of the vertical iCCD are transmitted to each other independently.
4 ),クロック転送電極である D V T G (クロッ ク D V T Gと略称されろ。 ）の 下に作られる電位井戸の電荷を独立に転送する事を特徴とする第 1項 己載の固 体撮像装置。 .  4) The solid-state imaging device according to item 1, characterized in that the charge of a potential well created under a clock transfer electrode DVTG (abbreviated as clock DVTG) is independently transferred. .
( 5 ),隣接する 2個のクロック D V T Gの間のチヤ ンネル領域は中間直流電位 を持つ事を特徵とする第 4項記載の固体撮像装！軍.。 (5) The solid-state imaging device according to item 4, wherein the channel region between two adjacent clocks D VTG has an intermediate DC potential! army..
(6 ),クロック D V T Gの下に作られる電位 戸と、 隣接する 2個のクロック D V T Gの間に配置される中間直流電位拌戸の電荷を独立に転送する事を'特徵 とォる第 1項記載の固体撮像装置。 ( 7 )，クロック転送電極である N' D V T G (クロ 'ソク N D V T Gと略称される。 ） を備え、 そして奇（偶）数番目のクロック V T Gの下の ¾位并戸の電荷を独 3' に転送する事を特徵とする第 1項記載の固体撮像装置。 (6) The first feature is that the charge of the potential door created under the clock DVTG and the charge of the intermediate DC potential stirrer placed between two adjacent clocks DVTG are transferred independently. The solid-state imaging device according to claim 1. (7) Equipped with N 'DVTG (abbreviated as NDVTG) which is a clock transfer electrode, and the electric charge of the ¾-position parallel to the odd (even) -numbered clock VTG is reduced to 3'. 2. The solid-state imaging device according to claim 1, wherein the image is transferred.
( 8 ) ,垂直 C C Dの出力端から注入された空の電位井戸が 2電位井戸ピッチだ け逆転送された後で、 次の空の電位井戸が垂直 C CDの出力端から再び注入さ - れろ事を特徴とする第 1項記載の固体撮像装置。 (8) After the empty potential well injected from the output terminal of the vertical CCD is reversely transferred by two potential well pitches, the next empty potential well is injected again from the output terminal of the vertical CCD. 2. The solid-state imaging device according to claim 1, wherein:
(9) ,垂直 C CDの各クロック転送電極はシフ トレジスタの出力接点または上 記のシ'フトレジスタによって制御されるバッファ回路の出力接点に接続される 事を特徵とする第 1項記載の固体撮像装置。 - (9) The solid-state device according to item 1, wherein each clock transfer electrode of the vertical CCD is connected to an output contact of a shift register or an output contact of a buffer circuit controlled by the shift register. Imaging device. -
(1 0) ,上記のシフ トレジスタの各 1 Z2転送段の出力接点、 または上記の各(1 0), each of the above shift registers 1 Output contact of Z2 transfer stage, or each of the above
1 / 2転送段がそれぞれ制御する各バッファ回路の出力接点が垂直 C CDの各 クロック NDVTGにそれぞれ接続される事を特徵とする第 9項記載の固体撮 10. The solid-state imaging device according to claim 9, wherein the output contact of each buffer circuit controlled by the 1/2 transfer stage is connected to each clock NDVTG of the vertical CCD.
(1 1 ) ,上記のシフ トレジスタの各耘送段の出力接点、 または上記の各転送段 がそれぞれ制御する各バッファ回路の出力接点がそれぞれ垂直 C CDの各クロッ ク D V T Gに接続される事を特徵とする第 9項記載の固体撮'像装置。 (11) The output contacts of each shift stage of the shift register or the output contacts of each buffer circuit controlled by each transfer stage are connected to each clock DVTG of the vertical CCD. 10. The solid-state imaging device according to claim 9, wherein:
(1 2) .垂直 C CDの奇（偶）数番目のクロック転送電極（クロック N D V T Gま たはクロック D VT Gを指定する）とその偶（奇）数番目のク口ック耘送電極は 異なるシフ ト レジスタの出力接点または異なるシフ ト レジスタによって制御さ れるバッファ回路の出力接点に接続される事を特徵とする第 9項記載の固体撮 像装置。 ' . ·  (1 2). The odd (even) number clock transfer electrode (specifying clock NDVTG or clock D VTG) of the vertical CCD and its even (odd) number clock transmission electrode are 10. The solid-state imaging device according to claim 9, wherein the solid-state imaging device is connected to an output contact of a different shift register or an output contact of a buffer circuit controlled by the different shift register. '. ·
(1 3 ),画素と垂直 C C Dを電気的に接統する転送電極（以下において AT Gと 略称される。 ）が垂直 C C Dのクロック転送電極に接続されるィンタライン転 送 C C Dセンサ（以下において共通転送電極 I Tセンサと略称される。 ）であり、 そして上記のシフ トレジスタまたはバッファ回路の電源電 JEの変更によって、 画素から垂直 C C Dに信号電荷を転送する事を特徵とする第 9項記載の固体撮 像装置。 ( 1 4 )，垂直 C C Dの各クロック D V T Gは順次スィツチを介して 1相または 2相クロック電源に接続され、 そして上記の順次スィツチはシフ トレジスタに よって制御される事を特徵とする第 1項記載の固体撮像装置。 (13), an interline transfer CCD sensor (hereinafter referred to as common transfer) in which a transfer electrode (hereinafter abbreviated as ATG) that electrically connects the pixel and the vertical CCD is connected to the clock transfer electrode of the vertical CCD. 10. The solid-state imaging device according to item 9, wherein the signal charge is transferred from the pixel to the vertical CCD by changing the power supply JE of the shift register or the buffer circuit described above. Imaging device. (14), wherein each clock DVTG of the vertical CCD is connected to a one-phase or two-phase clock power supply via a sequential switch, and the sequential switch is controlled by a shift register. Solid-state imaging device.
(1 5 ) ,垂直 C C Dの隣接する 2個のクロック DVT Gと 2相クロック電源を 接続する 2個の順次スィツチは同時に動作する事を特徵とする第 1 項記載の 固体撮像装置。  (15) The solid-state imaging device according to item 1, wherein two sequential switches connecting the two clocks DVTG adjacent to the vertical CCD and the two-phase clock power supply operate simultaneously.
(1 6)，垂直 C CDの各クロック転送電極は順次スィツチを介してクロック電 源によって駆動され、 そして上記のクロック DVT Gまたは奇（偶）数番目のク ロック ND V T Gは垂直転送期間の前 深い電位 V Hに充電され、 'そして次の 垂直転送期間に各クロック転送電極は上記の順次スィッチを介してだけ電圧を 印加される事を特徵とする第 1項記載の固体撮像装置。  (16) Each clock transfer electrode of the vertical CCD is sequentially driven by a clock power supply via a switch, and the above clock DVTG or the odd (even) th clock ND VTG is set before the vertical transfer period. 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is charged to a deep potential VH, and a voltage is applied to each clock transfer electrode only through the above-mentioned sequential switch during the next vertical transfer period.
C1 7),垂直転送期間の前に、 上記の各クロック D V T Gまたは奇（偶）数番目 のクロック N D V T Gは上記のクロック電源によつて深い電位 V H、 または読 みだし電位 V Rを印加される事を特徵とする第 1 6項記載の固体撮像装置。 ( 1 8 ),垂直 C C Dのクロック転送電極に転送クロック電圧を直接または間接 に印加するか、 または垂直 C C Dのクロック転送電極とク口 'ソク電源を接続す る順次スィツチを制御するシフ トレジスタは撮像部の両側に配置される事を特 徴とする第 1項記載の固体撮像装置。  C17), before the vertical transfer period, the above clock DVTG or the odd (even) th clock NDVTG is applied with the deep potential VH or the read potential VR by the above clock power supply. 17. The solid-state imaging device according to item 16, wherein (18) The shift register that applies the transfer clock voltage directly or indirectly to the clock transfer electrode of the vertical CCD, or controls the sequential switch that connects the clock transfer electrode of the vertical CCD and the power supply, captures the image. 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is arranged on both sides of the unit.
(】 9)、 各垂直 C C Dのクロック転送電極に接続される 1行の垂直走査線は両 側からク口ツク電圧を印加される事を特徵とする第 1 8項記載の固体撮像装置。 (2 0), 1 ライールド期間にすべての画素の信号電荷を出力し、 そして出力さ れた奇（偶）数番目の画素行の信号電荷だけを表示する事を特徵とする第 1項記 載の固体撮像装置。  (9) The solid-state imaging device according to Item 18, wherein one vertical scanning line connected to the clock transfer electrode of each vertical CCD is applied with a click voltage from both sides. (2 0), 1 The signal charge of all pixels is output during the field period, and only the output signal charges of the odd (even) number pixel rows are displayed. Solid-state imaging device.
(2 1 ),インタライン転送 C C Dセンサ（ ί Τセンサと略称される。 ）であり、 そして低照度時にフ レーム蓄積動作を実施し、 高照度時にフィ ールド蓄積動作 を実施する事を特徵とする第 1項記載の固体撮像装置。 .  (21), interline transfer CCD sensor (abbreviated as Τ Τ sensor), which performs frame accumulation operation at low illuminance and performs field accumulation operation at high illuminance 2. The solid-state imaging device according to claim 1. .
(2 2), I Τセンサであり、 そして垂直 C CDは信号電荷とノィズ電荷を交互 に出力する事を特徵とする第 1項記載の固体撮像装置。 (2 2), I Τ sensor, and vertical CCD alternates signal charge and noise charge 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device outputs the data.
(23),信号電荷を垂直転送しない期間に垂直 C CDに残留するノィズ電荷は クリァされるかまたは再配 gされる事を特徵とする第 1項記載の固体撮像装置。 (24 ),画素から垂直 C C Dの隣接する 2個の電位并戸または残留ノィズ電荷 を保持する電位井戸によみだされた信号電荷を出力し、 そしてあらかじめ記億 されたスメァノィズ電圧と出力された信号電圧の差を検出する事を特徵とする 第 Γ項記載の固体撮像装置。  (23) The solid-state imaging device according to item 1, wherein noise charges remaining in the vertical CCD during a period in which signal charges are not vertically transferred are cleared or rearranged. (24) Output the signal charge from the pixel to the two adjacent potentials of the vertical CCD or the potential well holding the residual noise charge, and then output the previously stored smear noise voltage and the output signal. 4. The solid-state imaging device according to claim 3, wherein the difference in voltage is detected.
(2 5), 2次元配列された複数の画素と、 画素列を兼ねるかまたは画素列と独 立に配置された垂直 C C Dと、 水平 C CDを備え、 _b記の垂直 C CDは画素列 の信号電荷を水平 C CDに転送する固体撮像装置において、 飽和信号電荷を発 生する画素（飽和画素と略称される。 ）を含む画素列（飽和画素列と略称される。 )のスメァノィズ電圧を記億し、 そして少なくとも上記の飽和画素列の一部の 画素から発生する信号電圧から上記の記憶されたスメァノィズ電圧を差し引く 事を特徵とする固体撮像装置。  (25), a plurality of pixels arranged in a two-dimensional array, a vertical CCD that also serves as a pixel column or is arranged independently of the pixel column, and a horizontal CCD. In a solid-state imaging device that transfers signal charges to a horizontal CCD, the smearing voltage of a pixel row (abbreviated as a saturated pixel row) including a pixel that generates a saturated signal charge (abbreviated as a saturated pixel row) is recorded. A solid-state imaging device characterized in that the stored smearing voltage is subtracted from a signal voltage generated from at least a part of the pixels of the saturated pixel row.
(2 6 ),飽和画素から発生する信号電荷から上記のスメァノィズ電圧を差し引 かない事を特徴とする第 2 5項記載の固体撮像装蘆。  (26) The solid-state imaging device according to item 25, wherein the above-mentioned smearing voltage is not subtracted from the signal charges generated from the saturated pixels.
( 2 7 ),飽和画素列の飽和画素から下流の画素から発生する一部または全部の 闸紊から発牛-する信 -電圧から上記のスメァノィズ電圧を差し引かない事を特 徴とする第 2 5項記載の固体撮像装置。  (27) A feature of the present invention is that the above-mentioned smearing voltage is not subtracted from the signal generated from a part or all of the pixels generated from the pixels downstream from the saturated pixels in the saturated pixel row. Item 13. The solid-state imaging device according to Item 1.
(2 8 ),飽和画素を持たない画素列（非飽和画素列と略称される。 ）の画素から 発生する信号電圧から上記のスメァノィズ電圧を差し引かない事を特徵とする 第 2 5項記載の固体撮像装置。  (28) The solid according to item 25, wherein the above-mentioned smearing voltage is not subtracted from a signal voltage generated from a pixel in a pixel row having no saturated pixel (abbreviated as a non-saturated pixel row). Imaging device.
(2 9 ), 2次元配列された複欽の兩素と、 画素列を兼ねるかまたは画素列と独 立に さ た垂直 C C Dと、 水平 C CDを備え、 上記の垂直 C CDは画素列 の信 ^電荷を水平 C CDに転送する固体撮像装置において、 上記の水平 C CD は垂直帰線期間にスメァノィズ電荷を第 1速度で水平転送し、 そして水平走查 斯間に i 号電荷を第 2速度で水平転送し、 そして上記の第 1速度は上記の第 2 速度の 1ノ 2以下の速度である事を特徵とする固体撮像装置。 (29), equipped with a two-dimensionally arrayed double chip, a vertical CCD that also serves as a pixel row or is independent of a pixel row, and a horizontal CCD. In the solid-state imaging device that transfers the charges to the horizontal CCD, the horizontal CCD horizontally transfers the scan charges at the first speed during the vertical retrace period, and transfers the second charge during the horizontal scan. Horizontal transfer at the speed, and the first speed above is the second A solid-state imaging device characterized in that the speed is 1 to 2 or less.
C3 0)，垂直帰線期間に水平 C C Dから出力されたスメァノィズは遂次比校形 A.ZD変換器によってデジタルメモリに入力される事を特徵とする第 2 9項記 載の固体撮像装置。  C30). The solid-state imaging device according to item 29, wherein the smears output from the horizontal CCD during the vertical retrace period are input to the digital memory by the successive ratio type A.ZD converter.
(3 1 ),デジタルメモリから再生されたスメァノィズは遂次比校形 A ZD変換 器の DZA変換器で DZ A変換される事を特徵とする第.3 0項記載の固体撮像  (31) The solid-state imaging device described in Section 30 is characterized in that the smears reproduced from the digital memory are DZA-converted by the DZA converter of the successive-ratio AZD converter.
(3 2), 2次元配列された複数の画素と、 画素列を兼ねる垂直 C CDを備え、 上記の垂直 C C Dは画寒列の信号電荷を水平 C C Dに転送する固体撮像装置に おいて、 垂直 C C Dの隣接する 2個のクロック転送電極はチヤンネル領域また はチャンネルス トツプ領域の上方で接続され、 そして上記の 2個のクロック転 送電極は 3倍以上の抵^:比を持つ事を特徵とする固体撮像装置。 (3 2), a plurality of pixels arranged two-dimensionally, and a vertical CCD that also serves as a pixel column. The two adjacent clock transfer electrodes of the CCD are connected above the channel region or channel stop region, and the two clock transfer electrodes described above have a resistance: ratio of more than three times. Solid-state imaging device.
(3 3 ),上記の 2個のク ΰ 'ソク転送電極はチヤンネルス トップ領域の上方で接 続される事を特徴とする第 34.項記載の固体撮像装置。 (33) The solid-state imaging device according to the item 34, wherein the two crystal transfer electrodes are connected above a channel stop region.
各発明の具体的な特徵と効果が以下に説明される。 Specific features and effects of each invention will be described below.
独立発明 1 ,ク レーム 1  Independent invention 1, Claim 1
本発明は C CDエリァセンサにおいて、 垂直 C C Dのク σ .ソク転送電極にそれ ぞれ異なるクロック電圧を印加し、 そして垂直 C C Dの出力端から注入された 空の電位井戸が垂直 C C Dの他の一端に到着する前に次の空の電位井戸を上記 の出力端から再び注入し、 そして垂直 C C Dのすベての電.位并戸の電荷をそれ ぞれ独立に.転送する事を特徵とする。 上記の転送は連続注入 ΕΖΒ転送（C I ΕΖΒ転送）と略称される。 垂直 C C Dの各電荷は上記の C I Ε/Β転送を実 施する前に総ての方向性転送電極（D V T G)の下の電位丼戸に、 または奇（偶） 数番目の非方向性転送電極（NDV T G)の下の電位井戸に蓄積されている。 勿 論偶（奇）数番目の NDVT Gはその下に電位障壁を作る。 ただし、 NDVT G はその下のチヤンネル電位が一定であり、 電荷をどちらの方向へも転送できる 転送電極であり、 DVT Gはその下のチヤンネルに浅い電位 V Lを持つ電位障 壁領域と深い電位 V Hを待つ電位井戸領域が作られる転送電極である。 典型的 に 4相 C C Dは 4種類の N D V T Gを持ち、 2相 C C Dは 2種類の D V T Gを 持つ。 浅い電位 V Lは Nチャンネル C C Dにおいて、 負方向により大きい電位 であり、 深い電位 V Hは正方向により大きい電位である。 このようにすれば 2 相または 4相クロック電圧で駆動される従来の垂直 C C Dに比べて、 画素当た りの転送電極数を半分にできる。 そして電荷転送能力を 2 ίきにできる。 C C D の各転送電極にそれぞれ異なるク口 Vク電圧を印加し、 各 D V T Gの下のまた は奇（偶）数番目の N D V T Gの下の電荷をそれぞれ独立に転送する事は公知で あり、 たとえばセキンと トンプセツ ト，近代科学社，電荷転送デバイス， 3 6か ら 3 7頁と 2 2 8から 2 2 9頁，に記載されている。 しかし、 上記の先行技術 において、 1個の空の電位井戸（電荷を保持しない電位井戸）を垂直 C C Dの出 力端からその反対端まで逆転送する事によつて全体の電荷を 1電位井戸ピッチ だけそれぞれ耘送する。 その結果電荷転送速度が遅くなり、 C C Dエリアセン サへの応用は実質的に不可能であった。 転送速度を改善する為に、 垂直 C C D の M個の転送電極を N群に分割し、 そして τ個の空の電位井戸を配置するも提 案されている。 その結果電荷転送速度は N倍になり、 必要なクロック電圧は M .Z N相になる。 しかし、 C C Dエリアセンサにおいて、 画素と垂直 C C Dの電 位拌戸の比が整数関係を持たないことは垂直 C C Dの耘送電極構造を非常に複 雑にし、 そして各電位并戸の電荷蓄積能力を低下させる欠点を持つ。 これらの 問題は本発明によって解決された。 本発明の他の特徵と効果は以下の説明を参 照されたい。 ― - 従属発明 1 ，クレーム 2 ' The present invention relates to a CCD area sensor, in which a different clock voltage is applied to each vertical transfer electrode of the vertical CCD, and an empty potential well injected from the output terminal of the vertical CCD is connected to the other end of the vertical CCD. Before arrival, the next empty potential well is injected again from the above output terminal, and the electric charges of all the electric potentials of the vertical CCD are independently transferred. The above transfer is abbreviated as continuous injection ΕΖΒ transfer (CI ΕΖΒ transfer). Each charge of the vertical CCD is transferred to the potential bowl under all directional transfer electrodes (DVTG) or the odd (even) number of non-directional transfer electrodes before performing the above-mentioned CI Ε / Β transfer. (NDV TG) accumulated in the potential well. Of course, the even-numbered NDVT G creates a potential barrier beneath it. However, NDVT G is a transfer electrode that has a constant channel potential below it and can transfer charges in either direction, and DVT G is a potential obstacle with a shallow potential VL to the channel below it. This is a transfer electrode in which a wall region and a potential well region waiting for a deep potential VH are formed. Typically, a four-phase CCD has four types of NDVTG, and a two-phase CCD has two types of DVTG. The shallow potential VL is a larger potential in the negative direction in an N-channel CCD, and the deep potential VH is a larger potential in the positive direction. In this way, the number of transfer electrodes per pixel can be halved compared to a conventional vertical CCD driven by a two-phase or four-phase clock voltage. And the charge transfer capability can be reduced to two. It is known that a different voltage is applied to each transfer electrode of a CCD, and the electric charge under each DVTG or under an odd (even) NDVTG is independently transferred. And Thompset, Modern Science, Inc., Charge Transfer Devices, pp. 36-37 and 228-229. However, in the above prior art, one empty potential well (potential well holding no charge) is reversely transferred from the output end of the vertical CCD to the opposite end, so that the entire charge is shifted by one potential well pitch. Only till each. As a result, the charge transfer speed became slow, and application to CCD area sensors was virtually impossible. In order to improve the transfer speed, it has been proposed to divide the M transfer electrodes of the vertical CCD into N groups and to arrange τ empty potential wells. As a result, the charge transfer rate increases N times and the required clock voltage becomes M.ZN phase. However, in the CCD area sensor, the ratio between the pixel and the potential stirring unit of the vertical CCD does not have an integer relationship, which greatly complicates the cultivation electrode structure of the vertical CCD and increases the charge storage capacity of each potential paralleling unit. It has the disadvantage of lowering. These problems have been solved by the present invention. For other features and effects of the present invention, see the description below. --Dependent invention 1, claim 2 '
本発明において、 各ク π Vク転送電極はそれぞれ異なるクロック電 Eを受け取 ろ。 そして空の電位井戸が垂直 C C Dの出力端から注入され、 注入された空の 電位丼戸が反対端に到着する前に次の空の電位丼戸が上記の出力端から注入さ れるっ そして空の電位并戸が上記の反対端に到着した後で、 各クロッグ転送電 極に 1相または 2相または 4相クロック電圧が印加される。 空の電位井戸が垂 直 C C Dの反対端に到着するかまたその 1 ビ'ソ ト下流のクロ、ソク転送電極に到 着するときに、 各信号電荷井戸（信号電荷を保持する電位井戸）の間に空の電位 井戸が配置される。 従って空の電位井戸が上記の反対端に到着した後で、 垂直 C C Dを従来の 1相または 2相または 4相クロッ ク電圧で駆動する事ができる。 In the present invention, each clock transfer electrode receives a different clock voltage E. An empty potential well is injected from the output end of the vertical CCD, and the next empty potential bowl is injected from the output end before the injected empty potential bowl arrives at the opposite end. After the potentials of the two arrive at the opposite end, a one-phase, two-phase, or four-phase clock voltage is applied to each clog transfer electrode. Empty potential well When arriving at the opposite end of the direct CCD or arriving at the black and slow transfer electrodes one bit downstream, empty potential wells between each signal charge well (potential well holding signal charge) Is arranged. Therefore, after the empty potential well arrives at the opposite end, the vertical CCD can be driven with the conventional one-phase, two-phase or four-phase clock voltage.
従属発明 2 ,クレーム 3  Dependent invention 2, Claim 3
本発明の重要な利点は垂直 C C Dの作ることができるすべての電位井戸の電荷 を独立に転送できる事である。 1実施例において、 1水平帰線期間に 2個の空 の電位井戸が垂直 C C Dの出力端から注入される。 その結果 1水平走査期間に 隣接する 2画素行の信号電荷を独立に出力する事ができる。 ただし空の電位井 戸の注入は垂直 C C Dの 1電位井戸の電荷をその出力端から出力する事に等し い。 他の 1実施例において、 垂直 C C Dの隣接する 2-個の電位井戸は同じ画素 の電荷を転送する。 このようにすれば実質的に垂直 C C Dのダイナミ ック レン ジを 2倍にできる、  An important advantage of the present invention is that it can independently transfer the charge in all potential wells that a vertical CCD can make. In one embodiment, two empty potential wells are injected from the output of the vertical CCD during one horizontal retrace period. As a result, signal charges of two adjacent pixel rows can be output independently in one horizontal scanning period. However, injecting an empty potential well is equivalent to outputting the charge of one potential well of the vertical CCD from its output terminal. In another embodiment, two adjacent potential wells in a vertical CCD transfer charge for the same pixel. This effectively doubles the dynamic range of vertical CCD.
従属発明 3 ,クレーム 4  Dependent invention 3, Claim 4
1実施冽において、 垂直 C C Dはクロック D V T Gを備え、 そして各クロック D V T Gの下の電位井戸の電荷は独立に転送される。 1実施例において、 1画 素当たり 1個の D V T Gが配置される。 他の 1 実施例において、 I Tセンサの 垂直 C C Dは 1 画素当たり 2個の D V T Gを備える。 そして隣接する 2個の電 位井戸で 1画素の信号電荷を転送する。 または奇（偶）数番目の電位井戸で信'号 電荷を転送し、 偶（奇）数番目の電位井戸でノィズ電荷（特にスメァノィズ電荷） を転送すろ。 即ち、 2.画素行の電荷をよみだす事、 .または垂直 C C Dの電荷転 送能力を 2倍にする事、 または信号電荷とノィズ電荷を分離して転送する事が 可能になる。 1 画素当たり 2 D V T Gを配置する I Tセンサの実施例において、 奇（偶）数番目の電位井戸が信号電荷を転送し、 そして上流側に隣接する偶（奇） 数番目の電位井戸で非転送電荷を集める事も可能である。 その結果転送効率が 改善される。  In one implementation, the vertical CCD is provided with a clock DVTG, and the charge in the potential well under each clock DVTG is transferred independently. In one embodiment, one D VTG is arranged per pixel. In another embodiment, the vertical CCD of the IT sensor comprises two DVTGs per pixel. The signal charges of one pixel are transferred between two adjacent potential wells. Alternatively, transfer the signal charge in the odd (even) number potential well and transfer the noise charge (especially the smear noise charge) in the even (odd) number potential well. That is, 2. It is possible to read out the charges in the pixel row, or to double the charge transfer capability of the vertical CCD, or to transfer the signal charges and noise charges separately. In an embodiment of an IT sensor where 2 DVTGs are arranged per pixel, the odd (even) potential wells transfer signal charge, and the non-transferred charge in the even (odd) potential well adjacent upstream It is also possible to collect. As a result, transfer efficiency is improved.
従属発明 4 ，ク レーム 5 クレーム 4の 1実施例において、 隣接する 2値のクロック D VT Gの間の中間 チャンネル領域に、 中間直流電位を与える事ができる。 この実施例は特に FT センサに好ましい。 ί実施例において、 上記の中間チヤンネル領域の上に中間 直流電位を持つ ND V T Gが配置される。 この ND V T Gは一定電圧を持つの で、 非常に薄く作ることができ、 高い青感度を持つ。 他の 1実施例において、 垂直 C CDはバルクチャンネルを持ち、 そして露出した中間チヤンネル領域の 表面にイオン注入を実施し、 その下のバルクチャ： ネル領域に一定の中間電位 が付加される。 上記の露出した中間チヤンネル領域は高い青感度を持つ。 Dependent invention 4, claim 5 In one embodiment of claim 4, an intermediate DC potential can be applied to an intermediate channel region between adjacent binary clocks D VTG. This embodiment is particularly preferable for an FT sensor. In the embodiment, an ND VTG having an intermediate DC potential is arranged on the above-mentioned intermediate channel region. Since this ND VTG has a constant voltage, it can be made very thin and has high blue sensitivity. In another embodiment, the vertical CCD has a bulk channel, and the surface of the exposed intermediate channel region is implanted with a constant intermediate potential applied to the underlying bulk channel region. The exposed intermediate channel region has a high blue sensitivity.
従属発明 5 ,ク レーム 6  Dependent invention 5, Claim 6
1実施例において、 垂直 C CDはクロック D VT Gと、 クロック DVTGの間 の中間チヤ ンネル領域に作られた中間直流電位井戸と中間直流電位障壁を備え る。 上記の中間直流電位丼と中間直流電位障壁はクロック D V T Gの間の中間 チャンネル領域の上方に中間直流電位を印加される DVTGを配置する事によつ て、 または上記の中間バルクチャンネル領域の露出した表面に 2回のイオン注 入を実施する事によって作られる。 この実施例を F Tセンサに応用する時に、 音感度が改善される。  In one embodiment, the vertical CCD includes a clock D VTG and an intermediate DC potential well and an intermediate DC potential barrier created in an intermediate channel region between the clocks DVTG. The intermediate DC potential bowl and the intermediate DC potential barrier can be provided by arranging the DVTG to which the intermediate DC potential is applied above the intermediate channel region between the clock DVTGs, or by exposing the intermediate bulk channel region. Created by performing two ion implantations on the surface. When this embodiment is applied to an FT sensor, the sound sensitivity is improved.
従厲発明 6 ,ク レーム 7  Subordinate invention 6, claim 7
I ¾施例において、 奇（偶）数番目のクロック ND V T Gの下に '¾位拌戸が作ら れ、 偶（奇）数番目のクロック MD VTGの下に電位障壁が作られ、 上記の電位 井 の電荷が独立に転送されろ。 1実施例において、 1画素当たり 2個のクロッ ク VTGが配置される。 ただし F Tセンサにおいて、 'フィ一ルド期間毎に 上記の ¾位井戸と電位障壁の位置を反対にする事によって、 インタ レース動作 を実施でき、 垂直画素数を等価的に 2倍にでさる。 I Tセンサの 1実施例にお いて、 1画素当たり 1個の ND VT Gを配置する事ができる。 この実施例にお いても、 フィールド期間毎に異なる画素行の信号電荷を転送する事によって、 インタレース動作を実旎できる。 勿論 1画素当たり、 2 NDVTGを備える実 施冽において、 2画素行の信号電荷の並列読みだし、 その他従属発明 3で説明 された電荷転送方式が実施できる。 I In the present embodiment, an odd-numbered stirrer door is created below the odd-numbered clock ND VTG, and a potential barrier is created below the even-numbered clock MD VTG. Transfer well charges independently. In one embodiment, two clock VTGs are arranged per pixel. However, in the FT sensor, the interlaced operation can be performed by reversing the positions of the upper well and the potential barrier every field period, and the number of vertical pixels is equivalently doubled. In one embodiment of the IT sensor, one ND VTG can be arranged per pixel. Also in this embodiment, an interlace operation can be performed by transferring signal charges of different pixel rows for each field period. Of course, with the implementation of 2 NDVTG per pixel, the signal charges of 2 pixel rows are read out in parallel, and other dependent inventions 3 explain. The implemented charge transfer method can be implemented.
従属発明 7，ク レーム 8 · *  Dependent invention 7, Claim 8 · *
クレーム 1の好ましい動作において、 垂直 C C Dの出力端から注入された空の 電位井戸が 2電位井戸ピッチだけ逆転送された後で、 次の空の電位拌戸が再び 上記の出力端から注入される。  In a preferred operation of claim 1, after the empty potential well injected from the output terminal of the vertical CCD is reversely transferred by two potential well pitches, the next empty potential stirring door is injected again from the above output terminal. .
従属発明 8 ,ク レーム 9  Dependent invention 8, Claim 9
'好ましい 1実施例において、 垂直 C C Dの各クロック電極は垂直転送クロック 電圧を発生するシフ ト レジスタの出力接点または上記の出力接点によって制御 される電流増幅用バッファ回路の出力接点に接続される。 上記のバヅファ回路 は一般にソースホロワ回路またはソース接地ィンバーター回路であり、 小さい 出力抵抗を持つ。 In a preferred embodiment, each clock electrode of the vertical CCD is connected to an output contact of a shift register for generating a vertical transfer clock voltage or an output contact of a current amplification buffer circuit controlled by the above-mentioned output contact. The above buffer circuit is generally a source follower circuit or a common-source inverter circuit and has a small output resistance.
従属発明 9，ク レーム 1 0  Dependent invention 9, claim 1 0
垂直 C C Dがクロック ND V T Gを備える C I E//B転送C CDエリアセンサ (以下 (こおいて 2 EZB転送センサと略称される。 ）において、 各クロック ND V T Gは 2相シフ トレジスタを構成する各インバーターの出力接点または上記 の出力接点によって制御されるバッフ τ回路の出力接点に接続されろ。 このよ うにすれば 2 E/B転送センサの垂直ク口ック電圧を発生でさる。 勿論 4相シ フ トレジスタの奇（偶）数番目のィンバーターの出力接点に各クロック ND V T Gを接続してもよい。 Vertical CCD is abbreviated CIE / / B transfer C CD area sensor (hereinafter as (Kooite 2 EZB transfer sensor comprises a clock ND VTG. In), each clock ND VTG's respective inverters constituting the two-phase shift register Connect it to the output contact or to the output contact of the buffer τ circuit controlled by the output contact described above, which will generate the vertical cut-off voltage of the 2 E / B transfer sensor. Each clock ND VTG may be connected to the output contact of the odd (even) number inverter of the register.
従属発明 1 0 ,ク レーム 1 1 ― .  Dependent invention 10, claim 11 1.
垂直 C C Dがクロック D V T_Gを備える C I EZB転送 C C Dエリアセンサ（以 下において 1 Eノ B転送センサと略称される。 ）において、 各クロック D VT Gは 2相シフ トレジスタを構成する各インバーターの内、 奇（偶）数番目のイン パーターの出力接点または上記の出力接点によって制御されるバッファ回路の 出力接点に接続される。 このようにすれば 1 EZB転送センサの垂直クロック 電圧を発生できる。 勿論、 4相シフ ト レジスタを構成する 4種類のインバータ —の内の 1種類のィンパ'一ターの出力接点に各クロック D V T Gを直接または バッファ回路を介して接続できる。 また 3相シフ トレジスタを構成する 3種類 のィンバーターの内の 1種類のインバーターの出力接点に直接にまたはバッファ 回路を介してクロック DVT Gを接続してもよい。 即ち、 クレーム 1 1の文言 はシフ ト レジスタの 1転送段当たり 1個の出力接点に各クロック D VT Gを接 続する事を意味ォる。 勿論各クロック D VT Gは各行のクロ ':/ク DVTGを意 味する， クレーム 1 0においてシフ ト レジスタの 1 / 2転送段当たり 1個の出 力接点にクロック ND V T Gが接続さ る。 クレーム 9において、 2相シフ ト レジスタは構造と動作が簡単であり、 垂直方向の画素密度を大きくできるので、 特に好ましい。 本従属発明において、 クロック DVTGに接続されるシフ トレ ジスタのインバーター（出カインバーターと略称される。 ）またはバッファ回路 を構成すろィンバーターはレシオレス動作を実施する事が好ましい。 レシオレ スインバーターはその出力接点を論理放電する評価期間の前に、 上記の出力接 点を一斉に充電する充電斯間を持つので、 垂直 C CDの空の電位井戸の上方の クロック D V T Gは上記の空の電位井戸に電荷が転送される前に、 上記の空の 電位井戸を浅い電位 V Lから深い電位 VHに変化させる。 その結果 1 EZB転 送動作は非常に安定する。 In a vertical CCD CCD area sensor (hereinafter abbreviated as 1E B transfer sensor) having a clock DV T_G, each clock D VTG is composed of two inverters constituting a two-phase shift register. Connected to the output contact of the odd (even) numbered inverter or to the output contact of the buffer circuit controlled by the above output contact. In this way, the vertical clock voltage of one EZB transfer sensor can be generated. Of course, each clock DVTG is directly or directly connected to the output contact of one of the four types of inverters that constitute the four-phase shift register. It can be connected via a buffer circuit. Alternatively, the clock DVTG may be connected directly to the output contact of one of the three types of inverters constituting the three-phase shift register or via a buffer circuit. That is, the wording of claim 11 means that each clock DVTG is connected to one output contact per transfer stage of the shift register. Of course, each clock DVTG means the clock DVTG of each row. In claim 10, the clock ND VTG is connected to one output contact per 1/2 transfer stage of the shift register. In claim 9, a two-phase shift register is particularly preferred because it is simple in structure and operation and can increase the pixel density in the vertical direction. In the dependent invention, it is preferable that the inverter (shifted output inverter) of the shift register connected to the clock DVTG or the buffer inverter constituting the buffer circuit performs a ratioless operation. Since the ratio inverter has a charge period for charging the above output contacts all at once before the evaluation period for logically discharging its output contacts, the clock DVTG above the empty potential well of the vertical CCD is Before the charge is transferred to the empty potential well, the above-mentioned empty potential well is changed from the shallow potential VL to the deep potential VH. As a result, 1 EZB transfer operation is very stable.
従属 ¾明 1 1 ,クレーム 1 2  Dependent description 1 1, claim 1 2
1 EZB転送センサまたは 2 EZB転送センサにおいて、 奇（偶）数番目のクロ ':/ ク転送電極と偶（奇）数番目のクロック転送電極は異なるシフ トレジスタによつ て直接に、 またはバッファ回路を介して駆動される。 好ましい 1突施冽におい て&シフ ト レジスタの 転送段当たり 1個の出力接点にクロック 送電極が接 続される。 このようにすれば 1 E B転送または 2 EZB転送に必要な垂直ク ロック電圧を発生できる。 更に、 少ない転送段数を持つシフ トレジスタを撮像 領域の両側に配置できるので、 シフ トレジスタの 1転送段の垂直寸法が 2倍に できる。 そして各シフ トレジスタのクロック電獠周波数を低減できる。  In the 1 EZB transfer sensor or 2 EZB transfer sensor, the odd (even) clock transfer electrode and the even (odd) clock transfer electrode can be connected directly by different shift registers or by a buffer circuit. Is driven through. In a preferable one-shot condition, the clock transmitting electrode is connected to one output contact per transfer stage of the & shift register. In this way, the vertical clock voltage required for 1EB transfer or 2EZB transfer can be generated. Furthermore, since shift registers having a small number of transfer stages can be arranged on both sides of the imaging area, the vertical dimension of one transfer stage of the shift register can be doubled. Then, the clock power frequency of each shift register can be reduced.
従属発明 1 2.ク レーム 1 3  Dependent invention 1 2. Claim 1 3
共通 &送電極 I Tセンサにおいて、 シフ トレジスタの電源電圧を最も深い読み だし電圧 V Rにする事によって、 総ての画素または奇（偶）数番目の画素の信号 電荷を垂直 C C Dに転送する事ができる。 このようにすれば読みだし電圧発生 回路を付加する必要がなく、 上記の読みだし電圧発生回路とシフ トレジスタと ― の干渉も防止できる。 The deepest reading of the power supply voltage of the shift register However, by setting the voltage to VR, the signal charges of all pixels or the odd (even) number pixels can be transferred to the vertical CCD. By doing so, it is not necessary to add a reading voltage generating circuit, and the interference between the above reading voltage generating circuit and the shift register can be prevented.
従属発明 1 3 ,クレーム 1 4 - 垂直 C C Dがクロック D V T _Gを備える 1 E / B転送センサにおいて、 各クロッ ク D V T Gは順次スィッチを介して 1相または 2相クロック電源に接続される。 ただし、 上記の順次スイッチは下流側から順番に動作するスィッチである。 こ の E Z B転送センサはクロック線駆動 1 E / B転送センサと呼ばれ-、 クレーム 9の E Z B転送センサはシフ トレジスタ駆動 E / B転送センサと呼ばれる。  Dependent inventions 13, claim 14-In a 1E / B transfer sensor in which the vertical CCD has a clock DVT_G, each clock DVTG is connected to a one-phase or two-phase clock power supply via a switch in sequence. However, the above-mentioned sequential switch is a switch that operates sequentially from the downstream side. This EZB transfer sensor is called a clock line driven 1 E / B transfer sensor-and the EZB transfer sensor in claim 9 is called a shift register driven EB transfer sensor.
従属発明 1 4 ，ク レーム 1 5  Dependent invention 14, claim 15
クレーム 1 4の好ましい 1実施例において、 垂直 C C Dの隣接する 2個のクロツ ク D V T Gはそれぞれ順次スイッチを介して第 1、 ，第 2相クロック電源に接続 され、 そして上記の隣接する 2個の順次スィッチは同時に動作する。 このよう にすれば順次スィツチを駆動するシフ トレジスタの転送段数を垂直 C C Dの D V T Gの半分にできる。 更に順次スィ ツチの動作'を簡単にでさる。  In a preferred embodiment of claim 14, two adjacent clocks of the vertical CCD, DVTG, are each connected to the first, second, and second phase clock power supplies via sequential switches, and The switches operate simultaneously. In this way, the number of transfer stages of the shift register for sequentially driving the switches can be reduced to half of the vertical CCD DVTGG. In addition, the operation of the switch can be performed easily.
従属発明 1 5 ，ク レーム 1 6  Dependent invention 15, claim 16
垂直 C C Dのクロック転送電極が順次スィツチを介してクロック ¾源線に接続 されるクロック線駆動 Eノ B転送センサにおいて、 各クロック転送電極は垂直 ¾送を実施する前に、 所定の電位を印加される。 そして、 各クロッ ク転送電極. は電源線から遮断され、 その後で、 順番に順次スィ ッチを介してクロ ッ ク電源 に接続される。 このようにすればクロック転送電極（クロック D V T Gまたは クロック N D V T G )の電位制御が非常に簡単になる。 垂直 C C I〕のクロック D V T Gが順次スイッチを介してクロッ ク電源線に接続される C I E B転送 センサはク口ック線駆動 1 Ε ,/ Β転送センサと呼ばれる。 この 1 Ε ./ Β転送セ ンサにおいて、 すべてのクロック D V T Gは垂直転送を実施する前に、 深い電 位 V Ηになる。 垂直 C C Dのクロッ ク N D V T Gが順次スィ ッチを介してク口 ヅ ク電源線に接続される C I EZB耘送センサはクロック線駆動 2 EZB転送セ ンサと呼ばれる。 この 2 E/B転送せンサにおいて、 垂直転送を-実施する前に、 奇（偶）数番目のクロヅク NDVT Gは深い電位 VHになり、 偶（奇）数番目のク ロヅク ND V T Gは浅い電位 V Lになる。 ただし、 クロック線駆動 2 EZB転 送センサの垂直転送ク口、、Jク電圧波形は複雑になる。 クロック線駆動 E/B転 送センサはクレーム 9に開示されるシフ トレジスタ駆動 E/B転送センサに比 ベてシフ トレジスタの出力抵抗を大きくできる力 その代わり伝送スィッチで ある順次スィツチが小さいチヤンネル抵抗を持つ必要がある。 1実施例におい て、'上記の垂直転送前に実施されるクロック転送電極の初期電位設定は専用の リセッ トスィツチを介して各ク口ヅク転送電極をリセッ ト電源線に接続する事 によって実施される。 共通転送電極 I Tセンサにおいて、 上記のクロック転送 電極をリセ、：/ トする回路手段によって、 听定のクロック転送電極に読みだし電 圧 VRを印加する事ができる。 In a clock-line-driven E-B transfer sensor in which the clock transfer electrodes of a vertical CCD are sequentially connected to a clock source line via a switch, a predetermined potential is applied to each clock transfer electrode before performing vertical transfer. You. Then, each clock transfer electrode is cut off from the power supply line, and thereafter connected to the clock power supply via the switch in order. This makes it very easy to control the potential of the clock transfer electrode (clock DVTG or clock NDVTG). The vertical CCI] clock DVTG is sequentially connected to the clock power supply line via a switch. A CIEB transfer sensor is called a clock line drive 1Ε /// transfer sensor. In this 1Ε. / Β transfer sensor, all clock DVTGs have a deep potential VΗ before performing vertical transfer. Vertical CCD clock NDVTG is sequentially opened via switch ヅ The CI EZB feed sensor connected to the clock power line is called the clock line driven 2 EZB transfer sensor. In this 2 E / B transfer sensor, before performing the vertical transfer, the odd (even) clock NDVT G becomes the deep potential VH, and the even (odd) clock ND VTG becomes the shallow potential. Becomes VL. However, the voltage waveform of the vertical transfer port of the clock line drive 2 EZB transfer sensor and the J voltage voltage become complicated. The clock-line driven E / B transfer sensor has the ability to increase the output resistance of the shift register compared to the shift register-driven E / B transfer sensor disclosed in claim 9, but instead uses a channel resistance, which is a transmission switch and has a smaller sequential switch. You need to have. In one embodiment, the initial potential setting of the clock transfer electrodes performed before the above vertical transfer is performed by connecting each of the block transfer electrodes to the reset power supply line via a dedicated reset switch. . In the common transfer electrode IT sensor, the readout voltage VR can be applied to the fixed clock transfer electrode by the circuit means for resetting and / or resetting the clock transfer electrode.
従属発明 1 6 ,クレーム 1 7  Dependent invention 16, Claim 17
クレーム 1 6の好ましい 1実施例において、 上記の垂直転送を実施する前に実 施されるクロ '；/ク転送電極の初期電位設定は順次スィツチを介して各クロック 転送電極に接続される垂直転送用クロック電源線によって実施される。 当然上 記の電位設定を実施する時に、 必要なすべての順次スィッチはシフ トレジスタ によってすべてターンオンされる。 本発明の電位設定技術は共通耘送電極 I T センサにおいて、 必要なクロ ':/ク転送電極に読みだし電圧 V Rを印加する事に よって、 画素から垂直 C CDに信号電荷を転送する時にも応用できる。 即ち、 必要な順次スィツチをターンオンして斩定のクロック線に読みだし電圧 VRを 印加すれば良い。 本発明によれば、 各クロック転送電極はシフ トレジスタによ て制御される順次スイッチを介してクロック線に接続するだけでよいので、 回 路構造と垂直転送ク口ック動作が簡単になる。  In a preferred embodiment of Claim 16, in the preferred embodiment, the initial potential setting of the clock transfer electrode is performed before performing the above vertical transfer, and the vertical transfer is sequentially connected to each clock transfer electrode via a switch. This is performed by the clock power supply line. Of course, when performing the above potential setting, all necessary sequential switches are all turned on by the shift register. The potential setting technology of the present invention is also applied to the transfer of signal charges from pixels to vertical CCDs by applying a read voltage VR to the required black transfer electrode in the common tiller electrode IT sensor. it can. That is, the necessary sequential switches may be turned on, and the read voltage VR may be applied to a predetermined clock line. According to the present invention, since each clock transfer electrode need only be connected to the clock line via a sequential switch controlled by the shift register, the circuit structure and the vertical transfer clock operation are simplified.
従属発明 1 7 ,ク レーム 1 8 . 本発明の EZBfe送センサの好ましい 1実施例において、 垂直 C CDのクロ ", ク転送電極にクロ'ック電圧を直接にまたはパッファ回路を介して印加するシフ トレジスタ、 または上記の順次スィツチを順番にターンオンするシフ トレジス タは撮像部の両側に配置される。 1実施例において、 奇（偶）数番目のクロッ ク 転送電極は左側に配置されたシフ トレジスタに直接または間接に接続されるか， または上記のシフ 卜レジスタによつて制御される順次スイッチを介してクロッ ク線に接続される。 同様に右側のシフ トレジスタは偶（奇）数番目のクロック転 送電極を制御する。 このようにすればシフ ト レジスタの設計が楽になる。 · 従属発明 1 8 ,クレーム 1 9 Dependent invention 17, claim 18. In one preferred embodiment of the EZBfe feed sensor of the present invention, a vertical CCD A shift register that applies a clock voltage to the clock transfer electrode directly or through a buffer circuit, or a shift register that turns on the above-mentioned sequential switches in order is disposed on both sides of the imaging unit. In one embodiment, the odd (even) clock transfer electrodes are connected directly or indirectly to a shift register located on the left or via a sequential switch controlled by the shift register described above. Connected to the clock line. Similarly, the right shift register controls the even (odd) number clock transfer electrodes. This makes the shift register design easier. · Dependent invention 18, claim 19
クレーム 1 8の 1実施例において、 各垂直 C C Dの 1行のクロック転送電極を 駆動する 1垂直走査線はその両側から駆動される。 ただし上記の 1垂直走査線 を分割してもよい。 このよう.にすれば順次スィツチまたはシフ トレジスタまた はバッファ回路を小さくできる。  In one embodiment of claim 18, one vertical scan line driving one row of clock transfer electrodes of each vertical CCD is driven from both sides. However, the above one vertical scanning line may be divided. In this way, the size of the switch or shift register or the buffer circuit can be reduced.
従属発明 1 9 ,ク レーム 2 0  Dependent invention 19, claim 20
E Z B転送センサを使用する T Vカメ ラの 1実施例において、 1 フィ ール ド期 間に総ての画素から信号電荷を出力し、 そして奇（偶）数番目のの画素から出力 された信号電荷を表示する事ができる。 このようにすればフィ一ルド残像を低 減でき、 ダイナミ ックレンジを改善できる。 勿論低照度時に出力された総ての 信号電荷を衷示する事も可能である。 In one embodiment of a TV camera using an EZB transfer sensor, signal charge is output from all pixels during one field period, and signal charge output from odd (even) numbered pixels. Can be displayed. In this way, afterimages in the field can be reduced, and the dynamic range can be improved. Of course, it is also possible to take into account all the signal charges output at low illuminance.
従属発明 2 0 ,ク レーム 2 1  Dependent invention 20, claim 2 1
E Z B転送 I Tセンサを使用する T Vカメ ラの 1実施例において、 低照度時に フレーム蓄積動作を実施し、 高照度時にフィールド蓄積動作を宾施しても良い。 たとえばこの蓄積動作の切り替えは垂直転送動作を開始する前に、 クロック転 送電極の半分または全部に読みだし電圧 V Rを印加する。 In one embodiment of the TV camera using the EZB transfer IT sensor, the frame accumulation operation may be performed at low illuminance and the field accumulation operation may be performed at high illuminance. For example, this switching of the storage operation involves applying a read voltage V R to half or all of the clock transfer electrodes before starting the vertical transfer operation.
従属発明 2 1 ,ク レーム 2 2  Dependent invention 2 1, claim 2 2
E Z B転送 I Tセンサの 1実施例において、 垂直 C C Dは 1 画素当たり 1個の 電位井戸を備え、 そして奇（偶）数画素行の信号電荷と、 ノ イズ電荷を交互に上 記の電位井戸に蓄積し、 そして上記の信号電荷とノィズ電荷を独立に転送する 事ができる。 このようにすれば信号電荷の S /N比、 特に暗電流とスメァノィ _ズに対する S / N比を改善できる。 In one embodiment of the EZB transfer IT sensor, the vertical CCD has one potential well per pixel, and alternately stores signal charges and noise charges of odd (even) pixel rows in the above potential wells. And independently transfer the signal charge and the noise charge. Can do things. S / N ratio of the thus them if signal charges can be improved the S / N ratio particularly dark current and Sumeanoi _'s.
従属発明 2 2 .ク レーム 2 3  Dependent invention 2 2. Claim 2 3
クレーム 2 2において、 信号電荷の垂直転送を実施した後で、 垂直 C C Dに残 留するノィズ電荷はクリアされるかまたは再配置される。 このようにすれば隣 接する信号電荷井戸とノ.ィズ電荷井戸のスメァノィズ電荷は大体等しくなるの で、 上記の 2個の電位井戸から出力される電圧を差し引けば、 スメァノイズを 除去できる。 上記のクリアは垂直帰線期間に垂直 C C Dを高速耘送する事によ- てまたは垂直 C C Dに隣接する ドレンに残留ノィズ電荷を転送する事によって 実施できる。 即ち、 本発明の C I E / B転送センサにおいて、 垂直転送の終わ りに電位井戸が実質的に半分になり、 その結果残留ノィズ電荷は次の垂直転送 時に、 奇（偶）数番目の電位井戸にだけ存在する。 したがつてこの残留ノイズ電 荷を除去するか，または再配置し、 そして隣接する 2個の電位井戸の出力信号 を差し引くことによって、 スメァノイズと残留ノィズ電荷は除去できる。  In claim 22, after performing the vertical transfer of the signal charge, the noise charge remaining in the vertical CCD is cleared or relocated. In this way, the smear noise charges of the adjacent signal charge well and the noise charge well become substantially equal, so that the smear noise can be removed by subtracting the voltages output from the two potential wells. The above clearing can be performed by high-speed tilling of the vertical CCD during the vertical retrace or by transferring the residual noise charge to the drain adjacent to the vertical CCD. That is, in the CIE / B transfer sensor of the present invention, the potential well is substantially halved at the end of the vertical transfer, and as a result, the residual noise charge is transferred to the odd (even) number potential well at the next vertical transfer. Only exists. Thus, by removing or relocating this residual noise charge, and subtracting the output signals of two adjacent potential wells, the smear noise and residual noise charge can be removed.
従属発明 2 3 ,クレーム 2 4  Dependent invention 2 3, Claim 2 4
1両素当たり垂直 C C Dが 2俩の電位井戸を備える C I E .ZB転送センサにお いて、 1画素の信号電荷を隣接する 2個の電位井戸.によって垂直転送する実施 例において、 または 1両素の信号電荷を残留ノイズ電荷を保持する電位井戸に よって垂直耘送する実施例において、 信号電荷に混入ォるスメァノィズ電荷は 大体一定になる ..従って、 垂直帰線期間に 1画素行（または飽和画素列の 1'画 素行分）のスメァノィズ電荷を記億し、 上記の信 電荷から上記のスメァノィ . ズ電荷を差し引く事によって、 スメァノィズは大幅に低減される。  In a CIE.ZB transfer sensor in which a vertical CCD per element has two potential wells, in an embodiment in which the signal charge of one pixel is vertically transferred by two adjacent potential wells, or In the embodiment in which the signal charge is vertically fed by the potential well holding the residual noise charge, the smear noise charge mixed into the signal charge is substantially constant .. Therefore, one pixel row (or saturated pixel) is provided during the vertical retrace period. The smear noise is significantly reduced by recording the smear noise charge of (1 'pixel row in the column) and subtracting the smear noise charge from the above-mentioned charge.
独立発明 2 ,ク レーム 2 5  Independent Invention 2, Claim 25
1画素当たり垂直 C C が 1電位井戸を備え、 そして 1垂直転送期間に全画素 の信号電荷を出力する C I E B車云送センサの垂直 C C Dにおいて、 残留ノィ ズ電荷を保持する奇（偶）数番目の電位井戸と、 残留ノイズ電荷を保持しない偶 (奇）数番目の電位井戸は大幅に異なるスメァノィズ電荷を持つ。 従ってクレー ム 2 4のように 1両素当たり垂直 C C Dが 2個の電位井戸を持つ必要がある欠 点が有った。 また 1画素行のスメァノィズを記憶して後から出力される各画素 行の信号から差し引く従来技術において、 スメァノィズが大きいと強い光を受 け取り飽和信号電荷を発生する画素（飽和画素）から出力される信号電圧が小さ くなる欠点が有った。 本発明は上記の問題を改善する事を目的とする。 上記の 目的を達成する為に、 本発明は少なく とも飽和画素列の 1画素行分のスメァノ ィズを記憶し、 そして上記の飽和画素列の一部の画素から発生する信号から上 記の記億されたスメァノィズを差し引き、 そして飽和画素列の他の画素から発 生する信号から上記の記億されたスメァノィズを差し引かない事を特徵とする。 このようにすれば、 1 フィールド期間にすべての画素から信号電荷を出力でき る C I E Z B転送センサを作る事ができる。 そして最大信号電圧が小さくなら ない C C Dエリァセンサを作る事ができる。 スメァノィズ電荷は主として強い 光を受け取る飽和画素の下または橫を電位井戸が通過する時に、 上記の電位井 戸に混入する。 従って飽和画素の下または横を通過する電位丼戸から発生する 信号から、 記億されたスメァノ イズを差し引き、 そして飽和画素列の他の電位 井戸から発生する信号から上記のスメァノ.ィズを差し引かない事を特徵とすろ。 In a vertical CCD of a CIEB vehicle transport sensor, in which a vertical CC has one potential well per pixel and outputs signal charges of all pixels in one vertical transfer period, an odd (even) number CCD holding residual noise charge is provided. Potential wells and even-numbered potential wells that do not retain residual noise charge have significantly different smears charges. Therefore clay There was a drawback in that a vertical CCD per element had to have two potential wells, as shown in FIG. Also, in the conventional technology in which the smearing of one pixel row is stored and subtracted from the signal of each pixel row output later, if the smearing is large, the pixel receives strong light and generates a saturated signal charge and is output from a pixel (saturated pixel). There is a disadvantage that the signal voltage becomes small. The present invention aims to remedy the above problems. In order to achieve the above object, the present invention stores at least one pixel row of a saturated pixel column, and reads the above signal from signals generated from some pixels of the saturated pixel column. It is characterized in that the subtracted smears are subtracted, and the above-mentioned recorded smears are not subtracted from signals generated from other pixels of the saturated pixel sequence. This makes it possible to create a CIEZB transfer sensor that can output signal charges from all pixels in one field period. And it is possible to make a CCD area sensor whose maximum signal voltage does not decrease. The smeared charges are mixed into the above potential well mainly when the potential well passes below or under a saturated pixel receiving strong light. Therefore, the recorded smear noise is subtracted from the signal generated from the potential bowl passing under or beside the saturated pixel, and the above-mentioned smear noise is subtracted from the signal generated from the other potential well of the saturated pixel column. Special features are not available.
従属発明 1 ，ク レーム 2 6  Dependent invention 1, claim 26
1 ¾施例において、 飽和画素から発生する信号から上^の記憶:されたスメァノ ィズは減算しない。 その結果最大信号電圧は減少しな 、。  1 に お い て In the embodiment, the above stored memory noise is not subtracted from the signal generated from the saturated pixel. As a result, the maximum signal voltage does not decrease.
従属発明 2 ,ク レーム 2 7  Dependent invention 2, Claim 27
1実施例において、 |§和.画素列の飽 ¾画素よりも下流の一部のまたは全部の画 素から発牛-する ί· '号から上記の記億されたスメァノ ィズを減算しない。 垂直 C C Dが 1画素当たり 1電位丼戸を持ち、 各電位井戸が異なろ画素の信号電荷を 転送する C I Ε Ζ Β転送センサ（C I Ε Ζ Β転送センサは単に Ε Ζ Β転送セン サと略称される事も有る。 ）は飽和画素よりも下流の画素（下流画素と略称され る。 ）の内、 奇（偶）数番目の画素の信号電荷から上記の記憶されたスメァノィ ズを減算する。 これは飽和画素よりも下流の電位井戸の内、 奇（偶）数番目の電 位井戸にスメァノィズ電荷が混入するからである。 即ち飽和画素よりも下流の 電位井戸の内、 偶（奇）数番目の電位井戸は垂直転送期間の最初に作られる為に、 飽和画素の下または橫を通過しない。 In one embodiment, the above-described smear noise is not subtracted from the symbol “発” which is generated from some or all of the pixels downstream of the pixel in the pixel row. A vertical CCD has one potential bowl per pixel, and each potential well transfers the signal charge of the pixel if it is different. CI Β Ζ Β Transfer sensor (CI Β Ζ Β セ ン サ セ ン サ Β セ ン サ セ ン サ Β Β セ ン サ セ ン サ) ) Subtracts the stored smear noise from the signal charges of the odd (even) number pixels among the pixels downstream of the saturated pixel (abbreviated as “downstream pixels”). This is the odd (even) number of potential wells downstream of the saturated pixel. This is because smeared charges are mixed into the well. That is, among the potential wells downstream of the saturated pixel, even (odd) potential wells are formed at the beginning of the vertical transfer period and do not pass below the saturated pixel or 橫.
従属発明 3，クレーム 2 8  Dependent invention 3, Claim 2 8
1実施例において、 飽和画素を持たない画素列（非飽和画素列）の画素から発生 する信号から上記の記億されたスメァノィズを減算しない。 このようにすれば ランダムノイズを低减できる。 ただし飽和画素列に隣接する非飽和画素列はス メァノイズを持つ場合があるので、 上記の減算を実施しても良い。  In one embodiment, the above-mentioned stored noise is not subtracted from signals generated from pixels in a pixel row having no saturated pixel (non-saturated pixel row). In this way, random noise can be reduced. However, since the unsaturated pixel row adjacent to the saturated pixel row may have smear noise, the above-described subtraction may be performed.
独立発明 3 ,クレーム 2 9 . ' 独立発明 2のスメァノィズ低減技術は独立発明 1の EZB転送センサのスメァ ノィズを効果的に低減する。 しかし独立発明 2の問題はビデオ帯域で動作する 高価な A/D変換器と DZ A変換器を必要とする事である。 その結果固体撮像 装置の価格は増加し、 競争上非常に不利になる。 本発明は上記の問題を改善す る為に、 垂直帰線期間に水平 C CDを低速で駆動し、 そして垂直 C CDから転 送されたスメァノィズ電荷を低速で出力する事を特徵とする。 このようにすれ ば、 低逮 AZD変換器を使用できるので、 コストは大幅に低减できる。  Independent Invention 3, Claim 2 9. 'The independent noise reduction technology of Independent Invention 2 effectively reduces the noise of the EZB transfer sensor of Independent Invention 1. However, the problem of independent invention 2 is that it requires an expensive A / D converter and DZA converter that operate in the video band. As a result, the price of the solid-state imaging device increases and becomes very disadvantageous in terms of competition. In order to solve the above-mentioned problem, the present invention is characterized in that the horizontal CCD is driven at a low speed during the vertical flyback period, and the smear noise charges transferred from the vertical CCD are output at a low speed. In this way, the cost can be significantly reduced because a low-arrest AZD converter can be used.
従属発明 1 ,ク レーム 3 0 Dependent invention 1, Claim 30
1実施例において、 Nビッ トの遂次比铰形 AZD変換器が使用されろ。 遂次比 校形 AZD変換器はビデオ帯域並列 A ZD変換器に比べて非常に安価である。 例えば、 安価な 6ビッ トの遂次比铰形 AZD変換器を使用する実施例において、 垂直帰線期間内の約 7 平走査期間に等しい期間に 1水平画素行のスメァノ ィ ズが AZD変換される。  In one embodiment, an N-bit sequential ratio AZD converter is used. The AZD converter is very inexpensive compared to the video band parallel AZD converter. For example, in an embodiment using an inexpensive 6-bit successive-ratio AZD converter, the smears of one horizontal pixel row are AZD-converted during a period equal to about 7 horizontal scanning periods in the vertical blanking period. You.
従属発明 2，ク レーム 3 1  Dependent invention 2, Claim 3 1
1実施例において、 垂直走査期間に遂次比较形 AZD変換器に内蔵される DZ Λ変換器によって、 デジタルメモリから再生されたスメァノィズは D/ A変換 される。 このようにすれば DZA変換器を省略できる。  In one embodiment, the smear noise reproduced from the digital memory is D / A-converted by the DZ converter in the successive approximation AZD converter during the vertical scanning period. In this way, the DZA converter can be omitted.
独立発明 4，クレーム 3 2 独立発明 1 に開示される E Z B転送センサは実質的に従来の 2倍の垂直画素密 度を持つ事ができる。 しかし、 有力な 1形式であるフレーム転送センサ（F T センサ）に上記の E / B転送を応用する時に新しい問題が発生する。 即ち、 一 般的に垂直 C C Dはバルクチャンネルとその上方に配列されたオーバーラップ する転送電極を備えるが、 本発明の E ZB転送センサにおいて、 実質的に各転 送電極が 1画素を構成するので、 同じ色信号を発生する総ての転送電極の光透 過率を等しくする必要がある事である。 -そして本発明の E Z B転送センサにお いて、 各ク口ッ ク転送電極はシフ ト レジスタ、 または上記のシフ ト レジスタに よつ T制御されるバッファ回路、 または順次スィッチを介してクロ 'ソ ク線によつ てそれぞれ独立に駆動される。 その結菓垂直転送速度は各垂直走査線の充放電 速度に依存し、 上記の充放電速度はシフ トレジスタまたはバ' /ファ回路または 順次スィ ツチの抵抗と垂直走査線の抵抗の和と、 垂直走査線の容量の積に依存 する。 その結果垂直走査線のライン抵抗を低減する事が非常に重要になる。 し かし低いライン抵抗を持つ垂直 C C Dのクロ 'ソク転送電極は一般に悪い光透過 率（特に悪い青感度）を持つ。 本発明の目的は上記の問舉を改善する事である。 上記の問題を改善する為に、 本発明は垂直 C C Dの隣接する 2個の転送電極を 垂直 C C Dのチヤンネル領域の上方または垂直 C C D間のチヤンネルス トップ 領域の上方で接続して実質的に 1転送電極を構成し、 そして上 S己の第 1 の転送 電極に厚い膜厚を与え、 そして上記の第 2の転送電極に薄い膜厚を与える事を 特徵とする。 1転送電極を 2分割する事によって、 特に第 2転送電極は高いラ ィン抵抗を持つ。 しか-し第 1転送電極と第 2転送電極が撮像領域の 方で接続 すろ事によって、 第 2転送電極の等価的ライン抵抗は小さくできる。 また 2個 の転送電極によって構成された上記の等価的転送電極はそれぞれ等しい等価率 を持つ。 本発明において第 2転送電極の膜厚はできる限り薄くできる。 . Independent invention 4, Claim 3 2 The EZB transfer sensor disclosed in the independent invention 1 can have substantially twice the vertical pixel density as the conventional one. However, a new problem arises when the above E / B transfer is applied to a leading type of frame transfer sensor (FT sensor). That is, a vertical CCD generally includes a bulk channel and an overlapping transfer electrode arranged above the bulk channel. However, in the EZB transfer sensor of the present invention, since each transfer electrode substantially constitutes one pixel. However, the light transmittance of all transfer electrodes that generate the same color signal must be equal. -And in the EZB transfer sensor of the present invention, each of the close transfer electrodes is connected to a shift register, a buffer circuit controlled by the above shift register, or a cross switch via a sequential switch. Each is independently driven by a line. The confection vertical transfer rate depends on the charge / discharge rate of each vertical scan line, and the above charge / discharge rate is the sum of the resistance of the shift register or buffer circuit / sequential switch and the resistance of the vertical scan line, and the vertical Depends on the product of scanning line capacitance. As a result, it is very important to reduce the line resistance of the vertical scanning lines. However, vertical CCD transfer electrodes with low line resistance generally have poor light transmittance (particularly poor blue sensitivity). An object of the present invention is to improve the above question. In order to improve the above-mentioned problem, the present invention connects two adjacent transfer electrodes of a vertical CCD above the channel region of the vertical CCD or above the channel stop region between the vertical CCDs, thereby forming substantially one transfer electrode. It is characterized in that a thick film is given to the first transfer electrode of the upper self and a thin film is given to the second transfer electrode. By dividing one transfer electrode into two, especially the second transfer electrode has a high line resistance. However, by equivalently connecting the first transfer electrode and the second transfer electrode in the imaging region, the equivalent line resistance of the second transfer electrode can be reduced. The above-mentioned equivalent transfer electrodes formed by two transfer electrodes have the same equivalent ratio. In the present invention, the thickness of the second transfer electrode can be made as thin as possible. .
従属発明 1 ,ク レーム 3 3  Dependent invention 1, Claim 3 3
1実施例において、 チヤ ンネルストップ領域の上方で第 1 と第 2転送電極は第 3の電極（例えばアルミ二ゥム）を介してまたは直接に接続される。 このようにすれば接続面積を大きく設定でき、 画素感度は低下しない。 1実施 例において低抵抗の第 1転送電極はチヤンネルストップ領域の土方で、 チャン ネル領域の上方よりも大きな垂直幅を持つ。 このようにすれば上記の接続面積 が広くなり、 ライン抵抗が小さくなる。 方向性転送電極（DVT G)を作るため に、 上記の第 1または第 2転送電極をマスクとしてチヤンネル領域に所定のィ オン注入する事も可能である。 各独立発明の他の特徵と効果が以下に説明され るゥ 以下の説明において、 インバーターで構成された 2相シフ トレジスタが使 用されるが、 インバーターで構成された 3相、 4相シフ トレジスタの使用も可 能であり、 BBD， C CDシフ トレジスタの使用も可能である。 In one embodiment, the first and second transfer electrodes are connected via a third electrode (eg, aluminum) or directly above the channel stop region. In this way, the connection area can be set large, and the pixel sensitivity does not decrease. In one embodiment, the low resistance first transfer electrode has a greater vertical width at the side of the channel stop region than above the channel region. In this way, the connection area is increased and the line resistance is reduced. In order to form a directional transfer electrode (DVT G), a predetermined ion can be implanted into the channel region using the first or second transfer electrode as a mask. Other features and effects of each independent invention are described below. In the following description, a two-phase shift register composed of an inverter is used, but a three-phase or four-phase shift register composed of an inverter is used. Use is possible, and BBD and CCD shift registers can be used.
以下に各独立発明の他の特徵と効果が捕足される。 独立発明 1の好ましい 1実 施例に関して、 図 4， 5， 6はシフ トレジスタ（S R)駆動形 1 E/B転送センサ がダイナミ ックシフ ト レジスタ（D S R)を使用できる事を開示する。 この事実 は重要である。 即ち。 上記の D S Rのプリチャージ動作によって、 垂直 C CD の DVT Gは深い電位 VHに充電され、 動作が非常に簡単になる。 そして D S Rは CMO S— S Rを採用しなくても消費電力を減らす事ができ、 そして製造 工程を簡単にする。 従って D S Rを使用する EZB転送センサ構造に関するク レームを本発明者は留保す ¾。 そして、 独立究明 1の好ましい 1実施例に関し て、 本発明の EZB転送形 C CDエリァセンサは 1水平期間に隣接する 2画素 ί丁を独立に出力する単扳カラ一 TVカメラまたは磁気カメラに好適である。 こ の事実は重要である。 なぜなら従来の単板 C CDカラー TVカメラは少ない水 平画素数を持つので、 輝度または色信号の解像度が悪か όた。 また従来の C CIn the following, other features and effects of each independent invention are captured. Regarding a preferred embodiment of Independent Invention 1, FIGS. 4, 5, and 6 disclose that a shift register (SR) driven 1 E / B transfer sensor can use a dynamic shift register (DSR). This fact is important. That is. By the above DSR precharge operation, the DVT G of the vertical CCD is charged to the deep potential VH, and the operation becomes very simple. And DSR can reduce power consumption without using CMO S—SR and simplify the manufacturing process. Therefore, the inventor reserves a claim regarding the EZB transfer sensor structure using DSR. In addition, with respect to a preferred embodiment of Independence Investigation 1, the EZB transfer type CCD area sensor of the present invention is suitable for a single color TV camera or a magnetic camera which independently outputs two adjacent pixels in one horizontal period. is there. This fact is important. Because the conventional single-chip CCD color TV camera has a small number of horizontal pixels, the brightness or color signal resolution was poor. Conventional C C
D磁気カメラにおいて、 2フィールド期間の撮影によって 1 フレーム画像を構 成ォる為に、 動く被写体に対する解像度が悪かった。 本発明によれば隣接する 2画素行を 1水平走査期間に独立に出力できるので、 この悶題は解決される。 従来上記の問題を解決するために、 垂直 C C Dの水平転送段数を 2 ίきにするま たは垂直 C C D数を 2倍にするなどの方法が実施されていた。 これらの方法は 構造と製造工程と S Ν比において悪い結果をもたらす η 従って、 隣接 2画素行 ZH出力動作を実施する EZB転送 C CDエリアセンサ関するクレームを発明 者は留保する。 In the D magnetic camera, the resolution for a moving subject was poor because one frame image was composed by shooting for two field periods. According to the present invention, since two adjacent pixel rows can be output independently during one horizontal scanning period, this problem is solved. Conventionally, in order to solve the above problem, methods such as increasing the number of horizontal transfer stages of the vertical CCD to two or doubling the number of vertical CCDs have been implemented. Η Thus, two adjacent pixel rows these methods leads to bad results in the structure and fabricating process and S New ratio The inventor reserves a complaint regarding the EZB transfer CCD area sensor that performs the ZH output operation.
更に独立発明 1の C I EZB転送センサの説明を以下に追加する。 従来の EZ B転送は実質的に各クロック電圧がそれぞれ対称的である N相クロック転送方 式であり、 Nの增加は転送速度に反比例するので、 1水平帰線期間に 1画素行 以上の信号電荷を出力する必要がある C CDエリァセンサの垂直 C CDに使用 できなかった。 本発明の C I EZB転送方式は非常に多くのクロック相を使用 する点において従来の EZB転送方式と同じであるが、 C C Dの最初の半分の 画素行の信号電荷を出力するまで上記のクロ、ソク電圧を非対称クロック電圧と し、 その後で実質的に 1 または 2または 4相クロ、:/ク電圧とする点に特徴があ る。 その結果転送する前に一斉に入力されている C C Dの信号電荷は順番に出 力される。 従って本発明の C I EZB転送方式は S P S形 C CD構造の出力用 C CDまたは C CDラインセンサなどにも応用できる。 更に上記の C I E/B 転送方式を C CDエリァセンサの垂直転送に使用する事、 その実際の垂直転送 動作、 その好ましいまたは必要な回路構成、 その新規な応用と効果などは公知 では無かった。 本発明者は C CDエリアセンサにおいて、 1水平期間に 1個ま たは 2個の空の P W (電位井戸）を注入し、 そして注人された上記の の P Wを 1 水平期間にすこしだけ逆転送すれば良い事に気がついた。 本発明によれば同 じ V T G (垂直 C C Dの転送電極）数を持つ垂直 C C Dによって従来より 2倍の 垂直画素数を確保できる。 なお、 本明細書において、 0 丁 0(方向性¥丁 0) はその下に P B (電位障壁）と PW (電位井戸）を持つ V T Gであり、 N D V T G (非方向性 V T G)はその下に P Bと P Wのどちらかを持つ V T Gである。 D V T Gを使用する本発明の C I EZB転送法は 1 EZB転送と呼ばれ、 NDVT Gを使用するそれは 2 Eノ B転送と呼ばれる。 そして浅い電位 V Lは信号電荷 を蓄稜しない電位であり、 深い電位 VHは信号電荷を蓄積する電位である。 即 ち、 Nチャンネル C C Dにおいて、 浅い電位 V Lはより負のクロック電圧であ り、 深い電位 V Hはより正方向のクロック電圧である。 本発明は I Tセンサ（ィ ンタライン転送エリァセンサまたはフルフレーム転送形 F Tセンサ（フレーム 転送エリアセンサ）の垂直 C CDに ΪΕ用できるが、 垂直 C CDと水平 G CDの 間にバッファ C CD (蓄積 C CD)を備える通常の F Tセンサの垂直 C CDにも 応用できる。 バッファ C G Dを備える通常の F Τセンサのバッファ C CDを垂 直 C CDと同じシフ トレジスタで駆動する事も可能であるが、 ·この実施例にお いて、 垂直 C CDの VT ^だけ転送前にリセッ トする事によって垂直 C CDだ け C I EZB転送を実施し、 バッファ C CDは 2相または 4相転送を実施する。 本発明の 2 EZB転送を実施する F Tセンサにおいて、 P Bと PWの初期位置 を変更する事によって、 インタレースを実施する事ができる。 ' Further description of CI EZB transfer sensor of independent invention 1 is added below. The conventional EZ B transfer is an N-phase clock transfer method in which each clock voltage is substantially symmetrical. Since the addition of N is inversely proportional to the transfer speed, signals of one pixel row or more in one horizontal blanking period It could not be used for vertical CCD of CCD area sensor which needs to output electric charge. The CI EZB transfer method of the present invention is the same as the conventional EZB transfer method in using a very large number of clock phases, but the above-described clock and signal are output until the signal charge of the first half pixel row of the CCD is output. It is characterized in that the voltage is an asymmetrical clock voltage, and subsequently, a one-, two-, or four-phase clock voltage is used. As a result, the CCD signal charges that are input all at once before transfer are output in order. Therefore, the CI EZB transfer method of the present invention can also be applied to an SPS type CCD structure output CCD or CCD line sensor. Furthermore, the use of the above-mentioned CIE / B transfer method for vertical transfer of a CCD area sensor, its actual vertical transfer operation, its preferred or necessary circuit configuration, its novel application and effect, etc., were not known. In the CCD area sensor, the inventor injects one or two empty PWs (potential wells) in one horizontal period, and inverts the injected PWs slightly in one horizontal period. I noticed that I should send it. According to the present invention, a vertical CCD having the same number of VTGs (transfer electrodes of a vertical CCD) can secure twice the number of vertical pixels as compared with the conventional case. In this specification, 0 (directivity 0) is a VTG having PB (potential barrier) and PW (potential well) below it, and NDVTG (non-directional VTG) is a PTG below it. VTG with either PW or PW. The CI EZB transfer method of the present invention using DVTG is called 1 EZB transfer, and that using NDVT G is called 2 ENO B transfer. The shallow potential VL is a potential that does not accumulate signal charges, and the deep potential VH is a potential that accumulates signal charges. That is, in an N-channel CCD, the shallow potential VL is a more negative clock voltage, and the deep potential VH is a more positive clock voltage. The present invention relates to an IT sensor It can be used for the vertical CCD of an interline transfer area sensor or a full frame transfer type FT sensor (frame transfer area sensor), but a normal FT sensor with a buffer CCD (accumulated CCD) between the vertical CCD and the horizontal G CD It can be applied to vertical CCDs. It is possible to drive the buffer CCD of a normal F sensor with a buffer CGD with the same shift register as the vertical CCD, but in this embodiment, only the VT ^ of the vertical CCD is transferred before By resetting, the vertical CCD performs CI EZB transfer only, and the buffer CCD performs 2-phase or 4-phase transfer. In the FT sensor that performs 2EZB transfer according to the present invention, interlacing can be performed by changing the initial positions of PB and PW. '
独立発明 2 (クレーム 2 5 )は独立発明 1 (クレーム 1 )の固有のスメァノィズパ ターンの抑圧に非常に効果があり、 両者を一緒に使用する事によって大きなダ イナミ ックレンジと小さなスミァノィズを持つエリァセンサを製造できる。 独 立発明 3 (クレーム 2 9)は独立発明 2の欠点で.ある回路の複雑化とコストの增 加を抑圧するので、 独立発明 1， 2 , 3を一緒に実施する事によって、 実用性の 高いエリァセンサを製造する事ができる。 独立発明 1を使用する 1 EZB転送 形 F Tセンサを従来の 2層電極技術で製造する時に、 奇（偶）数行の画素感度と 偶 数行の画素感度が異なるので、 大きなパターンノィズが発生する欠点が あるつ 独立究明' 1 (ク レーム 3 2)を使用する事によって、 上記の欠点が改善さ れ、 良い性能を持つ FTセンサを製造できる。 Independent invention 2 (claim 25) is extremely effective in suppressing the unique smear noise pattern of independent invention 1 (claim 1) .By using both together, an area sensor having a large dynamic range and a small smear noise is manufactured. it can. Independent invention 3 (claim 29) is a drawback of independent invention 2 because it suppresses the complexity of the circuit and increases the cost, so that by implementing independent inventions 1, 2, and 3 together, A high area sensor can be manufactured. Using Independent Invention 1 1 When manufacturing an EZB transfer type FT sensor using the conventional two-layer electrode technology, the pixel sensitivity of odd (even) rows is different from the pixel sensitivity of even rows, resulting in large pattern noise. By using Independent Investigation 1 (Claim 3 2), the above-mentioned disadvantages can be improved and a FT sensor with good performance can be manufactured.
「発朋を実施するための最良の形態 」 . -"The best way to carry out the excitement"-
¾ 1 と図 2は独立発明 1に開示される連続注入 Eノ B転送セ-ンサの 1実施例ブ ロック回路図である。 図 1において、 撮像領域 1に水平方向に配置された垂直 走査線 3は垂直転送ク口ヅク電圧を発生するシフ トレジスタ（V S Rと略称さ れる ) 2 A, 2 Bによって駆動される。 シフ トレジスタと垂直走査線の問に、 電流増幅用バツフアインバ一タを配置できる事は当然であるので、 以下におい て、 垂直走査線 3をシフ.トレジスタによって直接に駆動する実施例を説明する c 垂し 走查锒 3は一般に垂直 G CDの転送電極と一体化しているので、 両者は同 じ符号を与えられる。 図 1において、 各垂直走査線 3はシフ ト レジスタ 2 Aと 2 Bによって駆動されるので、 その充電と放電は高速になる。 2 Aと 2 Bは同 じ動作をする。 3を半分に分割しても良い。 水平 C C D 5 Aは転送電極 4 Aに よって、 垂直 C CDまたはバッファ C C Dに接続される。 水平 C CD 5 Bは転 送電極 4 Bによって、 水平 C C D 5 Aに接続される。 図 2において、 奇（偶）数 番目の垂直走査線 3 Aはシフ トレジスタ 2 Aの出力接点にそれぞれ接続され、 偶（奇）数番目の垂直走査線 3 Bはシフ ト レジスタ 2 Bの出力接点にそれぞれ接 続される。 図 1 , 2において、 画素とバッファ CCDと垂直 C CDは省略され ている。 図 3 (Aから F-)において、 図 1の構造を ί つ 1 E/B転送動作が説明 される。 ただし、 2 Β.4 Β.5 Βは省略される。 垂直 C CD 6は DV T G 3 CU から Ζ)を持つ。 3 Ζと 5 Αの間に転送電極 4 Αが配置される。 3 Zと 4 Aの 間にバツファ C C Dを配置する事は可能である。 転送を開始する前に 3 から 3 Zは深い電位 V Hに充電され、 その下の各電位井戸に信号電荷 Q 1から Q 6 が蓄積される。 もちろん信号電荷は I Tセンサにおいて画素列から注入さ.れ、 FTセンサにおいて、 光によって、 注入される。 図 3 Aにおいて、 3 Zが浅い 電位 V Lになり、 Q 1は 3 Zの下から 4 Aを介して、 水平 C C D 5 Aに転送さ れる。 4 Aと 5 Aのクロック動作は周知であり、 詳細な説明は省略される。 図 3 Bにおいて、 3 Zは深い電位 VHになり、 3 Yは浅い電位 V Lになる。 そし て Q 2は 3 Zの下に耘送される。 図 3 Cにおいて、 37,と 3 は浅ぃ電位 し になり、 3 Yと 4 Aは深い電位 V Hになり、 Q 2は水平 C C D 5 Aに転送され、 Q 3は 3 Y.の下に転送される 9 同様に図 3 Dから図 3 Fの動作によって各信号 II荷 Q 3から Q 6は独立に垂直転送される。 垂直走査線 3 (Aから Z)はシフ ト レジスタ 2 Aの各出力接点にそれぞれ接続される。 図 3 (Aから F)において、 シフ ト レジスタ 2 Aの入力端 2 Cから転送パルス情報である浅い電位 V Lと深 い電位 VHを交互に注入する事によって、 上記の垂直転送を実施できる事が理 解される。 1水平期間に 1両素行を出力する 1実施例において、 図 3 Aと図 3 B、 または図 3 Bと図 3 Cの転送動作が水平帰線期間に実施され、 そして水平 走查期間に水平 C CD 5 Aは信号電荷を水平転送する。 図 3 (Aから F)におい て、 0で表される空の電位井戸（PW)が 2 PWピッチだけ逆転送される毎に、 次の空の PWが注入される事が理解される。 図 3 (Aから F)の 1 EZB転送に おいて、 空の PWは浅い電位 V Lから深い電位 V Hにされた後で、 信号電荷を 受け取る事が望ましい。 浅い電位 V Lを持つ D V T Gを深い電位 VHに再び充 電する良い方法は上記の D VT Gに隣接する上流の D VT Gに浅い電位 VLを 印加する前に、 すべての DVT Gに深い電位 VHを印加する事である.。 シフ ト レジスタ 2 Aの出カインバータ（またはバッフアインバータ）を充電期間と放電 期間を持つレシオレス形ィンバータにすれば、 上記の動作は簡単に実施できる。 図 4 (Aから F)に図 2の構造を持つ 1 EZB転送動作が説明される。 図 4 (A から F)は図 3 (Aから F)と同じ動作伏態を持つ。 ただし図 4 (Aから F)にお いてシフトレジスタ 2 Aと 2 Bは交互に深い電位 VI-Iになる。 2 Aと 2 Bの上 記の動作はシフ トレジスタの出力インバータをダイナミ ック形特にレシオレス 形にすれば簡単に作る事ができる。 FIG. 1 and FIG. 2 are block circuit diagrams of an embodiment of the continuous injection E / B transfer sensor disclosed in the independent invention 1. In FIG. 1, vertical scanning lines 3 arranged in the imaging area 1 in the horizontal direction are driven by shift registers (abbreviated to VSRs) 2 A and 2 B that generate a vertical transfer cut-off voltage. The question of the shift register and a vertical scanning line, so that you can place Batsufuainba one motor current amplification is of course, less Te smell, c vertical for explaining an embodiment of driving directly the vertical scanning lines 3 by shift. Torejisuta Since Run 3 is generally integrated with the vertical G CD transfer electrode, The same sign. In FIG. 1, each vertical scanning line 3 is driven by shift registers 2A and 2B, so that its charging and discharging become faster. 2A and 2B operate the same. 3 may be divided in half. The horizontal CCD 5A is connected to the vertical CCD or buffer CCD by the transfer electrode 4A. The horizontal CCD 5B is connected to the horizontal CCD 5A by the transfer electrode 4B. In FIG. 2, the odd (even) th vertical scanning line 3A is connected to the output contact of the shift register 2A, respectively, and the even (odd) vertical scanning line 3B is connected to the output contact of the shift register 2B. Connected to each other. In FIGS. 1 and 2, the pixel, the buffer CCD, and the vertical CCD are omitted. In FIG. 3 (A to F-), one E / B transfer operation is described using the structure of FIG. However, 2 Β.4 Β.5 Β is omitted. Vertical CCD 6 has DV TG 3 CU from). Transfer electrode 4 Α is placed between 3 Ζ and 5 Α. It is possible to place a buffer CCD between 3Z and 4A. Before starting the transfer, 3 to 3 Z are charged to the deep potential VH, and signal charges Q 1 to Q 6 are stored in each potential well below. Of course, the signal charge is injected from the pixel array in the IT sensor, and is injected by light in the FT sensor. In FIG. 3A, 3Z becomes a shallow potential VL, and Q1 is transferred to the horizontal CCD 5A via 4A from below 3Z. 4 A and 5 A clock operations are well known and will not be described in detail. In FIG. 3B, 3Z has a deep potential VH and 3Y has a shallow potential VL. And Q 2 is tilled below 3 Z. In Figure 3C, 37, and 3 become shallow potential, 3Y and 4A become deep potential VH, Q2 is transferred to horizontal CCD 5A, and Q3 is transferred below 3Y. Q 6 from the signal II load Q 3 by 9 Similarly, FIG. 3 F operation from Figure 3 D is is the vertical transfer independently. Vertical scan line 3 (A to Z) is connected to each output contact of shift register 2A. In Fig. 3 (A to F), the above vertical transfer can be performed by alternately injecting the transfer pulse information, the shallow potential VL and the deep potential VH, from the input terminal 2C of the shift register 2A. It is understood. In one embodiment in which one row is output in one horizontal period, in one embodiment, the transfer operation shown in FIG. 3A and FIG. 3B or FIG. 3B and FIG. During the scanning period, the horizontal CCD 5 A transfers the signal charge horizontally. In Fig. 3 (A to F), it is understood that the next empty PW is injected every time the empty potential well (PW) represented by 0 is reversely transferred by 2 PW pitches. In the 1 EZB transfer shown in Fig. 3 (A to F), it is desirable that empty PWs receive signal charges after being changed from shallow potential VL to deep potential VH. A good way to recharge a DVTG with a shallow potential VL to a deep potential VH is to apply a deep potential VH to all DVT Gs before applying the shallow potential VL to the upstream D VTG adjacent to the above D VTG. Is to apply. If the output inverter (or buffer inverter) of shift register 2A is a ratioless inverter having a charge period and a discharge period, the above operation can be easily performed. FIG. 4 (A to F) illustrates one EZB transfer operation having the structure of FIG. Figure 4 (A to F) has the same operational state as Figure 3 (A to F). However, in Fig. 4 (A to F), shift registers 2A and 2B alternately have a deep potential VI-I. The above operation of 2A and 2B can be easily made by making the output inverter of the shift register a dynamic type, especially a ratioless type.
好ましい 1実施例において、 片方のシフ ト レジスタの充電動作が他のシフ トレ ジスタの評価（放電）動作より早く始まる事が好ましい。 ダイナミ ツク形特にレ シォレス形バッフアインバータを使用する実施例においても、 図 3 (Aから F) と図 4 (Aから F)のクロック動作は可能である。 ただし、 インバータの充電動 作はその出力接点に深い電位 VHを与えるク口ック動作であり、 その放電動作 はその出力接点に浅い電位 V Lを印加するクロック動作である。 本発明の 1 E /Bg送が非常に簡単なク.口、ソク動作によって実施で.きる事がわかる。 図 3 (A から F)と図 4 (Aから F)において、 信^電荷の転送の後で再び各 D V T Gに 深い電位 VHを印加すれば、 次の 1 EZB転送を実施できる。 図 5は図 4のシ フ 卜レジスタの 1実施例等価回路図である。 勿論図 3のシフ ト レジスタも図 5 と基本的に同じ構造を持つ事ができる， 垂直走査線 3 Z , 3 Y， 3 Xはシフ トレ ジスタ 2 Λ.2 Βの出力インバータ 1 1 Αの出力接点 1 2 A, 1 2 A'に直接接 統される。 勿論、 両者をスィッチによって接続しても良い。 1 1 Aは充電スイツ チ 8 Aと評価スィツチ 9 Aと放電スイッチ 1 ,0 Aを持つダイナミ ヅクインバー タである。 2値の出力インバータを接続する接続用インバータ 1 1 Bは放電ス イッチ 1 0 Bと評価スィッチ 9 Bと充電スィツチ 8 Bを持つ。 1 1 Aと 1 1 B は接続スィツチ 7 Aと 7 Bによって交互に接続される。 図 6は図 5の 2相シフ トレジスタ 2 A， 2 Bの 1実施例動作図である。 ただし、 1 4は 2 Aの動作図 であり、 1 4 'は 2 Bの動作図である。 ク.ロヅク電圧 V Γ , V 2'は 2 Bに印加 され、 クロック電圧 V 1 , V 2は 2 Aに印加される。 1 4の Pは出力接点 1 2 Λの充電状態を表し、 Hは保持状態を表し、 Eは評価（放電）状態を表す。 同様 に、 1 4'の P'は 2 Bの出力接点 1 2'の充電状態を表し、 H'は保持状態を表 し、 E'は評価状態を表す。 MO S 2相シフ ト レジスタの動作は周知であり、 詳細な説明は省略される。 図 6において、 Eは P'より遅れて動作し、 E'は P より遅 て動作する。 図 6において、 1水平帰線期間に P .Η,Εを配置する事 によって、 1画素行の信号電荷を水平 C CDに転送できる。 図 5において、 1 O Aを遮断し、 8 Aを導通させる事によって、 各 D V T Gに深い電位 V Hを印 加する事ができる。 この時、 充電用電源電圧 VDを最も深い電位 VRに変更す れば、 共通転送電極形 I Tセンサの AT G (画素容量と垂直 C C Dを接続する スィツチのゲート電極）に読みだしパルス電圧を印加で 5、 両素の信号電荷を 垂 ¾ C C Dに転送でさる。 図 7はシフ ト レジスタ 2 Aによつて駆動されるバッ ファインバータ 1 5の出力接点に垂直走査線 3 Zを接続する実施例を表す。 ダ イナミ ヅクインパータ 1 5によって、 図 3 (Aから F)と図 4 (Aから F)の転送 ク.ロックを発生でさる。 たとえば図 6において、 P期間に充電スィッチ 1 5 A が導通し、 放電スィツチ 1 5 Cが遮断する。 H期間に 1 5 A, 1 5 Cが遮断す ろ。 E期間に 1 5 Aは遮断し、 1 5 Cは導通すろ。 図 8は図 7の変形実施例で あるつ 接続スィツチ 1 6は図 7の放電スイッチ i 5 Cと同じ動作をする。 図 9 はク レーム 1 0を説明する動作図であり、 図 1の構造を持つ 2 E./Bfe送セン サのシフ ト レジスタ 2 Aの動作図である。 シフ ト レジスタ 2 Aは出力インパー タ 1 1 Λと出カインバータ 1 1 Bを交互に接続して構成される。 そして垂直走 査線 3 (Zから W)は各出力インバータの出力接点 1 2 A， 1 2 Bに接続される。 時刻 tOから t 6の期間に、 2相シフ トレジスタ 2 Aの各出力接点は図 9のよう な変化をするので、 奇（偶）数番目の N'DVT Gの下に蓄積された信号電荷を独 立に垂直転送できる。 図 9の垂直走査線の'電位変化は図 1 0 (Aから H)と同じ であるので、 垂直転送状態は図 1 0 (Aから H)と同じである。 垂直転送を実施 する前に、 奇（偶）数番目の ND VT Gに深い電位 VHを印加し、 偶（奇）数番目 の ND VT Gに浅い電位 VLを印加する事は当然であり、 1 1 A.1 1 Bをダ ィナミ ック形インバ一タとする事により簡単に実施できる。 勿論特別の充電ス イッチを付加しても良い。 3 Zは下流の垂直走査線であり、 3Wは上流の ND VT Gである。 図 1 0 (Aから H)は図 2の構造を持つ 2 EZB転送センサを表 す動作図である。 ただし、 シフ トレジスタ 2 A, 2 Bの記載は省略されている。 2 Λは ND V T G 3 (Z， X , V)を駆動し、 2 Bは ND V T G 3 (Y ,W， U)を駆 動する。 2 Aと 2 Bを交互にク aヅク動作さ,せる事によって、 信号電荷 Q 1 , Q 2 , Q 3を独立に転送できる。 図 9 ,図 1 0において、 シフ トレジスタ 1 1 A, 1 1 Bは 2相スタチック形シフ トレジスタによって、 構成できる。 勿論 4祖シ フ トレジスタなどの使用も可能である。 図 9のシフ トレジスタ 2 Aにおいて、 インバータ 1 1 と 1 1 Bは交互に評価（放電）動作 Eと保持動作 Hを実施する ので、 シフ トレジスタ 2 Aは 2相ダイナミ 'ソク（特にレシオ）形式とする事がで さる。 図 1 0 (Aから H)の奇（偶）数番目の ND VT Gを駆動するシフ ト レジス タ 2 Aと、 偶（奇）数番目の ND V T Gを駆動するシフ トレジスタ 2 Bはそれぞ れ保持動作 Hと評価動作 Eを交互に実施するので、 ダイナミ ツク〈特にレシオ） 形シフトレジスタを使用できる。 図 9 ,図 1 0 (Aから H)において、 2 A, 2 B はレシオレス形出カインバータを備えるシフ トレジスタによって、 構成できる c ただし、 充電動作期間 Pの出力接点の電位変化を垂直走査線に伝達しないよう に、 充電期間 Pにシフ トレジスタと垂直走査線を接続するスイッチは遮断され る。 図 1 1 A (Aから C)は 1 E/B転送 I Tセンサの残留電荷 QNRを表す動 作図である。 垂直帰線期間の最初に、 垂直 C CD 6の各電位井戸 3 (Ζ'から S ')は図 1 1 Aの状態になる。 即ち、 残留電荷 QN'R( 1から 4)は PW3 Z' , 3 X' .3 V' , 3 T'にそれぞれ蓄積されている。 次に、 残留電荷 QNR 2.QNR 4を 1 PWピッチだけ垂直転送する。 この垂直耘送は PW 3 Y' , 3 W' , 3 U'， 3 S，に深い電位 V Hを印加し、 そして P W3 X' , 3 T'に浅い電位 V Lを印加 する事によって実施される。 このクロック動作はたとえば図 5において、 隣接 する 2個の充電スィツチ 8 Aをそれぞれ異なる充電用電源 V D 1 ， V D 2に接 続し、 放電スイツチ 1 0 Aを遮断し、 8 Aを導通し、 上記の VD 1 , VD 2を 変更すれば良い。 もちろんバッファインバータを備える実施例においても、 ダ イナミ ツ ク形バッ フアインパータの充電スィッチを上記の充電スィッチと同様 に動作させればよい。 その結果、 残留電荷は図 1 1 Bの配置を持つ。 その後、 オペての D V T Gに深い電位 V Hが印加され、 そして奇（偶）数番目の PW3 Z ' .3 X ' , 3 V ' , 3 T 'に画素から信号電荷 Q 1 , Q 2， Q 3. Q 4が転送される。 図 1 1 Cは上記の状態を表す。 そして、 P W3 Z'の電荷と PW3 Y'の電荷は 隣接する 2個の水平 C CDによって出力され、 そして出力された 2個の出力電 圧が減算される。 次に PW3 X'と PW3 W'の電荷が同様に出力され、 減算さ れる。 このようにすればスメァノイズは垂直相関によって、 相殺される。 フィ ールド期間毎に出力する信号電荷を変更してィンタ レースを実施する事は^然 であろ。 図 i 1 (Dから F)は 2 EZB転送センサに上記のスメァノ イズ減算技 術を使用する事を説明する動作図である。 図 1 1 Dは垂直帰線期間の最初の残 留電荷の配置を表す。 図 1 1 Eは奇（偶）数番目の残留電荷を i電位井戸（PW) ピ チだけ転送した状態を表す。 .図 1 1 Fは画素から信号電荷 1., Q 2 ,Q 3 を垂直 C C D 6の電位井戸 3 Z' .3 V' , 3 R 'に転送した状態を表す。 基本的 な動作は上記の 1 EZB転送 I Tセンサと同じである。 図 1 1 (八から ）に説 明された残留電荷の再配置の他に、 垂直帰線期間に残留電荷を垂直 C CD 6か ら排出し、 そして隣接する 2個の電位井戸の電荷を減算してもよい。 図 1 2は クレーム 5に開示される中間電位 1 転送センサを表す 1実施例断面図で ある。 Ντ形基板（4 X 1 0 4]·原子/ C C) 2 0の上に P形ゥエル領域（ 2 X 1 0 【 1 5 }原子 C C 3 2が作られる。 ただし〖 ）は指数項を表ォ。 その上 に、 N形バルクチャンネル領域（ 1 X 1 0 [1 6 )原子 Z C C) 2 2が作られる。 領域 2 2の一部の表面にボロンイオンが注入されて、 電位障壁領域 3 が作ら れる。 そして領域 2 2の表面に絶緣膜 3 6を介して DVT G 3 7 A.3 7 Bが 作られる。 そして瞵接する 2個の D VT G 3 7 A , 3 7 Bの間の中間チヤンネ ル領域 2 2 Aの上に直流電位を持つ NT D V T G 3 5が作られる。 図 1 3は図 1 2のチヤンネル電位図である。 中間チヤンネル領域 22 Aには中間電位 VMが 与えられる。 クロックされない ND VT G 35は非常に薄くできるので、 1 E ZB転送 F Tセンサの青感度が改善される。 図 1 2の 1実施例において、 中間 チヤンネル領域 2 2 Aの表面にポロンイオンの注入によって電位障壁領域を作 れば、 上記の ND V T G 3 5を省略する事ができる。 その桔杲青感度はさらに 改善される。 中間チャンネル領域 2 2 Aの表面へのイオン注入と、 DVTGの 下の電位障壁領域へのイオン注入は同じ工程によって実施できる。 上記の説明 によって、 本発明のシフ トレジスタ駆動 EZB転送センサが F Tセンサと I T センサの垂直転送に使用できる事、 上記の垂直 送によってノ ンインタレース 出力方式または 2画素行読みだしィンタレース出力方式の実施が可能である事 が理解される。 更にインタ レースノノ ンインタ レース方式の切り替え、 フ レー ム蓄積モー ド Zフィールド蓄積モー ドの切り替えも可能である。 垂 [ftC CDの どちらかまたは両方を使用して、 1画素行の信号電荷を転送する 1画素行読み だしィンタレースも可能である。 スメァノィズが小さい時に 2画素行読みだし インタレース.を実施し、.スメァノ ィズが大きい.時にク レーム 2- 3 , 24のスメ ァノィズ低减技術を利用する事も可能である。 図 1 4はクロック線駆動 1 EZ B転送センサを説明すろ 1実施例等価回路であり、 図 1 5はクロック線 2 Υ' ,In a preferred embodiment, the charging operation of one shift register preferably begins earlier than the evaluation (discharge) operation of the other shift register. The clock operation shown in FIG. 3 (A to F) and FIG. 4 (A to F) is also possible in the embodiment using the dynamic type, especially the ratio type buffer inverter. However, the charging operation of the inverter is a quick operation that applies a deep potential VH to its output contact, and the discharging operation is a clock operation that applies a shallow potential VL to its output contact. It can be seen that the 1 E / Bg transmission of the present invention can be implemented by a very simple mouth and speed operation. In Fig. 3 (A to F) and Fig. 4 (A to F), if the deep potential VH is applied to each DVTG again after the transfer of the charge, the next 1EZB transfer can be performed. FIG. 5 is an equivalent circuit diagram of one embodiment of the shift register of FIG. Of course, the shift register in Fig. 3 can also have basically the same structure as in Fig. 5. The vertical scanning lines 3Z, 3Y and 3X are the output of the shift register 2 2.2Β and the output of the inverter 11 1. Directly connected to contacts 12 A and 12 A '. Of course, both may be connected by a switch. 1 1 A is the charging switch This is a dynamic inverter with 8 A switch, 9 A evaluation switch and 1, 0 A discharge switch. The connection inverter 11B for connecting the binary output inverter has a discharge switch 10B, an evaluation switch 9B, and a charge switch 8B. 11A and 11B are alternately connected by connection switches 7A and 7B. FIG. 6 is an operation diagram of one embodiment of the two-phase shift registers 2A and 2B of FIG. Here, 14 is an operation diagram of 2 A, and 14 ′ is an operation diagram of 2 B. The clock voltages VΓ and V 2 ′ are applied to 2 B, and the clock voltages V 1 and V 2 are applied to 2 A. 14 P indicates the charge state of the output contact 12 1, H indicates the hold state, and E indicates the evaluation (discharge) state. Similarly, P 'of 14' indicates the state of charge of the output contact 12 'of 2B, H' indicates the holding state, and E 'indicates the evaluation state. The operation of the MOS two-phase shift register is well known and will not be described in detail. In FIG. 6, E operates later than P ', and E' operates later than P. In FIG. 6, by arranging P.Η, Ε during one horizontal retrace period, signal charges of one pixel row can be transferred to the horizontal CCD. In FIG. 5, by blocking 1 OA and conducting 8 A, a deep potential VH can be applied to each DVTG. At this time, if the charging power supply voltage VD is changed to the deepest potential VR, the read pulse voltage can be applied to the ATG (gate electrode of the switch connecting the pixel capacitance and the vertical CCD) of the common transfer electrode type IT sensor. 5. Transfer the signal charges of both elements to the vertical CCD. FIG. 7 shows an embodiment in which the vertical scanning line 3Z is connected to the output contact of the buffer inverter 15 driven by the shift register 2A. The transfer lock shown in FIG. 3 (A to F) and FIG. 4 (A to F) is generated by the dynamic disconnector 15. For example, in FIG. 6, the charge switch 15 A conducts and the discharge switch 15 C shuts off during the P period. During the H period, 15 A and 15 C cut off. During period E, 15 A is cut off and 15 C is conducting. FIG. 8 shows a modification of FIG. 7. The connection switch 16 operates in the same manner as the discharge switch i 5 C of FIG. FIG. 9 is an operation diagram for explaining the frame 10, and is an operation diagram of the shift register 2A of the 2E./Bfe transmission sensor having the structure of FIG. Shift register 2A is configured by alternately connecting output inverters 11 1 and output inverters 11B. And vertical running Line 3 (from Z to W) is connected to the output contacts 12 A and 12 B of each output inverter. During the period from time tO to t6, the output contacts of the two-phase shift register 2A change as shown in Fig. 9, so the signal charge accumulated under the odd (even) number N'DVT G is Vertical transfer can be performed independently. Since the potential change of the vertical scanning line in FIG. 9 is the same as in FIG. 10 (A to H), the vertical transfer state is the same as in FIG. 10 (A to H). It is natural to apply the deep potential VH to the odd-numbered ND VTG and the shallow potential VL to the even-numbered ND VTG before performing the vertical transfer. 1 A.11 1B can be easily implemented by using a dynamic inverter. Of course, a special charging switch may be added. 3Z is the downstream vertical scan line, and 3W is the upstream ND VTG. FIG. 10 (A to H) is an operation diagram showing a 2EZB transfer sensor having the structure of FIG. However, the description of the shift registers 2A and 2B is omitted. 2Λ drives ND VTG 3 (Z, X, V), and 2B drives ND VTG 3 (Y, W, U). The signal charges Q 1, Q 2, and Q 3 can be transferred independently by alternately applying a pulse operation to 2 A and 2 B. In FIGS. 9 and 10, shift registers 11A and 11B can be constituted by two-phase static shift registers. Of course, the use of four shift registers is also possible. In shift register 2A in Fig. 9, inverters 11 and 11B alternately perform evaluation (discharge) operation E and hold operation H. Therefore, shift register 2A has a two-phase dynamics (especially ratio) format. You can do it. Figure 10. Shift register 2A that drives the odd (even) ND VTG of A (H) and shift register 2B that drives the even (odd) ND VTG Since the holding operation H and the evaluation operation E are performed alternately, a dynamic (particularly ratio) shift register can be used. 9, in the (H from A) 1 0 by 2 A, 2 B are shift register comprises a mosquito inverter output ratioless form, c can be configured, however, the vertical scanning line potential change of the output contacts of the charging operation period P To prevent transmission, the switch connecting the shift register and the vertical scan line during the charging period P is shut off. Figure 11A (A to C) is an operation diagram showing the residual charge QNR of the 1 E / B transfer IT sensor. At the beginning of the vertical retrace period, each potential well 3 (Ζ 'to S ') Is in the state of Fig. 11A. That is, the residual charges QN'R (1 to 4) are accumulated in PW3Z ', 3X'.3V', and 3T ', respectively. Next, the residual charges QNR 2. QNR 4 are vertically transferred by 1 PW pitch. This vertical tilling is performed by applying a deep potential VH to PW3Y ', 3W', 3U ', 3S, and a shallow potential VL to PW3X', 3T '. . In this clock operation, for example, in FIG. 5, two adjacent charging switches 8 A are connected to different charging power supplies VD 1 and VD 2, the discharging switch 10 A is cut off, and 8 A is turned on. VD 1 and VD 2 can be changed. Of course, even in the embodiment having the buffer inverter, the charging switch of the dynamic buffer inverter may be operated in the same manner as the above-mentioned charging switch. As a result, the residual charge has the configuration shown in Fig. 11B. After that, a deep potential VH is applied to the DVTG in operation, and signal charges Q 1, Q 2, Q 3 from the pixel are applied to odd (even) -numbered PW3 Z '.3 X', 3 V ', and 3 T'. Q 4 is transferred. FIG. 11C shows the above state. Then, the charge of PW3 Z 'and the charge of PW3 Y' are output by two adjacent horizontal CCDs, and the two output voltages output are subtracted. Next, the charges of PW3 X 'and PW3 W' are similarly output and subtracted. In this way, the smear noise is canceled by the vertical correlation. It is natural that the interlace is performed by changing the signal charge to be output every field period. Fig. I1 (D to F) is an operation diagram illustrating the use of the above-described smear noise subtraction technique for the 2EZB transfer sensor. Figure 11D shows the arrangement of the first residual charge during the vertical retrace period. Fig. 11E shows a state in which the odd (even) -numbered residual charges are transferred by the i potential well (PW) pitch. FIG. 11F shows a state in which signal charges 1., Q 2, and Q 3 are transferred from the pixel to the potential wells 3 Z ′ .3 V ′ and 3 R ′ of the vertical CCD 6. The basic operation is the same as the above 1 EZB transfer IT sensor. In addition to the relocation of the residual charge described in Figure 11 (from 8), the residual charge is drained from the vertical CCD 6 during the vertical retrace period, and the charge of the two adjacent potential wells is subtracted. May be. FIG. 12 is a cross-sectional view of one embodiment showing the intermediate potential 1 transfer sensor disclosed in claim 5. New tau form the substrate (4 X 1 0 4] · atom / CC) 2 0 P-type Ueru region (2 X on the 1 0 [15] atom CC 32 is created. However, 〖) indicates the exponential term. On top of this, an N-type bulk channel region (1 X 10 [16] atom ZCC) 22 is created. Boron ions are implanted into a part of the surface of the region 22 to form a potential barrier region 3. Then, a DVT G 37 A.37 B is formed on the surface of the region 22 via the insulating film 36. The N T DVTG 3 5 with a DC voltage on the瞵接to two D VT G 3 7 A, 3 7 intermediate Chiyan'ne Le regions 2 2 A during B is made. FIG. 13 is a channel potential diagram of FIG. An intermediate potential VM is applied to the intermediate channel region 22A. The unclocked ND VTG 35 can be very thin, thus improving the blue sensitivity of the 1E ZB transfer FT sensor. In the embodiment of FIG. 12, if the potential barrier region is formed by implanting polon ions on the surface of the intermediate channel region 22 A, the above-mentioned ND VTG 35 can be omitted. Its sensitivity is further improved. Ion implantation into the surface of the intermediate channel region 22 A and ion implantation into the potential barrier region below the DVTG can be performed by the same process. As described above, the shift register driving EZB transfer sensor of the present invention can be used for vertical transfer between the FT sensor and IT sensor, and the above vertical transfer implements a non-interlaced output method or a two-pixel line reading interlace output method. It is understood that is possible. In addition, it is possible to switch between interlaced non-interlaced systems, and to switch between frame storage mode and Z-field storage mode. One-pixel row reading and interlacing, in which one or both of the ftCCDs are used to transfer signal charges in one pixel row, are also possible. It is also possible to perform 2-pixel line reading and interlacing when the smearing is small, and use the low noise technology of claims 2-3 and 24 when the smearing is large. FIG. 14 is an equivalent circuit of the first embodiment to explain the clock line drive 1 EZ B transfer sensor, and FIG. 15 is a clock line 2 Υ ′,
2 Ζ 'に印加される 2相クロ 'プク電圧 V 1 , V 2の波形図である。 図 1 4 ,図 1FIG. 7 is a waveform diagram of two-phase clock voltages V 1 and V 2 applied to the channel 2. Fig. 14, Fig. 1
5はクロ Vク線駆動 1 Ε/Β転送センサの駆動回路を表す。 垂直 C C Dの D V T Gに接続される垂直走査線 3 (Ζから V)は順次スィ ヅチ 1 6 (Vから Ζ)によ て、 クロック線 2 Ζ， 2 Υに接続される。 上記の順次スィッチ はシフ トレジスタ 2によって制御される。 シフ トレジスタ 2の入力端 2 Xに転 送パルス情報を入力する事によって、 順次スィッチは 1 6 Z， 1 6 Yから順番 に導通する。 図 1 5において、 T 1期間は非転送期間であり、 垂直 C CDの各 電位井戸に信号電荷が蓄積される。 FTセンサにおいて、 T 1期間に全順次ス イッチが導通し、 2 Z， 2 Yは深い電位 VHになり、 全垂直走査線は深い電位 VHになり、 信号光が垂直 C C Dの各電位井戸に電荷を蓄積する。 同様に I T センサにおいて、 T 1期間に垂直 C C Dの各 D V T Gは V Hになり、 画素列の 電荷が D VTGの下に転送される。 共通転送電極形 I Tセンサにおいて、 T 1 期間に全順次スィッチが導通され、 V I . V 2は読みだし電圧 VRになる。 そ の結果画素列の電荷は D V T Gの下に転送される。 勿論ィンタレースを実施す る為に、 2 Z' , 2 Y'に交互に VRを印加してもよい。 そしてその後で 2 Z' , 2 Y'は深い電位 V Hになる。 転送パルス情報の入力によって、 全順次スイツ チは垂直転送期間の終わりに自動的に導通している。 非転送期間 T 1において、 垂直 C 00の0 で（ の下に電荷0 1から Q 8を転送または蓄積した後で、 全 順次スィツチは遮断される。 この遮断はシフ トレジスタ 2をダイナミ ック動作 させろ事によってまたは順次スィッチのゲ一トに特別のスィヅチで浅い電位 V Lを印加する事によって実施される。 従って各 D V T Gは浮遊電位 V Hを持つ。 次の t 1力、ら t 9期間に信号電荷 Q 1、 Q 2 , Q 3が垂直 C C Dから出力される 事が図 1 6 (Aから L)によって説明される。 t l期間に V 1は浅い電位 Vしに なり、 V 2は深い電位 V Hであり、 そして 1 6-Ζ, Ι 6 Υが導通する。 そして Q 1.. 転 ー ト 4 Αを介して水平 C CD 5 Aに転送される。 t 2期間に V 1 ,Reference numeral 5 denotes a drive circuit for a black line drive 1 ク / Β transfer sensor. The vertical scanning line 3 (Ζ to V) connected to the vertical CCD DVTG is connected to the clock lines 2Ζ and 2Ζ by the switches 16 (V to Ζ) sequentially. Above sequential switch Is controlled by shift register 2. By inputting the transfer pulse information to the input terminal 2X of the shift register 2, the switches are sequentially turned on in order from 16Z, 16Y. In FIG. 15, the T1 period is a non-transfer period, and signal charges are accumulated in each potential well of the vertical CCD. In the FT sensor, all the switches are turned on sequentially during the period T1, 2Z and 2Y become the deep potential VH, all the vertical scanning lines become the deep potential VH, and the signal light is charged in each potential well of the vertical CCD. To accumulate. Similarly, in the IT sensor, during the T1 period, each DVTG of the vertical CCD becomes VH, and the charge of the pixel column is transferred below the DVTG. In the common transfer electrode type IT sensor, all the switches are turned on sequentially during the period T1, and VI.V2 becomes the read voltage VR. As a result, the charges in the pixel column are transferred under DVTG. Of course, VR may be applied alternately to 2Z 'and 2Y' to implement the interlace. After that, 2 Z ′ and 2 Y ′ become deep potential VH. By inputting the transfer pulse information, all the sequential switches are automatically conducting at the end of the vertical transfer period. During the non-transfer period T1, all the switches are turned off after transferring or storing the charges 01 to Q8 at 0 of the vertical C00 (below the vertical C00. This cutoff makes the shift register 2 operate dynamically. This is done by applying a shallow potential VL to the gates of the switches in a special switch, either sequentially, so that each DVTG has a floating potential VH. The fact that Q1, Q2, and Q3 are output from the vertical CCD is explained by Fig. 16 (from A to L): During tl, V1 has a shallow potential V, and V2 has a deep potential VH. Yes, and 16-Ζ, Ι6Υ conducts, and is transferred to horizontal CCD 5 A via Q 1. Transit 4 。.
V 2は深い電位 V Hになる。 t 3期間に V 1は深い電位 V H、 V 2は浅い電位 Vしになる。 そして Q 2は D V T G 3 Yの下から D V T G 3 Zの下に転送され る。 t4期間に V 1 , V 2は深い電位 VHになる。 t 5期間に V 1は浅い電位 V L、 V 2は深い電位 V Hになる。 そして 1 6W.1 6 Xが導通する。 その結果 Q 3は DVT G 3 Xの下から DVT G 3 Yの下に転送される。 t6期間に V 1，V2 becomes a deep potential VH. In the period t3, V1 becomes the deep potential VH, and V2 becomes the shallow potential V. Then, Q2 is transferred from below DVTGG3Y to below DVTG3Z. During the period t4, V 1 and V 2 become the deep potential VH. In the period t5, V1 becomes the shallow potential VL, and V2 becomes the deep potential VH. And 16W.16X conducts. As a result, Q 3 is transferred from below DVT G 3 X to below DVT G 3 Y. V 1 during t6 period
V 2は深い電位 V Hになる。 t 7期間に V 1 は深い電位 V H、 V 2は浅い電位 V Lになる。 そして t 7期間に V 1は深い電位 V H、 V 2は浅い電位 V Lにな る そして Q 3 ,04カ《 1 DVT Gピッチ（1電位井戸ピッチ）だけ転送される。 t8期間に V 1 , V 2は深い電位 VHになる。 t9期間に V 1は浅い電位 VL、V2 becomes a deep potential VH. V1 is deep potential VH, V2 is shallow potential during t7 period Becomes VL. Then, in the period t7, V1 becomes the deep potential VH, V2 becomes the shallow potential VL, and Q3,04 <<< 1 DVT G pitch (one potential well pitch) is transferred. During the period t8, V 1 and V 2 become the deep potential VH. During t9, V 1 is a shallow potential VL,
V 2は深い電位 V Hになる。 そして 1 6 U, 1 6 Vが導通する。 その結果 Q 4， Q 5 , Q 6が 1 D V T Gピツチだけ転送される。 このようにすれば非常に簡単 に連続注入形 1 EZB耘送を実施できる。 特に L 1，t 5 ,t 9期間にクロヅクバ ルス電圧 V 1の印加（変化）と順次スィツチの導通を同時に実施できる事は転送 動作を非常に簡単にする。 更に隣接する 2個の順次スイツチを同時に導通でき る事は転送動作を非常に簡単にし、 シフ トレジスタを小形にする。 I Tセンサ において、 T 1は垂直帰線期間であり、 t 1から t4期間は 1水平帰線期間内に 配置さ.れる。 バッファ形 F Tセンサにおいて、 T 1は垂直走査期間であり、 T 1以外の期間は垂直帰線斯間に配置される。 図 1 7はクレーム 6に開示される 中間電位形 I EZB転送センサを説明する 1実施例断面図である。 基本的に図 1 7は図 1 2と同じである。 ただし、 直流電極 3 5の下に電位障壁領域 34が イオン注入によって付加され、 その結果中間電位障壁領域 2 2 Cと中間電位井 戸領域 2 2 Bが中間チャンネル領域に作られる。 この C C D構造は 1相 C C D として公知である。 図 1 8は図 1 7の電位図である。 図 1 9は図 1 7の変形実 施例であり 直流電極 3 5を省略して中間チヤンネル領域 2 2 Aの表面に 2種 類のイオン注入を実施して、 第 1電位障壁 34 Cと第 2電位障壁 34が作られ る。 そ.の結果中間チャンネル領域に異なる電位を持つ中間電位障壁領域 2 2-C と中間電位井戸領域 2 2 Bが作られる。 好ましい実施 において、 第 2電位障 壁 34 Bと電位障壁 34は同じイオン注入工程によって作られる。 この C CD 構造はバーチャル C CDとして公知である。 図 2 0は図 1 9の電位図である。 図 2 1は図 1 7と図 1 9の C C D構造を持つクロ .；/ク線駆動形 1 E/B転送セ ンサの駆動回路を表す。 各垂直走査線 3 (Zから T)はシフ トレジスタ 2によつ て制御される順次スィツチ 1 6 (Zから T)によってクロック線 2 Yに接続され る。 図 2 2は図 2 1のクロック線 2 Yに接続される。 図 2 2は図 2 1のクロッ ク線 2 Yに印加されるクロック電圧 V 1の波形図である。 これは基本的に図 1 5と同じである。 非転送期間 Τ 1に全 D VT Gに中間電位 VMが印加され、 D V T Gの下の電位井戸 P WVと中間チヤ ンネル領域の電位井戸 PWMは中間電 位 VM'を持つ。 そして垂直 C C Dの全電位井戸に電荷が蓄積または転送され る。 図 23 ( Αから L)は図 2 1、 図 2 2のクロック線駆動形 1 E B転送セン ザの垂直 D 6の動作を表す。 DVT G 3 Z, 3 X, 3 V, 3 Tの間に直流転 送電極 3 Y.3 W, 3 Uが配置され、 それらの下に電荷 Q 1から Q 7が蓄積され る。 T 1期間に全順次スィッチは導通するので、 2 Yによって D VT Gに中間 電位 VMを印加できる事は図 1 4 ,図 1 5，図 1 6 同じである。 I Tセンサに おいて、 深い電位 V Hまたは読みだし電位 V Rを印加してもよい。 そして T 1 期間の終わりに全順次スィッチは遮断され、 VMを持つ各 D V T Gは浮遊電位 を持つ。 図 23 Aはこの状態を表す。 図 2 3 Bは t 1期間の状態を表し、 V 1 は浅い電位 V Lになり、 I 6 Zは導通し、 Q 1は 4 Aを介して水平 C C D 5 A に耘送される。 図 2 3 Cは t 2期間の状態を表し、 V 1 は深い電位 V Hになり、 Q 2は 3 Yの下から 3 Zの下に転送される。 図 2 3 Dは t 3期間の状態を表し、 V 1は浅い電位 V Lになり、 Q 2は 5 Aに転送される。 図 2 3 Eは t4期間の 状態を表し、 V 1は浅い電位 V Lになり、 1 6 Xは導通される。 その結果 Q 3 は 3 Xの下から 3 Yの下に転送される。 図 23 Fは t 5期間の状態を表し、 V 1 は深い電位 VHになり、 Q 3 , Q 4は 1電位井戸ピッチだけ転送される。 同 様にして図 23 Gから図 23 Lによって、 t 6期間から t l 1期間の状態が示さ れる。 t 2.,t3',t4期間に垂直 C CDは 1行の信号電荷を出力し、 t 5 ,t 6 ,t7 期間に、 次の 1行の信号電荷を出力する。 この転送方法は非常に簡単である特 徴を持つ。 1:4 ，t7，t 1 0期間に順次スィツチを 1値導通する事によって、 1 電位井戸の電荷を 1電位井戸ピッチだけ転送できる事は大きな利点である。 そ して図 1 7、 図 1 9の構造は F Tセンサの青感度を改善する。 中間直流転送電 極 3 5は非常に薄くできる。 図 24は独立発明 2のスメァノィズ低減技術を説 明する 1実施冽等価回路図である。 説明を簡単にする為に、 固体撮像素孑 1 A は従来の 2相クロック転送方法によって、 1水平走查期間に 1画素行を出力す る I Tセンサであると仮定する。 I Tセンサ 1 Aは撮像領域 1 と水平 C C D 5 を備える。 画素列と垂直 C C Dの記載は省略される。 垂直走查期間に水平 C C D 5から出力された信号電荷 Q Sは増幅器 9 2で信号電圧 V Sに変換され、 V Sは比铰器 9 3と減算回路 1 0 0に入力する。 垂直帰線期間に水平 C C D 5か ら出力されるスメァノィズ電荷 Q N Sは 9 2でスメァノィズ電圧 V N Sに変換 され、 V N Sは A Z D変換器 9 6を介して、 デジタルメモリ 9 7に雲己億される。 少なく とも飽和画素列に対する 1画素行分のスメァノイズ電圧が記億されるが、 全画素列に対する 1画素行以上のスメァノィズ電圧を記億しても良い。.垂直走 查期間にデジタルメモリ 9 7は D Z A変換器 9 8を介してスメァノィズ電圧 V N Sをスィッチ回路 9 9に送る。 スィッチ回路 9 9は特定の条件において、 D / A変換器 9 8から出力されるスメァノィズ電圧 V N Sを减算回路 1 0 0に伝 達する。 以下において、 上記の特定の条件が説明される。 撮像領域 1の各画素 の内、 M域 9 1 Aに強い光が入力している事と、 ブルーミ ング抑圧手段を持つ 事と、 垂直帰線期間に垂直 C C Dに残留する残留電荷を高速転送によってクリ ァする事が仮定される。 このクリア転送によって、 垂直 C C Dに残留する残留 荷はクリアされるので、 スメァノイズは低減される。 しかし、 上記の残留電 荷のクリアによって、 飽和画素領域 9 1 Aの下流の領域（下流領域と略称され る。 ） 9 1 Cのスメァノイズ電荷（残留電荷）は領域 9 1 A , 9 1 Bに比べて非常 に小さくなる。 その結果、 領域 9 1 A (飽和画素頜.域と略称されろ。 ）の 1：流の 領域（上流領域と略称される。 ）9 1 Bから発生する信号電荷に大きなスメァノ ィズが混入する。 独立発明 2の 1実施例において、 9 1 Aから発生する信号電 圧からスメァノイズ電圧を減算しない。 その結果 9 1 Aの信号電圧は小さくな らない。 独立発明 2の他の 1実施例において、 非飽和画素列 9 1 Fから発生す る信号電圧からスメァノイズ電圧を減算しない。 その結果 9 1 Fの信号電圧の ランダムノ イズは低減される。 独立発明 2の他の実施例において、 下流領域 9 1 Cから発生する信号電荷からスメァノイズ電圧を减算しない。 その结果スメ ァノィズ電荷を持たない 9 1 Cの信号電荷は負のスメァノィズを持たない。 具 体的な動作が以下に説明される。 9 2から出力ざれた信号電圧 V Sは比校器 9 3で飽和信号電圧 V S maxと比铰される。 V S V S maxである時に、 9 3は 0 を出力する。 9 3はアンド回路 9 5 A , 9 5 Eと、 インバータ 9 5 Bに論理信 号 V Cを送る。 9 5 Aはラインメモリ 9 4の出力信号 V Mと 9 3の出力信号 V Cのアンド信号をラインメモリ 9 4に送る。 ラインメモリ 9 4は水平 C C D 5 と同期して駆動される。 その結果ラインメモリ 9 4は領域 9 1 Aと 9 .1 Bの信 号電圧に対して、 0を出力する。 インバータ 9 5 Bは領域 9 1 Aの信号電圧に 対してだけ、 1を出力する。 従って、 9 4と 9 5 Bから論理信号を受け取るノ ァ回路 9 5 Cは領域 9 1 Bの信号電圧に対してだけ、 0をオア回路 9 5 Dに出 カオる。 その結果 9 5 Dによって制御されるスィッチ回路 9 9は上流領域 9 1 Bの信号電圧に対してだけ、 7から再生されたスメァノィズ電圧を减算回路 1 0 0に送る。 即ち、 領域 9 1 Bの信号電圧からだけスメァノイズ電圧が減算 される。 垂直帰線期間の最初にラインメモリ 9 4の各記億セルは 1 にリセッ ト される。 固体撮像素子 1 Aが E Z B耘送形 I Tセンサであり、 垂直帰線期間に 垂直 C C Dの残留電荷をクリアする実施例において、 図 1 4の回路を使用する 事ができる。 1 画素当たり 1 D V T Gまたは 2 N D V T Gを備え、 そして 1水 平走查期間に 2画素行を独 5：に出力し、 上記の残留電荷のク.リァを実施しない E Z B転送センサにおいて、 下流領 ¾ 9 1 Cの奇（偶）数番目の電位井 Pは残留 電荷を持ち、 偶（奇：)数番目の電位井戸は残留電荷を持たない。 故に、 奇（偶）数 番目の電位井戸の ί言号電荷が出力される時に、 アン ド Θ路 9 5 Εへ入力する ロック V Xを 1 にすれば良い。 その結果スィツチ回路 9 9が導通して減算回路 i 0 0は減算を実質的に実施し、 9 1 Cのスメァノイズは相殺される。 アン ド 回路 9 5 Eには信 V Cが入力するので、 領域 9 1 Aの信号電圧が出力される 時に、 スィッチ回路 9 9は遮断される。 上記の 1水平走査期間に 2画素行を独 立に出力する実施例において、 一般に 2 f の水平 C C Dが使用されるので、 領 域 9 1 Cから出力される 2水平 C C Dの ί言号電圧の内、 残留電荷を含む水平 C C Dの信号電圧からスメァノィズ電圧、 減算するように、 スイツチ回路 9 9、 アンド回路 9 5 Eを設計する事も可能である。 図 24の論理回路による制御信 号の遅延を捕償するために、 缄算回路 1 0 0に入力する信^電圧を遅延しても 良い。 I Tセンサにおいて、 垂直 C CDの残留電荷は画素に隣接するオーバ一 フロードレンにクリアしても良い。 1画素当たり 1個の ND VTGを備える 2 転送センサにおいて、 図 1 4の回路によって、 領域 9 1 Cの奇（偶）数番 目の電位井戸の信号電圧からスメァノイズ電圧を減算できる。 図 2 5は独立発 明 3の 1実施例を表す-遂次比铰形 A ZD変換器のプロック回路図である。 図 2 4の増幅器 9 2から出力されたスメァノィズ電 EVNSは比铰器 1 0 2によつ て、 参考電圧 VRXと比铰される。 1 0 2の出力信号は遂次比较形レジスタ 1 03に入力され、 1 0 3の出力信号は切り替え回路 1 _04を介して D/A変換 器 1 0 5に送られろ。 そして DZA変換器 1 0 5の出力信号は切り替え回路 1 0 1を介して比皎器 1 0 2に帰還される。 回路 1 0 1 と 1 04は AZD変換器 として使用される時に、 1 0 8と 1 0 7を接続しそして 1 0 9と I 1 0を接続 する。 そして DZ A変換器として使用する時に、 1 0 8と 1 0 5を接続し、 そ して 1 1 2と 1 1 0を接続する。 9 7はデジタルメモリである。 1 0 2に信号 電圧を送ろ水平 C Cは約 7水平走査期間に 1画素 分のスメァノィズ電荷を出 力する。 図 2 5の遂次比校形 A ZD変換器は 6ビッ 卜のデジタル信^を作る。 このようにすれば図 24の回路は非常に簡単に構成できる。 好ましい 1実施例 ··において、 比铰器 1 0 2は垂直走査期間には使用されないので、 1 0 2を垂直 走查期間に図 24の比铰器 9 3として使用する事ができる。 ·その結果図 24の 回路は簡単になる。 図 2 6は独立発明 4を表す 1実施例断面図である。 V2 becomes a deep potential VH. Then, 16 U and 16 V conduct. As a result, Q4, Q5 and Q6 are transferred by one DVTG pitch. In this way, continuous injection type 1 EZB tilling can be performed very easily. In particular, the ability to simultaneously apply (change) the clock pulse voltage V1 and sequentially turn on the switches during the periods L1, t5, and t9 greatly simplifies the transfer operation. Furthermore, the ability to conduct two adjacent switches at the same time greatly simplifies the transfer operation and reduces the size of the shift register. In the IT sensor, T 1 is a vertical retrace interval, and t 1 to t 4 are arranged within one horizontal retrace interval. In the buffer type FT sensor, T 1 is a vertical scanning period, and periods other than T 1 are arranged between vertical retrace lines. FIG. 17 is a cross-sectional view of one embodiment illustrating the intermediate potential type IEZB transfer sensor disclosed in claim 6. FIG. 17 is basically the same as FIG. However, a potential barrier region 34 is added below the DC electrode 35 by ion implantation, so that an intermediate potential barrier region 22C and an intermediate potential well region 22B are formed in the intermediate channel region. This CCD structure is known as a one-phase CCD. FIG. 18 is a potential diagram of FIG. FIG. 19 is a modified embodiment of FIG. 17, in which the DC electrode 35 is omitted and two types of ions are implanted into the surface of the intermediate channel region 22 A to form the first potential barrier 34 C and the second potential barrier 34 C. A two-potential barrier 34 is created. As a result, an intermediate potential barrier region 22-C and an intermediate potential well region 22B having different potentials are formed in the intermediate channel region. In a preferred implementation, the second potential barrier 34B and the potential barrier 34 are made by the same ion implantation process. This CCD structure is known as a virtual CCD. FIG. 20 is the potential diagram of FIG. Fig. 21 shows the driving circuit of a 1 / E / B transfer sensor with a CCD having the CCD structure shown in Figs. 17 and 19. Each vertical scan line 3 (Z to T) is connected to a clock line 2Y by a sequential switch 16 (Z to T) controlled by a shift register 2. FIG. 22 is connected to the clock line 2Y of FIG. Fig. 22 shows the clock of Fig. 21. FIG. 6 is a waveform diagram of a clock voltage V1 applied to a clock line 2Y. This is basically the same as FIG. In the non-transfer period Τ1, the intermediate potential VM is applied to all the D VTGs, and the potential well P WV below the DVTG and the potential well PWM in the intermediate channel region have the intermediate potential VM ′. Then, charges are accumulated or transferred to all potential wells of the vertical CCD. FIG. 23 (Α to L) shows the operation of the vertical D6 of the clock line drive type 1 EB transfer sensor of FIGS. 21 and 22. DC transfer electrodes 3Y.3W, 3U are arranged between DVT G3Z, 3X, 3V, 3T, and electric charges Q1 to Q7 are stored under them. Since all sequential switches conduct during T1, the intermediate potential VM can be applied to D VTG by 2Y as in Figs. 14, 15, and 16. In the IT sensor, a deep potential VH or a read potential VR may be applied. Then, at the end of the T 1 period, all sequential switches are turned off, and each DVTG with VM has a floating potential. Figure 23A illustrates this situation. FIG. 23B shows the state during the period t1, V1 becomes the shallow potential VL, I6Z conducts, and Q1 is fed to the horizontal CCD 5A via 4A. Figure 23C shows the state during t2, V1 goes to deep potential VH, and Q2 is transferred from below 3Y to below 3Z. Figure 23D shows the state during the t3 period, V1 becomes the shallow potential VL, and Q2 is transferred to 5A. Figure 23E shows the state during the t4 period, V1 becomes the shallow potential VL, and 16X becomes conductive. As a result, Q 3 is transferred from below 3 X to below 3 Y. FIG. 23F shows the state during period t5, where V 1 is at the deep potential VH, and Q 3 and Q 4 are transferred by one potential well pitch. Similarly, FIG. 23G to FIG. 23L show the state from the period t6 to the period tl1. The vertical CCD outputs one row of signal charges during the periods t2, t3 ', and t4, and outputs the next one row of signal charges during the periods t5, t6, and t7. This transfer method has the feature of being very simple. It is a great advantage that the charge of one potential well can be transferred by one potential well pitch by sequentially turning on the switch one value during 1: 4, t7 and t10 periods. Then, the structures of Fig. 17 and Fig. 19 improve the blue sensitivity of the FT sensor. The intermediate DC transfer electrode 35 can be made very thin. FIG. 24 is a 1st embodiment clear equivalent circuit diagram for explaining the smear noise reduction technology of the independent invention 2. For simplicity of explanation, solid-state imaging device 1 A Is assumed to be an IT sensor that outputs one pixel row during one horizontal scan period by the conventional two-phase clock transfer method. The IT sensor 1A has an imaging area 1 and a horizontal CCD 5. The description of the pixel column and the vertical CCD is omitted. The signal charge QS output from the horizontal CCD 5 during the vertical scanning period is converted into a signal voltage VS by the amplifier 92, and the VS is input to the comparator 93 and the subtraction circuit 100. The smearing charge QNS output from the horizontal CCD 5 during the vertical retrace period is converted to a smearing voltage VNS at 92, and the VNS is stored in the digital memory 97 via the AZD converter 96. At least a smear noise voltage for one pixel row for a saturated pixel column is stored, but a smear noise voltage for one pixel row or more for all pixel columns may be stored. During the vertical scanning period, the digital memory 97 sends the scan voltage VNS to the switch circuit 99 via the DZA converter 98. The switch circuit 990 transmits the smearing voltage VNS output from the D / A converter 98 to the arithmetic circuit 100 under specific conditions. In the following, the above specific conditions will be explained. Among the pixels in the imaging area 1, strong light is input to the M area 91A, blooming suppression means is provided, and high-speed transfer of residual charges remaining in the vertical CCD during the vertical retrace period It is assumed that it is clear. This clear transfer clears the residual load remaining on the vertical CCD, reducing smear noise. However, due to the clearing of the residual charges described above, the area downstream of the saturated pixel area 91A (abbreviated as the downstream area) 91I C smear noise charge (residual charge) is reduced to the areas 91A and 91B. It is much smaller than that. As a result, a large smear noise is mixed in the signal charge generated from the region 91A (abbreviated as the saturated pixel I. region) 1: the flow region (abbreviated as the upstream region) 91B. . In one embodiment of the independent invention 2, the smear noise voltage is not subtracted from the signal voltage generated from 91 A. As a result, the signal voltage of 91 A does not decrease. In another embodiment of the independent invention 2, the smear noise voltage is not subtracted from the signal voltage generated from the unsaturated pixel column 91F. As a result, the random noise of the signal voltage of 91 F is reduced. In another embodiment of the independent invention 2, the smear noise voltage is not calculated from the signal charge generated from the downstream region 91C. The result No charge The signal charge of 9 1 C has no negative smear. The specific operation will be described below. The signal voltage VS output from the comparator 92 is compared with the saturation signal voltage VS max by the comparator 93. 93 outputs 0 when VSVS max. 93 sends a logical signal VC to AND circuits 95A and 95E and an inverter 95B. 95 A sends the AND signal of the output signal VM of the line memory 94 and the output signal VC of 93 to the line memory 94. The line memory 94 is driven in synchronization with the horizontal CCD 5. As a result, the line memory 94 outputs 0 for the signal voltages in the areas 91 A and 9.1 B. Inverter 95B outputs 1 only for the signal voltage in area 91A. Therefore, the NOR circuit 95C receiving logic signals from 94 and 95B outputs 0 to the OR circuit 95D only for the signal voltage in the region 91B. As a result, the switch circuit 99 controlled by 95D sends the screen noise reproduced from 7 to the arithmetic circuit 100 only for the signal voltage of the upstream area 91B. That is, the smear noise voltage is subtracted only from the signal voltage in the region 91B. At the beginning of the vertical retrace period, each of the memory cells in line memory 94 is reset to one. The circuit shown in Fig. 14 can be used in the embodiment in which the solid-state imaging device 1A is an EZB tiller-type IT sensor and the residual charge of the vertical CCD is cleared during the vertical retrace period. In an EZB transfer sensor that has one DVTG or two NDVTGs per pixel and outputs two pixel rows to Germany 5: during one horizontal run, and does not perform the above-described residual charge screening, the downstream region 9 The odd (even) -th potential well P of 1 C has a residual charge, and the even (odd:)-th potential well has no residual charge. Therefore, the lock VX input to the AND circuit 95 may be set to 1 when the signal charge of the odd (even) th potential well is output. As a result, the switch circuit 99 becomes conductive, and the subtraction circuit i 00 substantially performs the subtraction, and the smear noise of 91 C is canceled. Since the signal VC is input to the AND circuit 95E, the switch circuit 99 is cut off when the signal voltage of the area 91A is output. In the above-described embodiment in which two pixel rows are independently output during one horizontal scanning period, a 2 f horizontal CCD is generally used. Therefore, the symbol voltage of the two horizontal CCDs output from the area 91 C is used. Of which, horizontal C including residual charge It is also possible to design the switch circuit 99 and the AND circuit 95E so that the scan voltage is subtracted from the CD signal voltage. In order to compensate for the delay of the control signal by the logic circuit of FIG. 24, the signal voltage input to the arithmetic circuit 100 may be delayed. In an IT sensor, the residual charge on the vertical CCD may be cleared to the overflow drain adjacent to the pixel. In a two-transfer sensor with one ND VTG per pixel, the circuit in Figure 14 allows the smear noise voltage to be subtracted from the signal voltage at the odd (even) number potential wells in region 91C. FIG. 25 is a block diagram of a block diagram of an embodiment of the independent invention 3 of the successive approximation ratio AZD converter. The SMNS output EVNS output from the amplifier 92 in FIG. 24 is compared with the reference voltage VRX by the comparator 102. The output signal of 102 is input to the serial ratio register 103, and the output signal of 103 is sent to the D / A converter 105 via the switching circuit 104. The output signal of the DZA converter 105 is fed back to the comparator 102 via the switching circuit 101. Circuits 101 and 104, when used as AZD converters, connect 108 and 107 and connect 109 to I10. Then, when used as a DZA converter, 108 and 105 are connected, and 112 and 110 are connected. 97 is a digital memory. Send the signal voltage to 102. The horizontal CC outputs one pixel of smearing charge during about 7 horizontal scanning periods. The successive ratio type A-ZD converter shown in Fig. 25 produces a 6-bit digital signal. In this way, the circuit of FIG. 24 can be configured very easily. In a preferred embodiment, since the comparator 102 is not used during the vertical scanning period, 102 can be used as the comparator 93 in FIG. 24 during the vertical scanning period. · As a result, the circuit in Fig. 24 is simplified. FIG. 26 is a cross-sectional view of one embodiment showing the independent invention 4.
N形基板（4 X 1 0 {1 4}原子/ C C)2 0上に P形ゥエル領域（2 x 1 0 [ 1 5] 原子 ZC C)3 2が配置される。 その上に N形バルクチヤンネル領域（1 0 〔1 6 }原子/ C C) 2 2が配置される。 N形バルクチヤンネル領域 2 2の第 1領域 2 2 Aの表面にポロンイオンが注入されて電位障壁領域 3 が作られる。 電位 障壁領域 34以外のチヤンネル領域 2 2 Bは電位井戸領域である。 バルクチャ ンネル領域 2 2の間に P形チャンネルス トップ領域（4 X 1 0 M 7 ]原子 C C ) 2 3が作られる。 領域 2 2 ,領域 2 3の表面に酸化シリ コン膜 3 6 Cと窒化 シリ コン膜 3 6 Βが作られる。 その上にリ ンドープされたポリ シリコンによつ て約 1 ミ クロンの第 2転送電極 3 7 ( Α , Β , C )が作られる。 上記の第 2転送電 極はチヤンネルス ト ップ領域 2 3の上方で垂直方向に延びる分岐電極 3 7 Xを 持つ。 そして第 2転送電極は酸化されて、 その表面に酸化シリ コン膜 3 6 Αが 作られる。 そして分岐電極 3 7 X上の酸化膜はエッチングされて、 分岐電極 3 7 Xは露出する。 そしてその上にリ ンドープされだポリシリコンによって約 0 · 0 6 ミ クロン厚の第 1転送電極 3 5 ( A，B , C )が作られる。 そして第 1転送電 極は露出した分岐転送電極 3 7 Xの表面と側面において、 第 1転送電極と接続 される。 その結果転送電極 3 7 Aと 3 5 Aは等価的に 1個の転送電極になり、 転送電極 3 7 Bと 3 5 Bは等価的に 1個の転送電極になる。 図 2 7は図 2 6と 直角方向の断面図であり、 図 2 8は図 2 5 ,図 2 6の 1実施例平面図である。 以下に上記の実施例の説明が追加される。 On an N-type substrate (4 × 10 {14} atoms / CC) 20, a P-type well region (2 × 10 [15] atoms ZC C) 32 is arranged. An N-type bulk channel region (10 [1 6} atoms / CC) 22 is disposed thereon. Polon ions are implanted into the surface of the first region 22 A of the N-type bulk channel region 22 to form a potential barrier region 3. The channel region 22B other than the potential barrier region 34 is a potential well region. Bulk tea Between the channel regions 22, a P-type channel stop region (4 X 10 M 7] atom CC) 23 is created. A silicon oxide film 36 C and a silicon nitride film 36 作 are formed on the surfaces of the regions 22 and 23. A second transfer electrode 37 (Α, Β, C) of about 1 micron is formed on this by the doped silicon. The above-mentioned second transfer electrode has a branch electrode 37 X extending vertically above the channel stop region 23. Then, the second transfer electrode is oxidized to form a silicon oxide film 36 に on the surface thereof. Then, the oxide film on the branch electrode 37X is etched, and the branch electrode 37X is exposed. Then, a first transfer electrode 35 (A, B, C) having a thickness of about 0.6 μm is formed by the polysilicon doped with phosphorus. The first transfer electrode is connected to the first transfer electrode on the exposed surface and side surface of the branch transfer electrode 37X. As a result, the transfer electrodes 37 A and 35 A are equivalently one transfer electrode, and the transfer electrodes 37 B and 35 B are equivalently one transfer electrode. FIG. 27 is a cross-sectional view in a direction perpendicular to FIG. 26, and FIG. 28 is a plan view of one embodiment of FIGS. 25 and 26. The description of the above embodiment is added below.
図 3 (Aから Fの追加説明） この 1 シフ ト レジスタ駆動形 1 E / B転送センサ の基本的な特徵はシフ トレジスタの各転送段から出力されたクロック電圧が垂 Lt C C Dの各 D V T Gを制御し、 そして垂直転送を実施する前に上記のシフ ト レジスタの各出力接点は深い電位 V Hにリセッ トされ、 そしてシフ トレジスタ の入力端 2 Cから浅い電位 V Lと深い電位 V Hを交互に入力する事である。 好 ましい 1実施例において、 浅い電位 V Lを持つシフ トレジスタの奇（偶）数番目 の転送段が^い電位 V Hになった後で、 シフ トレジ タの偶（奇）数番目の耘送 段は深い電位 V Hから浅い電位 V Lに変化する。 上記の動作はダイナミ ックシ フ トレジスタを使用する事によって簡単に実施できる。 たとえば奇（偶）数番目 の耘送段の出力用インバーターと偶（奇）数番目の転送段の出力用ィンバータ一 が交互に充電動作と論理放電（評価）動作を交互に実施するダイナミ 'ソ クシフ ト レジスタにおいて、 常に片方の出カインバ一タの充電動作をもう片方の評価動 作に先 ί7するように設計すれば良い。 この 1 シフ ト レジスタ駆動 1 E / B転送エリアセンサにおいて、 垂直 C C Dの 1 D V T G当たりシフ トレジスタの 1転送段（2ィンバータ）を必要とするので、 垂直画素行ピッチを小さくできない欠点を持つ。 ただし、 シフ トレジスタ 2 A の出カインバータはレシオレス一ダイナミ ック構造を持つ事ができ、 2 E / B 転送エリァセンサの C M O S シフ ト レジスタに比铰して消費電力の節約と製造 工程の省略が可能になる。 垂直走査線の容量が大きい為に、 C M O Sシフ トレ ジスタの出力インバータはかなり大きな過渡電流を消費する。 更に上記のレシ ォレス出カインバータのプリチャージ期間 Pは浅い電位 V Lを持つ垂直走査線 を再び深い電位 V Hに充電した後で、 次の評価（放電）動作'を実施するので、 非 常に転送動作が安定する。 上記のレシォレス一ダイナミ ックシフ ト レジスタの 構造は基本的に図 5のシフ ト レジスタ 2 Aまたは 2 Bと同じであり、 シフ トレ ジスタ各出力接点 1 2 Aが各垂直走査線に順番に接続される。 Figure 3 (Additional explanation of A to F) The basic feature of this 1 shift register drive type 1 E / B transfer sensor is that the clock voltage output from each transfer stage of the shift register controls each DVTG of Lt CCD Before performing the vertical transfer, the output contacts of the shift register are reset to the deep potential VH, and shallow potential VL and deep potential VH are alternately input from the input terminal 2C of the shift register. It is. In one preferred embodiment, the odd (even) transfer stage of the shift register having a shallow potential VL is at a high potential VH before the even (odd) tilling stage of the shift register. Changes from a deep potential VH to a shallow potential VL. The above operation can be easily implemented by using a dynamic shift register. For example, an output inverter of an odd (even) number feed stage and an output inverter of an even (odd) number transfer stage alternately perform a charge operation and a logic discharge (evaluation) operation alternately. The shift register may be designed so that the charging operation of one of the output converters always precedes the evaluation operation of the other. This 1 shift register driven 1 E / B transfer area sensor requires one transfer stage (two inverters) of shift register per DVTG of vertical CCD, and thus has the disadvantage that the vertical pixel row pitch cannot be reduced. However, the output inverter of the shift register 2A can have a ratioless dynamic structure, which saves power consumption and eliminates the manufacturing process compared to the CMOS shift register of the 2E / B transfer area sensor. become. Due to the large capacitance of the vertical scan lines, the output inverter of the CMOS shift register consumes a considerable amount of transient current. Furthermore, during the precharge period P of the above-mentioned ratio output inverter, the next evaluation (discharge) operation is performed after the vertical scanning line having the shallow potential VL is charged again to the deep potential VH. Becomes stable. The structure of the above-mentioned ratio dynamic shift register is basically the same as the shift register 2A or 2B in FIG. 5, and each output contact 12A of the shift register is sequentially connected to each vertical scanning line. .
(図 4 ( Aから F )の追加説明） この 2 シフ ト レジスタ駆動形 1 E ZB転送セン サにおいて、 第 1 シフ トレジスタの各転送段から出力されるク口ック電圧が垂 直 C C Dの奇（偶）数番目のクロック D V T Gに印加され、 そして第 2 シフ トレ ジスタの各転送段から出力されるクロヅク電圧が垂直 C C Dの偶（奇）数番目の クロッ ク D V T Gに印加される。 ただし 1転送段は 2相シフ トレジスタにおい て 2個のィンバーターで構成され、 どち'らかのィンバーター（出カインバータ 一と呼ばれる）の出力接点から上記のクロック電圧が出力される。 そして上記 の 2個のシフ トレジスタは出カインバーターが充電動作と保持動作と放電動作 ―.を ·¾互に実施するダイナミ ックシフ トレジスタである。 特に上記の出力インバ 一ターは出力抵抗を小さくできるレシオレスィンバ一ターである事が好ましい。 図 4 (Aから F )において、 第 1 と第 2 シフ ト レジスタの各出力接点は最初 V H を出力する。 そして第 1、 第 2 シフ ト レジスタの出カインバーターは充電、 評 価動作を交互に実施する。 好まし 、 1実施例において、 片方のシフ ト レジスタ の出カインバーターの充電動作は常に他のシフ トレジスタの出力インバーター の評価動作より先行する。 そして各シフ トレジスタの入力端 2 Cから浅い電位 V Lが順番に入力される。 図 4 Aから図 4 Bにシフ トする時に、 シフ ト レジス タ 2 Aの各出力接点は VHを出力し、 その後でシフ トレジスタ 2 Bが論理放電 を開始する。 即ちダイナミ 'ゾクシフ ト レジスタの充電動作によって各出力接点 に発生する深い電位 VHが有効に利用される。 この 2シフ ト レジスタ駆動 1 E ZB転送エリァセンサは高い集積度と小さい消費電力と簡単な製造工程を持つ。 (図 9の追加説明） この 1 シフ トレジスタ駆動形 2 E/B転送センサは 2相シ フ トレジスタの 1 / - 転送段からそれぞれ出力される即ち各ィンバーターの出 力接点からそれぞれ出力されるクロック電圧を垂直 C CDの各クロッ ク ND V TGに印加する。 そしてシフ トレジスタの奇（偶）数番目の出力接点は最初に V Lを出力し、 その偶（奇）数番目の出力接点は VHを出力する。 そしてシフ トレ ジスタの入力端から V Lと V Hを交互に入力し、 そしてシフ ト.レジスタの奇（偶 )数番目のインバーター 1 1 Aと偶（奇）数番目のインバーター 1 1 Bは交互に 論理放電動作と保持動作を実施する。 このシフ ト レジスタの各インバーターは 論理放電動作と保持動作を実施し、 充電動作を必要としないスタチックインバ —ター（特に CMO S)である事が好ましい。 レシオレスィンバーターを使用す る時に、 ィンバ一ターの充電動作時の出力接点電圧を垂直走査線から遮断する スイ ッチが必要になる。 なお、 図 9の垂直転送動作は図 1 0 (Aから H)と同じ であろ。 （図 1 0 ( Aから H)の追加説明） この 2シフ ト レジスタ駆動形 2 Eノ B耘送センサにおいて、 垂直 C CDの奇（偶）数番目のクロ ッ ク ND V T Gは第 1 シフ ト レジスタの各転送段からそれぞれ出力されるクロック電圧を印加され .る。' そしてその偶（ f)数番目のク.口ック NDVT.Gは第 2シフ ト レジスタの各. 転送段からそれぞれ出力されるクロ 'ソク電圧を印加される。 勿論 1転送段はた とえば 2相シフ トレジスタにおいて、 2インバーターで構成される。 そして最 初に第 I シフ ト レジスタの各転送段は V Lを出力し、 第 2シフ ト レジスタの各 転送段は V Ηを出力する。 そして第 1、 第 2シフ ト レジスタ各出力インバータ 一は交互に保持動作と放電動作を実施する。 そして第 1 (または第 2)シフ トレ ジスタの入力端から V Lと V Ηが交互に入力される。 垂直 C CDが図 1 O Aか ら図 1 0 Bにシフ トする時に、 左側に配置されるシフ トレジスタ 2 Aは 1転送 段シフ トし、 垂直 C CDが図 1 0 Bから図 1 0 Cにシフ トする時に、 右側に配 置されるシフ トレジスタ 2 Bは 1転送段シフ トォる。 （図 1 6 (Aから L)の追 加説明） 図 1 6 (Aから L)によって、 図 1 4 ,図 1 5の 2クロック線駆動形 1 EZB転送センサの垂直耘送動作が説明される。 シフ ト レジスタ 2は 1転送段 当たり 1出力接点を持ち、 好ましくは 2相シフ ドレジスタである。 で 1期間に- シフ トレジスタ 2の各出力接点は V Hを出力し、 総ての順次スィヅチ 1 6 (Z から V)は導通し、 そしてクロック線 27ノ， 2 Y'は VHになり、 各垂直走査線 3 (Zから V)は VHになり、 各クロック DVTG 3 (Zから V)の下に信号電荷 Q 1から Q 5が蓄積さ'れる。 I Tセンサにおいて T 1期間にクロック線 2 Z' , 2 Y'に読みだし電極 V Rが印加される。 次にシフ トレジスタの各出力接点は VLになり、 各順次スィツチ 1 6 (Zから V)は遮断される。 （図 23 (Aから L) の追加説明） 図 23 (Aから L)によって、 図 2 1 ,図 2 2のクロツク線駆動形 中間電位 1 E/B転送センサの垂直転送動作が説明される。 シフ ト レジスタ 2 は 1転送段当たり i出力接点を持つ。 そして垂直転送を実施する前の T 1期間 に、 シフ ト レジスタ 2の各出力接点は V Hになり、 各順次スイッチ 1 6 (Z , X， V.T)は導通し、 クロック線 2 Υは中間電位 VMになる。 そして図 2 3 Αに説 明されるように各信号電荷 Q 1から Q 7が各クロック D VT G(3 Z、 3 X .3 V, 3 T)の下の電位丼戸とその間に配置される中間直流電位井戸に蓄積される。 そして T "1期間の終わりにクロック線 2 Yは V Lになり、.各クロック DV T G は V Lになる。 その後で、 シフ トレジスタの各出力接点は VLになり、 各順次 スィツチは遮断される， シフ トレジスタの各出力接点を一斉に VHまたは V L に設定するにはシフ トレジスタの出カインバーターの充電スィツチを導通し、 上記の充電スィツチを介して垂直走査線の電位を制御すれば良い。 (Additional explanation of Fig. 4 (A to F)) In this 2-shift register driven 1E ZB transfer sensor, the output voltage from each transfer stage of the 1st shift register is the odd voltage of the vertical CCD. The clock voltage output from each transfer stage of the second shift register is applied to the (even) th clock DVTG, and the even (odd) clock DVTG of the vertical CCD. However, one transfer stage is composed of two inverters in a two-phase shift register, and the clock voltage is output from the output contact of one of the inverters (called the output inverter 1). The above two shift registers are dynamic shift registers in which the output inverter alternately performs a charging operation, a holding operation, and a discharging operation. In particular, the output inverter is preferably a ratio inverter capable of reducing the output resistance. In Figure 4 (A to F), each output contact of the first and second shift registers outputs VH first. The output inverters of the first and second shift registers alternately perform charging and evaluation operations. Preferably, in one embodiment, the charging operation of the output inverter of one shift register always precedes the evaluation operation of the output inverter of the other shift register. And a shallow potential from the input terminal 2 C of each shift register VL is input in order. When shifting from Fig. 4A to Fig. 4B, each output contact of shift register 2A outputs VH, after which shift register 2B starts logical discharge. That is, the deep potential VH generated at each output contact due to the charging operation of the Dynamix shift register is effectively used. This 2-shift register driven 1E ZB transfer area sensor has high integration, low power consumption and simple manufacturing process. (Additional explanation for Fig. 9) This 1 shift register drive type 2 E / B transfer sensor outputs the clock voltage output from the 1 /-transfer stage of the 2-phase shift register, that is, the clock voltage output from the output contact of each inverter. Is applied to each clock ND V TG of the vertical CCD. The odd (even) output contacts of the shift register output VL first, and the even output contacts output VH. VL and VH are alternately input from the input terminals of the shift register, and the odd (even) -numbered inverter 11A and the even (odd) -numbered inverter 11B of the shift register are alternately logically connected. The discharging operation and the holding operation are performed. Each inverter of this shift register performs a logical discharge operation and a holding operation, and is preferably a static inverter (especially CMOS) which does not require a charging operation. When using the ratioless inverter, a switch is required to cut off the output contact voltage from the vertical scanning line during the charging operation of the inverter. Note that the vertical transfer operation in FIG. 9 is the same as in FIG. 10 (A to H). (Additional explanation of Fig. 10 (A to H)) In this 2-shift register-driven 2E-no-B tilling sensor, the odd (even) clock ND VTG of the vertical CCD is the first shift. The clock voltage output from each transfer stage of the register is applied. 'The even (f) -th clock NDVT.G is applied with the clock voltage output from each transfer stage of the second shift register. Of course, one transfer stage is composed of, for example, two inverters in a two-phase shift register. First, each transfer stage of the I shift register outputs VL, and each transfer stage of the second shift register outputs V 出力. The output inverters of the first and second shift registers perform the holding operation and the discharging operation alternately. Then, VL and VΗ are alternately input from the input terminal of the first (or second) shift register. Figure 1 OA vertical CCD When shifting to Figure 10B, shift register 2A on the left shifts by one transfer stage, and when the vertical CCD shifts from Figure 10B to Figure 10C, it shifts to the right. The shift register 2B is shifted by one transfer stage. (Additional explanation of Fig. 16 (A to L)) Fig. 16 (A to L) explains the vertical tilling operation of the two-clock-line-driven 1 EZB transfer sensor in Figs. 14 and 15 . Shift register 2 has one output contact per transfer stage, and is preferably a two-phase shift register. In one period, each output contact of the shift register 2 outputs VH, all the sequential switches 16 (Z to V) conduct, and the clock lines 27 and 2 Y 'become VH, and each vertical switch becomes VH. Scan line 3 (from Z to V) becomes VH, and signal charges Q1 to Q5 are accumulated under each clock DVTG 3 (from Z to V). In the IT sensor, the read electrodes VR are applied to the clock lines 2Z 'and 2Y' during the period T1. Next, each output contact of the shift register becomes VL, and each sequential switch 16 (from Z to V) is shut off. (Additional explanation of Fig. 23 (A to L)) Fig. 23 (A to L) describes the vertical transfer operation of the clock line drive intermediate potential 1 E / B transfer sensor of Figs. 21 and 22. Shift register 2 has i output contacts per transfer stage. Then, during the T1 period before the vertical transfer is performed, each output contact of the shift register 2 becomes VH, each switch 16 (Z, X, VT) is sequentially turned on, and the clock line 2 2 is connected to the intermediate potential VM. become. Then, as explained in Fig. 23Α, each signal charge Q1 to Q7 is arranged between the potential bowl door under each clock D VTG (3Z, 3X.3V, 3T) and between them. Is accumulated in the intermediate DC potential well. At the end of the T1 period, clock line 2Y goes to VL, and each clock DV TG goes to VL. Thereafter, each output contact of the shift register goes to VL, and each switch is turned off sequentially. To set all output contacts of the shift register to VH or VL at the same time, the charge switch of the output inverter of the shift register should be made conductive, and the potential of the vertical scanning line should be controlled via the above-mentioned charge switch.
図 5のシフ トレジスタの他の動作モ一ドが図 2 9によつて説明される。 Pは充 電スィプチ 8 Aまたは 8 Bが導通し、 放電スイッチ 1 0 A , 1 0 Bが遮断され る期間であり、 Eは充電スィッチが遮断され、 放電スィッチが導通する期間で あり、 保持期間は充電、 放電スィ ッチが遮断される期間である。 図 5では充電 期間 Pに前段の接続スィツチ 7 A， 7 Bが導通して論理情報が入力されるが、 それらを別々に実施する事も可能である。 この実施例の特徴は出カインバータ 1 1 Aが P ,Η,Εの順に動作し、 そしてインバータ 1 1 8が£,11,?の順に動 作する事である。 そしてシフ トレジスタ 2 Αはシフ トレジスタ 2 Βと 1 8 0度 異なる位相を持つ。 垂直 C C Dが 1画素行の信号電荷を出力する為に、 各イン バータは上記の Ρ ΗΕ動作を 1サイクル実施する。 なお、 垂直転送期間の終わ りに、 シフ トレジスタ 2 Αまたは 2 Bのどちらかの出力接点はすべて浅い電位 V Lを持つ。 従って浅い電位 V Lを出力するシフ トレジスタを 1 2転送段（1 ィンバータ）だけシフ トすればすべての垂直走査線を深い電位 V Hにリセ'ソ ト でさる。 また共通転送電極形 I Tセンサにおいて、 充電期間 Pに電源電圧 VD を読みだし電圧 V Rに変更する事によって、 画素の信号電荷を垂直 C CDに転 送できる。 図 3 0は図 4 (Aから F)または図 9または図 1 0 (Aから L)または 図 1 4または図 2 1のシフ ト レジスタの 1実施例等価回路図である。 図 3 0の リセッ トスイッチ 1 3にリセヅ ト電圧 VR Cを印加する事によって、 CMO S 出力インバータの入力接点がリセッ トされる。 ただし、 図 9の突施例において、 図 3 0のシフ トレジスタ 2 Aだけが使用され、 そしてその各インパータ 1 1 A と 1 ί Βの出力接点が垂直走査線に接続される。 ただし、 図 1 4と図 2 1の実 施例において、 図 3 0のシフ ト レジスタ.2 Αだけが使用される。 これらの実施 例における CMO Sシフ トレジスタの動作に関しては本発明者 iこよって出願さ れた特出 5 9— 2 1 1 7 9 7を参照されたい。 ■ . Another mode of operation of the shift register of FIG. 5 is described with reference to FIG. P is the period during which the charge switch 8A or 8B conducts and the discharge switches 10A, 10B are shut off, and E is the period during which the charge switch is shut off and the discharge switch conducts. Yes, the retention period is the period during which the charge and discharge switches are cut off. In FIG. 5, the preceding connection switches 7A and 7B conduct during the charging period P to input the logic information, but these can be implemented separately. The feature of this embodiment is that the output inverter 11 A operates in the order of P, Η, Ε, and the inverter 11 18 operates in the order of £, 11,?. Shift register 2Α has a 180 ° phase difference from shift register 2Β. In order for the vertical CCD to output the signal charge of one pixel row, each inverter performs the above operation for one cycle. At the end of the vertical transfer period, all output contacts of either shift register 2Α or 2B have shallow potential VL. Therefore, if the shift register that outputs the shallow potential VL is shifted by 12 transfer stages (one inverter), all the vertical scanning lines can be reset to the deep potential VH. In the common transfer electrode type IT sensor, the signal charge of the pixel can be transferred to the vertical CCD by reading the power supply voltage VD during the charging period P and changing it to the voltage VR. FIG. 30 is an equivalent circuit diagram of one embodiment of the shift register of FIG. 4 (A to F) or FIG. 9 or FIG. 10 (A to L) or FIG. 14 or FIG. By applying the reset voltage VRC to the reset switch 13 in FIG. 30, the input contact of the CMOS output inverter is reset. However, in the embodiment of FIG. 9, only the shift register 2A of FIG. 30 is used, and the output contacts of the respective inverters 11A and 1A are connected to the vertical scanning lines. However, in the embodiments of FIGS. 14 and 21, only the shift register .2 # of FIG. 30 is used. For the operation of the CMOS shift register in these embodiments, see Japanese Patent Application Laid-Open No. 59-2191197 filed by the inventor i. ■.
3 1は図 5の 2相レシオレス一ダイナミ ッ クシフ ト レジスタの変形実施例を 表す等価回路図である。 この周知の 2相シフ トレジスタの原理は図 5の 2相シ フ ト レジス夕と基本的に同じであり、 その動作説明は省略される。 放 ¾1スイツ チ 1 Ο Α, Ι O Bを省略したこの 2相レシオレス一ダイナミ ッ ク シフ ト レジス タを使用すれば、 シフ トレジスタをより小さくでき、 画素密度を改善できる。  31 is an equivalent circuit diagram showing a modified embodiment of the two-phase ratioless dynamic shift register of FIG. The principle of this well-known two-phase shift register is basically the same as that of the two-phase shift register shown in FIG. 5, and the description of its operation is omitted. If this two-phase ratio-less dynamic shift register is used without the first switch, the shift register can be made smaller and the pixel density can be improved.
[¾]3 2は図 3 1の々 π■«；ク電 ΐ「 であり、 クロックを簡単にすろ為に、 2個の シフ ト レジスタ 2 A, 2 Bの充電期間 Pと評価（放電）期間 Eは重なる。 図 3 3 は図 5の 2 シフ トレジスタ駆動形 1 EZB転送によって垂直 C C Dを駆動する フレーム転送エリァセンサのプロヅク回路を表す。 画素列を兼ねる垂直 C C D によって構成されるィメージ領域 1 と水平 C CD 5の間に、 パッファ C CDに よって構成される蓄積領域 4 Cが配置される。 そして上記の蓄積領域 4 Gと水 平 C C D 5の間にトランスファーゲート 4 Aが配置される。 イメージ部 1の垂 直 C C Dは図 4 (Aから F)で説明される 1 EZB転送法で信号電荷を垂直帰線 期間に転送する。 蓄積部 4 Cのバッファ C CDは垂直 C CDから受け取る信号 電荷を一時的に蓄積する。 上記のバッファ C C Dはシフ トレジスタ 2 A， 2 B と同じ構造を持つシフ トレジスタ 2 D , 2 Eによって駆動される。 ただし、 シ フトレジスタ 2 D , 2 Eは垂直帰線斯間の最初に図 4 Fと同じ初期状態を持つ。 そしてその後で実施される高速転送期間の前半に、 バッファ C CDは 2柜クロッ ク転送を実施する。 この 2相クロック転送はシフトレジスタ 2 D (または 2 E) に浅い電位 V Lを注入し、 そしてシフ トレジスタ 2 E (またはシフ ト レジスタ 2 D)に深い電位 V Hを注入する事によって簡単に実施できる。 そして上記の 高速転送期間の後半に（即ち垂直 C C Dから転送された信号電荷がバッフ ァ C C Dの入力端に到着した後で）、 上記のシフトレジスタ 2 D (または 2 E)に深 い電位 V Hを順次注入する。 このようにすれば D V T Gを備えるバッファ C C Dの各電位井戸にそれぞれ 1画素行の信号電荷を蓄積する事ができる。 そして 次の垂直走査期.間内の水平帰線期間毎に上記のバッフ了 C C Dは i:記の 1 EZ B耘.送法によって、 信号電荷を水平 C CDに出力する。 図 3 4 (Aから _D)はバッ ファ C GDの高速転送期間の前半の一部を表す 送状態図であり、 動作は図 3 4 Aから図 3 4 Dへ進行する。 図 3 4 (Eから H)は上記の高速転送期間の後半 の一部の期間を表す転送状態図であり、 動作は図 3 4 Eから図 3 4 Hへ進行す る n 即ち上記のシフトレジスタ 2 D (または 2 E)に注入する転送パルス情報を 高速転送期間の後半に浅い電位 V Lから深い電位 V Hに変化させる事によって、 バ、ソファ C. C Dを構成する各 D VT Gの下に信号電荷を蓄積する事が可能 になる。 垂直 C C Dの垂直転送と、 バッファ C C Dから水平 C C Dへの転送は いま.まで説明された 1 E/B転送 であり、 詳細な説明は省略される。 図 3 4 (Aから F)において、 バッファ C C D 6 Cの電位井戸 3 Z， 3 X , 3 V , 3 Tの 上に配置される各 D V T G (方向性転送電極）は 2相 C M 0 Sシフ ト レジスタ 2 Dによって駆動されるつ 同様に、 バッファ C CDの電位井戸 3 Y, 3 W, 3 Uは 2相 CMO Sシフ トレジスタ 2 Eによって駆動される。 2 F .2 Gはその入力 端である。 便宜上バッファ C C Dの電位井戸番号は垂直 C C Dの電位井戸番号 と重複する。 図 3 5は図 3 3、 図 3 4 (Aから H)の 2シフ ト レジスタ駆動 1 E ZB-転送 F Tエリァセンサの転送状態図である。 tOは垂直走査期間の最初の 状態を表し、 t 1から 1:5は高速転送期間の前半を表し、 t 6から t9はその後半 を表す。 そして垂直走査期間 Tvにバ'ソファ C C Dの信号電荷 Q 1から Q 5は 順番に出力される。 そして垂直帰線期間の終わりに垂直 C CD 6の全垂直走査 線は深い電位 V Hに充電される。 この充電は上記の高速転送の実施によって、 またはリセッ トスィツチの使用によって可能になる。 図 3 3 ,図 3 4に開示さ れろフレーム転送エリァセンサの転送動作は Theuwissen.アコ一デオンィメ一 ジャ、 論文番号 2. 6、 I EDM 8 4に開示される技術と本質的に同じである ただし上 dのアコ一デオンイメージャにおいて、 垂直 C C Dとバッファ C C D は N D V T Gを備え、 その C MO Sシフ ト レジスタは図 9に開示される 1 シフ トレジスタ 2 EZB転送法を使用する。 C VIO Sシフ ト レジスタは複雑な製造 工程を持ち、 歩どまりが悪くなる欠点と、 小さい出力インバ一タによって大き な垂直走査線容量を充放電する為に過渡電流が大きくなる欠点を持つ。 そ 結 粜消費電力が大きくなりチ，ソプの温度上昇によって暗電流が増加する。 図 3 3 , 図 3 4 (Λから H)に開示されろ 1 E /Bアコ一デオンイメージャはレシオレス —ダイナミ ヅ クシフ トレジスタを使用するので、 これらの問題は大巾に改善さ れる。 なお、 図 1 4の 2クロック線駆動 1 E 耘送法を使用するアコーデォ ンイメージャはシフ トレジスタをより簡単にできる利点を持つ。 なお上記の文 献に開示される 2 E/B転送形アコ一デオンイメージャにおいて、 図 1 0 (A から H)に開示される 2シフ ト レジスタ 2 E/B転送法を使用する事ができる。 即ち N D V T Gによつて構成された垂直 C C Dが図 1 0 (Άから H)に説明され る 2個の C M 0 Sシフ トレジスタによつて駆動され、 そして同様にバッファ C CDも 2個の CMO Sシフ ト レジスタによって駆動される。 そして高速転送期 間の前半においてバッファ C CDを駆動する各シフ トレジスタの入力端から浅 い電位 V Lと深い電位 VHが交互に注入され、 バッファ C CDは実質的に 4相 クロックで駆動される。 そして上記の高速転送期間の後半に（即ち、 垂直 C C Dから注入された信号電荷がバツファ C CDの入力端に到達した後で），バッファ C CDを駆動する第 1のシフ ト レジスタの入力端から浅い電位 VLを注入し、 そしてバッファ C CDを駆動する第 2のシフトレジスタの入力端から深い電位 VHを注入する。 このようにすればバッファ C CDの奇（偶）数番目の ND VT Gの下に信号電荷を蓄積する事ができる。 そして次の垂直走査期間内の水平'厣 線期間毎に上記のにバッファ C CDは 2シフ トレジスタ駆動 2 EZB転送法に よって、 信号電荷を水平 C C Dに出力する。 即ちバッファ C C Dを駆動する 2 倆の CMO Sシフ ト レジスタの入力端に注入する転送パルス情報を制御する事 によって、 バッファ C CDに 2個の ND VT G当たり 1画素行の信号電荷を蓄 積ォる事がでさる。 この 2シフ トレジスタ駆動 2 EZB転送アコ一デオンィメ ージャにおいて、 垂直 C CDまたはバッファ C C Dの動作は本質的に上記の文 献に記載される 1 シフ トレジスタ駆動 2 E ZB転送ァコーデオンイメージャま たは上記の 2シフ トレジスタ駆動 1 E /B転送ァコ一 オンイメージャと同じ . で る。 従" てその cな幾作説明は省略される。 本発明の 2シフ トレジスタ 駆動 2 EZB転送アコ一デオンイメージャは 2個の CMO Sシフ トレジスタを 備え、 各シフ トレジスタの奇（偶）数番目のインバー夕が出カインバータになる。 以下に上記の実施例の説明が捕足される。 [¾] 3 2 is π ■ «in Fig. 3 1; to make the clock easier, two The charge period P of shift registers 2A and 2B and the evaluation (discharge) period E overlap. FIG. 33 shows a block circuit of a frame transfer area sensor that drives a vertical CCD by two-shift register driving 1 EZB transfer of FIG. Between an image area 1 constituted by a vertical CCD also serving as a pixel column and a horizontal CCD 5, a storage area 4C constituted by a buffer CCD is arranged. Then, a transfer gate 4A is arranged between the storage area 4G and the horizontal CCD 5. The vertical CCD in the image section 1 transfers signal charges during the vertical blanking period by the 1 EZB transfer method described in Fig. 4 (A to F). The buffer CCD of the storage unit 4C temporarily stores signal charges received from the vertical CCD. The above buffer CCD is driven by shift registers 2D and 2E having the same structure as shift registers 2A and 2B. However, the shift registers 2D and 2E have the same initial state as FIG. Then, in the first half of the subsequent high-speed transfer period, the buffer CCD performs a 2 CD clock transfer. This two-phase clock transfer can be easily implemented by injecting the shallow potential VL into the shift register 2D (or 2E) and the deep potential VH into the shift register 2E (or the shift register 2D). Then, in the latter half of the high-speed transfer period (that is, after the signal charges transferred from the vertical CCD arrive at the input terminal of the buffer CCD), the deep potential VH is applied to the shift register 2D (or 2E). Inject sequentially. In this way, signal charges of one pixel row can be stored in each potential well of the buffer CCD having the DVTG. Then, for each horizontal retrace period in the next vertical scanning period, the above-mentioned buffer CCD outputs the signal charges to the horizontal CCD by the 1 EZ B tilling method described in i :. FIG. 34 (A to _D) is a transmission state diagram showing a part of the first half of the high-speed transfer period of the buffer CGD, and the operation proceeds from FIG. 34A to FIG. 34D. 3 4 (H from E) is a transfer state diagram showing a part of a period of the second half of the high-speed transfer period of the operation is 3 4 3 4 you proceed to H n that is, the shift register from E By changing the transfer pulse information to be injected into 2D (or 2E) from the shallow potential VL to the deep potential VH in the latter half of the high-speed transfer period, the signal below each D VT G that composes Charge can be stored become. The vertical transfer of the vertical CCD and the transfer from the buffer CCD to the horizontal CCD are the 1 E / B transfer described so far, and detailed description is omitted. In Fig. 34 (A to F), each DVTG (directional transfer electrode) placed on the potential wells 3Z, 3X, 3V, and 3T of the buffer CCD 6C is a two-phase CM0S shift. Similarly, the potential wells 3Y, 3W, 3U of the buffer CCD are driven by the two-phase CMOS shift register 2E. 2 F .2 G is its input. For convenience, the potential well number of the buffer CCD overlaps with that of the vertical CCD. FIG. 35 is a transfer state diagram of the two-shift register drive 1 EZB-transfer FT area sensor of FIGS. 33 and 34 (A to H). tO represents the first state of the vertical scanning period, t1 to 1: 5 represent the first half of the high-speed transfer period, and t6 to t9 represent the second half. Then, during the vertical scanning period Tv, the signal charges Q1 to Q5 of the base CCD are sequentially output. Then, at the end of the vertical blanking period, all the vertical scanning lines of the vertical CCD 6 are charged to the deep potential VH. This charging is made possible by implementing the high speed transfer described above or by using a reset switch. The transfer operation of the frame transfer area sensor disclosed in FIGS. 33 and 34 is essentially the same as the technology disclosed in Theuwissen. Accordion Manager, Article No. 2.6, IEDM84. In the accordion imager of d, the vertical CCD and the buffer CCD have NDVTG, and their CMOS shift registers use the one shift register two EZB transfer method disclosed in FIG. The CVIOS shift register has the disadvantage that the manufacturing process is complicated, the yield is poor, and the transient current is large because a small output inverter charges and discharges a large vertical scanning line capacitance. Conclusion (4) The power consumption increases, and the dark current increases due to the rise in the temperature of the sop. These problems are greatly improved because the 1 E / B accordion imager uses a ratioless-dynamic shift register, as disclosed in FIGS. 33 and 34 (Λ to H). The accordion imager using the two-clock-line driving 1 E tiller method shown in Fig. 14 has the advantage that the shift register can be simplified. In addition, in the 2 E / B transfer type accordion imager disclosed in the above-mentioned publication, FIG. To H) can use the 2 shift register 2 E / B transfer method. That is, a vertical CCD composed of NDVTG is driven by two CM0S shift registers described in FIG. 10 (Ά to H), and similarly, a buffer CCD is also composed of two CMOS shifts. Driven by an external register. Then, in the first half of the high-speed transfer period, the shallow potential VL and the deep potential VH are alternately injected from the input terminal of each shift register that drives the buffer CCD, and the buffer CCD is driven substantially by a four-phase clock. Then, in the latter half of the high-speed transfer period (that is, after the signal charge injected from the vertical CCD reaches the input terminal of the buffer CCD), the input terminal of the first shift register for driving the buffer CCD starts. The shallow potential VL is injected, and the deep potential VH is injected from the input terminal of the second shift register that drives the buffer CCD. In this way, signal charges can be stored under the odd (even) ND VTG of the buffer CCD. Then, the buffer CCD outputs the signal charges to the horizontal CCD by the two-shift register driving two EZB transfer method for each horizontal scanning period in the next vertical scanning period. That is, by controlling the transfer pulse information injected into the input terminal of the two-level CMOS shift register that drives the buffer CCD, the signal charge of one pixel row per two ND VTGs is accumulated in the buffer CCD. It comes out. In this 2-shift register-driven 2 EZB transfer accordion imager, the operation of the vertical CCD or buffer CCD is essentially as described in the above document. 1-shift register driven 2 EZB transfer accordion imager or above 2 shift register drive of 1 E / B transfer code Same as on-imager. Therefore, the description of the c is omitted. The 2-shift register driving 2 EZB transfer accordion imager of the present invention includes two CMOS shift registers, and each shift register has an odd (even) number. The invertor becomes the output inverter, and the description of the above embodiment is added below.
好ましい 1実施冽において、 C CDのチャンネルは N形 あり、 そして浅い電 位 V Lはたとえば 0 V、 深い電位 VHはたとえば + 7 V、'最も深い読みだし電 ί VRは + 1 2 Vである。 勿論上記の VL .VH.VMは同じ部分の相対電位で あり、 たとえば転送電極の浅い電位 V Lと電位井戸の浅い電位 V Lは異なるレ ベルの電位である。 図 5の VDは高位電源であり、 V Sは低位電源である。 図 1 2、 図 1 7、 図 1 9の V L L , V L H, VM, V H L， V HHはそれぞれのチヤ ンネル領域の電位である。 図 3 5の〇は深い電位 V Hを持つ電位井戸を表し、 記号の無い電位井戸は浅い電位 V Lを持つ電位井戸である。 In a preferred embodiment, the CCD channel is N-shaped, and the shallow potential VL is, for example, 0 V, the deep potential VH is, for example, +7 V, and the 'deepest readout voltage VR is +12 V. Of course, the above VL.VH.VM is the relative potential of the same part. For example, the shallow potential VL of the transfer electrode and the shallow potential VL of the potential well are different levels of potential. VD in Fig. 5 is the higher power supply, and VS is the lower power supply. VLL, VLH, VM, VHL, and VHH in Figs. 12, 17, and 19 are the potentials of the respective channel regions. 〇 in FIG. 35 represents a potential well having a deep potential VH, and a potential well without a symbol is a potential well having a shallow potential VL.
将来のクレームの追加の為に、 本発明の他の特徴と効果が以下にまとめられる。 Other features and advantages of the invention are summarized below for further claims.
(A) , シフ ト レジスタ駆動 1 E/B転送法において、 レシオレス一ダイナミ ツ クシフ ト レジスタを使用する実施例。 消費電力を減らし、 工程を簡単にする。(A), Shift register drive 1 An embodiment using a ratioless dynamic shift register in the E / B transfer method. Reduce power consumption and simplify the process.
(B)，インタライン転送 C CDエリァセンサの垂直 C CDへの応用。 垂直 C C Dのダイナミ ヅクレンジを改善し、 そしてスメァノィズ電荷転送などの多くの 応用を可能にする。 （C),隣接 2画素行を 1水平走査期間に出力する C CDェ リアセンサへの応用。 本発明の EZB転送法によって、 隣接 2画素行 ZH出力 形垂直 C CDの構造を非常に簡単にし、 そしてダイナミ ックレンジを確保でき る。 特にこの実施例は I Tセンサを使用する単扳カラー TVカメ ラ、 またはフ レーム画像を出力するスチルカメラに大きな効果を持つ。 （D),アコ一デオン イメージャと して使用される 1 EZB耘送ェリアセンサ n 2シフ ト レジスタ駆 動形 1 E,ZBfe送ァ.コーデオンイメージャはシフ ト レジスタの製造工程を簡荦 にし、 そしてその消費電力を減らす。 また、 クロッ ク線駆動 1 EZB転送アコ —デオンィメ一ジャはシフ トレジスタの負荷容量を非常に小さくするので、 製 造が簡単であり、 高速転送に有利である。 E), 2シフ ト レジスタ駆動〖 E.Z B¾送アコ一デオンィメージャまたは 2シフ ト.レジスタ駆動 2 EZB耘送アコ —デオンイメージャは画素行密度が大きくても、 1 シフ ト レジスタ駆動アコ一 デオンィメージャに比较して出力インバ一タを大きく設計でき、 そして出カイ ンバータの入力電圧変化が速いので、 過渡電流が少ない。 (B), Application of interline transfer CCD area sensor to vertical CCD. It improves the dynamic range of a vertical CCD and enables many applications such as smearing charge transfer. (C), application to a CCD area sensor that outputs two adjacent pixel rows during one horizontal scanning period. With the EZB transfer method of the present invention, the structure of a vertical CCD with two adjacent pixel rows and a ZH output can be extremely simplified, and a dynamic range can be secured. This embodiment is particularly effective for a single color TV camera using an IT sensor or a still camera for outputting frame images. (D), used as accordion imager 1 EZB tilling area sensor n 2 shift register drive type 1 E, ZBfe transmitter. Cordion imager simplifies the manufacturing process of shift register, and Reduce its power consumption. In addition, the clock line drive 1 EZB transfer accumulator-de-on-measure makes the load capacity of the shift register extremely small, making it easy to manufacture and advantageous for high-speed transfer. E), 2 shift register drive 〖EZ B¾ transfer accordion imager or 2 shift. Register drive 2 EZB 送 transfer accord — Deon imager has higher pixel row density than 1 shift register drive accordion demagnifier. As a result, the output inverter can be designed to be large and the input voltage of the output converter can be changed quickly, so that the transient current is small.
「図面の簡単な説明」  "Brief description of the drawings"
図 1は独立発明 1の 1 シフ ト レジスタ駆動形 C I E/Bfe送エリァセンサの 1 実施例プロック回路図であり、 特に垂直走査線 3が撮像領域 1の両側に配置さ れるシフ ト レジスタ 2 A.2 Bによつて駆動される事を表す。 図 2は 2シフ ト レジスタ駆動形 G I EZB転送エリァセンサの 1実施例プロック回路図であり、 奇（偶）数行の垂直走査線 3 Aと偶（奇）数行の垂直走査線 3 Bが異なるシフ トレ ジスタ 2 A， 2 Bによって駆動される事を表す。 図 3 (Aから F)は 1 シフ トレ ジスタ駆動形 1 EZB転送エリァセンサの垂直転送状態図であり、 シフ トレジ スタ 2 Aの入力端 2-Cから転送パルス情報 V Lまたは VHを注入する事によつ て、 電位井戸 3 (Uから Y)の信号電荷 Q(2から 6)が転送される事を表す。 図 4 (Aから F)は 2シフ トレジスタ駆動形 1 E/B転送エリアセンサの垂直転送 状態図であり、 シフ トレジスタ 2 A, 2 Bの入力端から転送パルス情報を交互 に注入する事によって、 電位井戸 3 (Uから Y)の信号電荷 Q (2から 6)が転送 される事を表す。 図 5は図 4のシフ トレジスタ 2 A.2 Bの 1実施例等価回路 図であり、 シフ トレジスタの出力インバータ 1 1 Aが.レシオレス形インバータ である事を表す。 図 6は図 5のシフ トレジスタ 2 A.2 Bのクロヅク電圧図で ある。 図 7と図 8はシフ ト レジスタ駆動形 C I E ZB転送ェリアセンサのバヅ ファ回路の 1実施例等価回路図である。 図 9は 1 シフ ト レジスタ駆動形 2 EZ Βΐέ送エリァセンサの 1実施例等価回路図であり、 シフ ト レジスタ 2 Αの各出 力インバ一タ 1 1 A.1 1 Bの出力接点 1 2 Λ.1 2 Bに接統される垂直走査線 3 ( から W)の電位変化も表す。 図 1 0 (Aから H)は 2シフ トレジスタ駆動形FIG. 1 is a block diagram of an embodiment of a 1-shift register driven CIE / Bfe transmission area sensor of independent invention 1 according to an embodiment. In particular, vertical scanning lines 3 are arranged on both sides of an imaging area 1. It is driven by shift register 2 A.2B. FIG. 2 is a block diagram of a two-shift register-driven GI EZB transfer area sensor according to an embodiment of the present invention. The odd (even) number of vertical scanning lines 3A are different from the even (odd) number of vertical scanning lines 3B. It is driven by shift registers 2A and 2B. Figure 3 (A to F) is a vertical transfer state diagram of a 1 shift register drive type 1 EZB transfer area sensor, in which transfer pulse information VL or VH is injected from input terminal 2-C of shift register 2A. This means that the signal charge Q (2 to 6) of the potential well 3 (U to Y) is transferred. Fig. 4 (A to F) is a vertical transfer state diagram of a 2-shift register driven 1 E / B transfer area sensor, in which transfer pulse information is alternately injected from the input terminals of shift registers 2A and 2B. Indicates that signal charge Q (2 to 6) of potential well 3 (U to Y) is transferred. FIG. 5 is an equivalent circuit diagram of one embodiment of the shift register 2A.2B of FIG. 4, and shows that the output inverter 11A of the shift register is a ratioless inverter. FIG. 6 is a clock voltage diagram of the shift register 2A.2B in FIG. 7 and 8 are equivalent circuit diagrams of a buffer circuit of a shift register driving type CIE ZB transfer area sensor according to an embodiment. Fig. 9 is an equivalent circuit diagram of one embodiment of a 1 shift register drive type 2 EZ transmission area sensor.Each output inverter 1 1 A.1 1B of shift register 2 出力 output contact 1 2 Λ. The potential change of the vertical scanning line 3 (from W) connected to 1 2 B is also shown. Figure 10 (A to H) shows 2-shift register drive type
2 EZB転送エリァセンサの垂直転送状態図であり、 電位井 Pまたは電位障壁2 is a vertical transfer state diagram of the EZB transfer area sensor, showing a potential well P or a potential barrier.
3 (じから Z)の上に存在する非方向性転送電極（記載は省略されてい.る。 ）に印 力 []されるクロヅケ電圧の変化によって、 電位井戸 3 Ζ,.3 X , 3 Vの信号電荷 Q3 A non-directional transfer electrode (not shown.) On (Joint Z) is impressed. A change in the croquet voltage applied [] causes a potential well 3Ζ, .3 X, 3 V Signal charge Q
1 ,Q 2.Q 3が転送される事を表す。 基本的に図 9の垂直転送状態も図〖 0 (A から H)と同じである。 図 1 1 (Aから C)は 1 EZBfe送 I Tセンサの残留電 荷再配置図であり、 隣接すろ 2電位井戸の電荷の减算によって、 残留ノ イズ電 荷を相殺できる事を表す。 図 1 1 (Dから F)は 2 E/B転送 I Tセンサの残留 電荷再配置図であり、 隣接する 2電位井戸の減算によって、 残留ノイズ電荷を 相殺できる事を表す。 図 1 2は中間電位 VMを持つ非方向性転送電極 3 5をク 口ック DVT Gの間に備える 1 EZB転送エリァセンサの 1実施例断面図であ り、 この垂直 C C Dは前に説明されたシフ ト レジスタ駆動形 1 E B転送技術 ' または後で説明されるク口 'ソク線駆動形 1 EZB転送技術によって、 転送され る。 図 1 3は図 1 2の垂直 C C Dのチヤンネル電位図である。 図 1 4は 2クロヅ ク線駆動形 1 E/B転送エリァセンサの 1実 ¾伊 1駆動回路図である。 図 1 5は 図 1 4のクロ ック電圧 V 1 , V 2の波形図である。 図 1 6 (Aから L)は図 1 4 の駆動回路によって駆動される垂直 C CD 6の垂直転送伏態図であり、 その電 位井戸 3 (Zから U)の信号電荷 Q( 1から 6)は順番に転送される。 図 1 7は中 間電位を持つ方向性転送電極 3 Y， 3 Wがクロック D V T G 3 Yの間に配置さ- れる 1 EZB転送エリァセンサの 1実施例断面図であり、 この中間電位を持つ 転送電極（中間電極） 3 Y, 3 Wの下のチヤ ンネル領域 2 2 Aは中間電位井芦領 域 2 2 Bと中間電位障壁領域 2 2 Cによって構成される。 図 1 8は図 1 7の垂 直 C CDのチャンネル電位図である。 図 1 9は図 1 7の垂直 C CDの変形実施 例を表す 1実施例断面図であり、 中間電位を持つ非方向性転送電極 3. Y , 3 W を省略して、 中間チヤンネル領域 2 2 Aにイオン注入によって中間電位井戸領 域 34 Bと中間電位障壁領域 34 Cを作る事を表す。 図 2 0は図 1 9の垂直 C C Dのチャ ンネル電位図である。 図 2 1 は 1 クロック線駆動形 1 E Z B転送ェ リァセンサの 1実施例駆動回路図であり、 図 1 7と図 1 9に説明される垂直 C CDの駆動回路を表す。 図 2 2は図 2 1のクロック電圧 V 1の波形図である。 図 2 3 (Aから L)は図 2 1の駆動回路によって駆動さ.れる垂直 C C D 6の垂直 転送状態図であり、 その電位幷戸 3 (Zから丁）の信号電荷 Q(lから 8)は順番 に転送される。 図 24は独立発明 2のスメァノ イズ 1 H記憶 部分減算技術を 表す 1実施例等価回路図である。 図 2 5は独立発明 3のスメァノィズ記億回路 の 1実施例等価回路図である。 図 2 6は独立発明 4の 2電極結合形 F Tセンサ の 1実施例断面図であり、 垂直 C C Dのチャ ンネル領域 2 2を表ォ。 図 2 7は m 2 6の断面図に直角の断面図を表し、 並列に配置される複数の垂直 C C Dの チヤンネル領域 2 2 Bを表す。 図 2 8は図 2 6と図 2 7の垂直 C CDの 1実施 例平面図である。 図 2 9は図 5のシフ トレジスタの他の動作実施例を表すクロッ ク電圧図である。 図 3 0は図 1 0 (Aから H.)の 2シフ トレジスタ駆動 2 E / B 転送法に使用されるシフ トレジスタの 1実施例等価回路図である。 図 3 1は図 4 (Aから F )の 2 シフ ト レジスタ駆動 1 E ZB転送法に使用されるシフ トレジ スタの等価回路図である。 図 3 2は図 3 1 のシフ トレジスタのクロック電圧図 である。 図 3 3は 2 シフ トレジスタ駆動 1 E B転送法を使用するアコーデォ ンイメージャの 1実施例等価回路図である。 図 3 4 ( Aから H)は.図 3 3のバッ ファ C C Dとそれを駆動するシフ トレジスタの動作を表す転送状態図である。 図 3 5は図 3 3と図 3 4 ( Aから H)のアコ一デオンイメージャの動作を表す転 送状態図である。 1, Q 2. Indicates that Q 3 is transferred. Basically, the vertical transfer state in FIG. 9 is the same as in FIG. 0 (A to H). Fig. 11 (A to C) is a relocation diagram of the residual charge of the 1 EZBfe transmission IT sensor. It shows that the residual noise charge can be offset by calculating the charge of the adjacent two potential wells. Fig. 11 (D to F) is a residual charge relocation diagram of the 2E / B transfer IT sensor, showing that residual noise charges can be offset by subtraction of adjacent two potential wells. Figure 12 shows a non-directional transfer electrode 35 with an intermediate potential VM. FIG. 5 is a cross-sectional view of one embodiment of an EZB transfer area sensor provided between the DVT G and the vertical CCD. The vertical CCD is a shift register driven type 1 EB transfer technology described above or a cross-sectional view described later. 'Sound line drive type 1 Transferred by EZB transfer technology. FIG. 13 is a channel potential diagram of the vertical CCD of FIG. FIG. 14 is a diagram showing one driving circuit of one clock of the two clock line driving type 1 E / B transfer area sensor. FIG. 15 is a waveform diagram of the clock voltages V 1 and V 2 of FIG. FIG. 16 (from A to L) is a vertical transfer breakdown diagram of the vertical CCD 6 driven by the drive circuit of FIG. 14, and shows the signal charge Q (1 to 6) of the potential well 3 (from Z to U). ) Are transferred in order. FIG. 17 is a cross-sectional view of one embodiment of a 1 EZB transfer area sensor in which directional transfer electrodes 3 Y and 3 W having an intermediate potential are arranged between clocks DVTG 3 Y. (Intermediate electrode) The channel region 22A below 3Y and 3W is composed of a medium potential well region 22B and a medium potential barrier region 22C. FIG. 18 is a channel potential diagram of the vertical CCD of FIG. FIG. 19 is a cross-sectional view of one embodiment showing a modification of the vertical CCD of FIG. 17. Non-directional transfer electrode having an intermediate potential. 3. Y, 3 W are omitted, and the intermediate channel region 2 2 This means that the intermediate potential well region 34B and the intermediate potential barrier region 34C are created by ion implantation into A. FIG. 20 is a channel potential diagram of the vertical CCD of FIG. FIG. 21 is a driving circuit diagram of one embodiment of a 1-clock line driving type 1 EZB transfer error sensor, and shows a driving circuit of the vertical CCD described in FIGS. 17 and 19. FIG. 22 is a waveform diagram of the clock voltage V1 in FIG. FIG. 23 (from A to L) is a vertical transfer state diagram of the vertical CCD 6 driven by the drive circuit in FIG. 21. The signal charge Q (from l to 8) of the potential 3 (from Z to D) is shown. Are transmitted in order. FIG. 24 is an equivalent circuit diagram of one embodiment representing the technique of the independent 1H storage partial subtraction technique of the independent invention 2. FIG. 25 is an equivalent circuit diagram of one embodiment of the smearing memory circuit of the independent invention 3. FIG. 26 is a cross-sectional view of one embodiment of the two-electrode-coupled FT sensor according to Independent Invention 4, showing the channel region 22 of the vertical CCD. FIG. 27 shows a cross section perpendicular to the cross section of m 26, and shows the channel regions 22 B of a plurality of vertical CCDs arranged in parallel. Figure 28 shows one implementation of the vertical CCD shown in Figures 26 and 27. It is an example top view. FIG. 29 is a clock voltage diagram showing another operation example of the shift register of FIG. FIG. 30 is an equivalent circuit diagram of one embodiment of the shift register used in the 2-shift register driving 2 E / B transfer method of FIG. 10 (A to H.). FIG. 31 is an equivalent circuit diagram of the shift register used in the 2-shift register driving 1 EZB transfer method of FIG. 4 (A to F). FIG. 32 is a clock voltage diagram of the shift register of FIG. FIG. 33 is an equivalent circuit diagram of an embodiment of an accordion imager using a 2-shift register driven 1EB transfer method. FIG. 34 (A to H) is a transfer state diagram showing the operation of the buffer CCD of FIG. 33 and the shift register that drives it. FIG. 35 is a transfer state diagram showing the operation of the accordion imager of FIGS. 33 and 34 (A to H).

Claims

85/03398 4 7 讃 求 の 範 囲 85/03398 4 7 Range of praise
( 1 ) , 2次元配列された複数の画素と、 画素列を兼ねるかまたは画素列と独立 に配置された垂直 C C Dと、 水平 C CDを備え、 上記の垂直 C C Dは画素列の 信号電荷を水平 C CDに転送する固体撮像装置において、 上記の垂直 C CDは 方向性転送電極（D V T Gと略称される。 ）と非方向性転送電極（ND V T Gと 略称される。 ）のどちらかまたは両方を備え、 そして上記の D V T Gまたは N D V T Gの一部または全部は転送 ロヅク電圧が印加される転送電極（ク口ッ ク転送電極と略称される。 ）であり、 そして垂直 C C Dの出力端に近いクロッ ク転送電極から順番に転送ク口ヅク電圧が印加され、 そして垂直 C C Dの出力 端から注 された空の電位井戸が垂直 C C Dの出力端と反対端に到達する前に 次の空の電位井戸が垂直 C C Dの出力端から注入される事を特徵とする固体撮 像装置。  (1), equipped with a plurality of pixels arranged two-dimensionally, a vertical CCD that also serves as a pixel column or is arranged independently of the pixel column, and a horizontal CCD, and the above-described vertical CCD horizontally transfers the signal charges of the pixel column. In a solid-state imaging device for transferring to a CCD, the above vertical CCD includes one or both of a directional transfer electrode (abbreviated as DVTG) and a non-directional transfer electrode (abbreviated as ND VTG). A part or all of the above DVTG or NDVTG is a transfer electrode to which a transfer lock voltage is applied (abbreviated as a close transfer electrode), and a clock transfer electrode close to the output end of the vertical CCD. From the output end of the vertical CCD, and before the empty potential well injected from the output end of the vertical CCD reaches the end opposite to the output end of the vertical CCD, the next empty potential well becomes It is characterized by being injected from the output end That the solid imaging device.
(2) ;空の電位井戸が垂直 C C Dの出力端と反対端に到達した後で、 上記の垂 直 C CDのクロック転送電極に 1相または 2相または 4相クロック電圧を印加 する事を特徵とする第 1項記載の固体撮像装置。  (2); After the empty potential well reaches the output end of the vertical CCD, the one-phase, two-phase or four-phase clock voltage is applied to the clock transfer electrode of the vertical CCD. 2. The solid-state imaging device according to claim 1, wherein
(3 ).垂直 C C Dのオペての電位井戸の電荷を互いに独立に転送する事を特徴 とする第 1項記載の固体撮像装置。  (3). The solid-state imaging device according to (1), wherein the electric charges of the potential wells in the vertical CCD operation are transferred independently of each other.
( 4 ) ,クロック坛送電極である DVT G (クロ 'ソ ク D V T Gと略称される。 ）の 下に作られる電位井戸の電荷を独立に転送する事を特徵とすろ第〖項記載の固 体撮像装置。 .  (4) The solid state described in item (2) above is characterized in that the electric charge of a potential well formed under a DVT G (abbreviated as a clock DVTG), which is a clock transmission electrode, is independently transferred. Imaging device. .
(5),隣接する 2膪のクロック D V T Gの間のチヤ ンネル領域は中間直流電位 を持つ を特徴とする第 4項記載の固体撮像装置。 (5) The solid-state imaging device according to (4), wherein a channel region between two adjacent clocks D VTG has an intermediate DC potential.
( 6 ) ,クロック D V T Gの下に作られろ電位井戸と、 隣接する 2個のクロック D V T Gの間に配置される中間直流電位井戸の電荷を独立に転送する事を特徴 とする第 1項記載の固体撮像装置。  (6) The charge of the potential well formed under the clock DVTG and the charge of the intermediate DC potential well arranged between two adjacent clocks DVTG are independently transferred. Solid-state imaging device.
( 7 ) ,クロック転送電極である NDVT G (ク σ 'ソク NDVT Gと略称される。 ） を備え、 そして奇（偶）数番目のク口ック ND V T Gの下の電位丼戸の電荷を独 4 8 (7) NDVT G, which is a clock transfer electrode, is abbreviated as σ 'ク NDVT G. German 4 8
立に転送する事を特徵とする第 1項記載の固体撮像装置。 2. The solid-state imaging device according to claim 1, characterized in that the solid-state imaging device is configured to perform the transfer.
(8) ,垂直 C CDの出力端から注入された空の電位井芦が 2電位井戸ピツチだ け逆転送された後で、 次の空の電位井戸が垂直 C C Dの出力端から再び注入さ れる事を特徵とする第 1項記載の固体撮像装置。 ―  (8) After the empty potential well injected from the output terminal of the vertical CCD is reversely transferred by two potential well pitches, the next empty potential well is injected again from the output terminal of the vertical CCD. 2. The solid-state imaging device according to claim 1, characterized in that: ―
(9)，垂直 C CDの各クロック転送電極はシフトレジスタの出力接点または上 記のシフ トレジスタによって制御されるバッファ回路の出力接点に接続される 事を特徵とする第 1項記載の固体撮像装置。  (9) The solid-state imaging device according to item 1, wherein each clock transfer electrode of the vertical CCD is connected to an output contact of a shift register or an output contact of a buffer circuit controlled by the shift register. .
(1 0) ,上記のシフトレジスタの各 1 2転送段の出力接点、' または上記の各 (1 0), the output contact of each 12 transfer stage of the above shift register, 'or each of the above
1 /2転送段がそれぞれ制御する各バッファ回路の出力接点が垂直 C GDの各 クロック ND VT Gにそれぞれ接続される事を特徵とする第 9項記載の固体撮 像装置。 10. The solid-state imaging device according to claim 9, wherein the output contact of each buffer circuit controlled by each of the 1/2 transfer stages is connected to each clock NDVTG of the vertical CGD.
(1 1 ) ,上記のシフ トレジスタの各転送段の出力接点、 または上記の各転送段 がそれぞれ制御する各バッファ回路の出力接点がそれぞれ垂直 C CDの各クロッ ク D V T Gに接続される事を特徵とする第 9項記載の固体撮像装置。  (11) The output contact of each transfer stage of the shift register or the output contact of each buffer circuit controlled by each transfer stage is connected to each clock DVTG of the vertical CCD. 10. The solid-state imaging device according to claim 9, wherein
(1 2) ,垂直 C C Dの奇（偶）数番目のク口 'ソク転送電極（クロック NDVTGま たはクロック D VT Gを指定する）とその偶（奇）数番目のクロツク転送電極は 異なろシフ トレジスタの出力接点または異なろシフ ト レジスタによって制御さ れろバ 'ソ フ ァ回路の出力接点に接続される事を特徴とォる第 9項記載の固体撮  (1 2) The odd (even) clock transfer electrode (specifying clock NDVTG or clock DVTG) of the vertical CCD and its even (odd) clock transfer electrode are different. 10. The solid-state imaging device according to item 9, characterized in that the solid-state imaging device is connected to an output contact of a shift register or an output contact of a software circuit controlled by a different shift register.
(1 3).両素と垂直 C CDを電気的に接続する転送電極（以下において AT Gと 略称される.。 ）.が垂直 C C Ϊ)めクロック転送電極に接続されるインタライン転 送 C CDセンサ（以下において共通転送電極 I Tセンサと略称される。 ）であり、 そして上記のシフ ト レジスタまたはパ ヅファ回路の電源電圧の変更によって、 画素から垂直 C CDに信号電荷を転送する事を特徵とする第 9項記載の固体撮 (1 3) The transfer electrode (hereinafter abbreviated as ATG) that electrically connects the element and the vertical CCD is the interline transfer C connected to the vertical CC clock transfer electrode. It is a CD sensor (hereinafter abbreviated as a common transfer electrode IT sensor), and is characterized by transferring signal charges from pixels to the vertical CCD by changing the power supply voltage of the shift register or the buffer circuit. Solid-state imaging according to paragraph 9
( 1 4).垂直 C CDの各クロック DVT Gは順次スィツチを介して 1相または 2相クロ '；/ク電源に接続され、 そして上記の順次スィツチはシフトレ ジスタによって制御される事を特徵とする第 1項記載の固体撮像装置。 (14). Each clock DVT G of the vertical CCD is connected to a one-phase or two-phase clock power source via a sequential switch, and the above-mentioned sequential switch is shifted. 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is controlled by a resistor.
(1 5 ) ,垂直 C C Dの隣接する 2 §ίのクロック DVTGと 2相クロック電源を 接続する 2個の順次スィツチは同時に動作する事を特徵とする第 1 4項記載の 固体撮像装置。  (15) The solid-state imaging device according to item 14, characterized in that two sequential switches connecting a two-phase clock DVTG adjacent to the vertical CCD and a two-phase clock power supply operate simultaneously.
( 1 6 ),垂直 C C Dの各クロック転送電極は順次スィッチを介してクロック電 源によって駆動され、 そして上記のクロック DVTGまたは奇（偶）数番目のク ロック D V T Gは垂直転送期間の前に深い電位 V Hに充電され、 そして次の 垂直転送期間に各クロック転送電極は上記の順次スィ 'ソチを介してだけ電圧を 印加される事を特徵とする第 1項記載の固体撮像装置。  (16) Each clock transfer electrode of the vertical CCD is sequentially driven by a clock power supply via a switch, and the above-mentioned clock DVTG or the odd (even) th clock DVTG has a deep potential before the vertical transfer period. 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is charged to VH, and a voltage is applied to each clock transfer electrode only through the above-mentioned sequential switch during the next vertical transfer period.
(1 7) ,垂直転送期間の前に、 上記の各クロック DVT Gまたは奇（偶）数番目 のクロック NDVTGは上記の'ク口ック電源によつて深い電位 V H、 または読 みだし電位 V Rを印加される事を特徵とする第 1 6項記載の固体撮像装置。 (17) Before the vertical transfer period, each of the clocks DVTG or the odd (even) -numbered clocks NDVTG is supplied with the deep potential VH or the read potential VR by the above-mentioned power supply. 17. The solid-state imaging device according to claim 16, wherein the solid-state imaging device is applied.
(1 8) ,垂直 C CDのクロ 'ソク転送電極に転送クロック電圧を直接または間接 に印加するか、 または垂直 C C Dのクロヅク転送電極とクロック電源を接続す る順次スイッチを制御するシフ トレジスタは撮像部の両側に配置される事を特 徴とする第 1項記載の固体撮像装置。 (18) The shift register that applies the transfer clock voltage to the vertical CCD transfer electrode directly or indirectly, or controls the sequential switch that connects the clock transfer electrode of the vertical CCD and the clock power supply, captures the image. 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is arranged on both sides of the unit.
(1 9)、 直 C C Dのクロック転送電極に接続される 1行の垂直走査線は両 側からク口ック電圧を印加される事を特徵とする第 1 8項記載の固体撮像装置 c C2 0), 1 フィ ールド期間にすべての画素の信号電荷を出力し、 そして出力さ れた ^(偶）数番目の画素行の信号電荷だけを表示する事を特徵とする第 1項記(19) The solid-state imaging device c C2 according to item 18, characterized in that a single vertical scanning line connected to the clock transfer electrode of the direct CCD is applied with a clock voltage from both sides. 0), 1 The signal charges of all the pixels are output during the field period, and only the output signal charges of the ^ (even) th pixel rows are displayed.
•載の固体撮像装置。 ― . 一 . '. .• On-board solid-state imaging device. ―.
(2 1 )，インタライン転送 C C Dセンサ（ I Tセンサと略称される。 ）であり、 そして低照度時にフレーム蓄積動作を実施し、 高照度時にフィールド蓄積動作 を実施する事を特徼とする第 1項記載の固体撮像装置。 (21) Interline transfer CCD sensor (abbreviated as IT sensor), which performs frame accumulation at low illuminance and field accumulation at high illuminance. Item 13. The solid-state imaging device according to Item 1.
(2 2), I Tセンサであり、 そして垂直 C CDは信号電荷とノィズ電荷を交互 に出力する事を特徴とする第 1項記載の固体撮像装置。  (22) The solid-state imaging device according to claim 1, wherein the solid-state imaging device is an IT sensor, and the vertical CCD alternately outputs a signal charge and a noise charge.
(2 3)，^^電荷を垂直耘送しない期間に垂直 C CDに残留するノィズ電荷は クリァされるかまたは再配置される事を特徵とする第 1項記載の固体撮像装置。 (24)，画素から垂直 C CDの隣接する 2個の電位井戸または残留ノィズ電荷 を保持する電位井 Fによみだされた信号電荷を出力し、 そしてあらかじめ記億 されたスメァノィズ電圧と出力された信号電圧の差を検出する事を特徵とする 第 1項記載の固体撮像装置。 (2 3), the noise charge remaining on the vertical CCD during the period when ^^ charge is not sent vertically 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is cleared or rearranged. (24) The pixel outputs the signal charge generated by two adjacent potential wells of the vertical CCD or the potential well F holding the residual noise charge, and outputs the previously stored smearing voltage. 2. The solid-state imaging device according to claim 1, wherein a difference between signal voltages is detected.
(2 5), 2次元配列された複数の画素と、 画素列を兼ねるかまたは画素列と独 立に配置された垂直 C CDと； 水平 C CDを備え、 上記の垂直 C CDは画素列 の信号電荷を水平 CCDに転送する固体攝像装置において、  (25), a plurality of pixels arranged two-dimensionally, and a vertical CCD which also serves as a pixel column or is arranged independently of the pixel column; a horizontal CCD is provided; In a solid-state imaging device that transfers signal charges to a horizontal CCD,
飽和信号電荷を発生する画素（飽和画素と略称される。 ）を含む画素列（飽和画 素列と略称される。 ）のスメァノイズ電圧を記憶し、 そして少なくとも上記の 飽和画素列の一部の画素から発生する信号電圧から上記の記憶されたスメァノ ィズ電圧を差し引く事を特徵とする固体撮像装置。 A smear noise voltage of a pixel row (abbreviated as a saturated pixel row) including a pixel that generates a saturated signal charge (abbreviated as a saturated pixel row) is stored, and at least some of the pixels in the above-described saturated pixel row are stored. A solid-state imaging device characterized in that the stored smearing voltage is subtracted from a signal voltage generated from the image signal.
(2 6),飽和画素から発生する信号電荷から上記のスメァノィズ電圧を差し引 かない事を特徵とする第 2 5項記載の固体撮像装置。  (26) The solid-state imaging device according to item 25, wherein the above-mentioned smearing voltage is not subtracted from the signal charges generated from the saturated pixels.
(2 7)，飽和画素列の飽和画素から下流の画素から発生する一部または全部の 画素から発生する信号電圧から上記のスメァノィズ電圧を差し引かない事を特 徵とする第 25項記載の固体撮像装置。  (27) The solid-state imaging device described in paragraph 25, wherein the above-mentioned smearing voltage is not subtracted from the signal voltages generated from some or all pixels downstream from the saturated pixels in the saturated pixel column. apparatus.
(2 8),飽和画素を持たない画素列（非飽和画素列と略称される。 ）の画素から 発生する信号電 IEから上記のスメァノィズ電圧を差し引かない事を特徵とする 第 2 5項記載の gl体撮像装置。  (28) The feature described in Item 25 is that the above-mentioned smearing voltage is not subtracted from the signal voltage IE generated from the pixels in the pixel row having no saturated pixel (abbreviated as the non-saturated pixel row). gl body imaging device.
(2 9 ),.2次元配列された複数の画素と、 適素列を兼ねる.かまたは画素列と独 5)：に配置された垂直 C C Dと、 水平 C CDを備え、 上記の垂直 C CDは画素列 の信号電荷を水平 C CDに転送する固体撮像装置において、  (2 9), a two-dimensional array of multiple pixels and a row of pixels or a row of pixels and Germany 5): a vertical CCD and a horizontal CCD, and the above vertical CCD Is a solid-state imaging device that transfers signal charges in a pixel column to a horizontal CCD.
上記の水平 C CDは垂直帰線斯間にスメァノィズ電荷を第 1速度で水平転送し、 そして水平走査期間に信号電荷を第 2速度で水平転送し、 そして上記の第 1速 度は上記の第 2速度の 1 / 2以下の速度である事を特徵とする固体撮像装置 (3 0),垂直帰線期間に水平 C CDから出力されたスメァノィズは遂次比校形 AZD変換器によってデジタルメモリに入力される事を特徵とする第 2 9項記 載の固体撮像装置。 The horizontal CCD horizontally transfers the scan charges at the first speed during the vertical blanking, and transfers the signal charges horizontally at the second speed during the horizontal scanning period, and the first speed is at the second speed. Solid-state imaging device characterized in that the speed is less than 1/2 of 2 speed (30) The solid-state imaging device according to item 29, wherein the smears output from the horizontal CCD during the vertical retrace period are input to a digital memory by a successive ratio AZD converter.
(3 1 ),デジタルメモリから再生されたスメァノィズは遂次比皎形 A/D変換 ' 器の DZA変換器で D A変換される事を特徵とする第 3 0項記載の固体撮像  (31) The solid-state imaging device according to item 30, wherein the smears reproduced from the digital memory are D / A-converted by a DZA converter of a successive ratio A / D converter.
(3 2), 2次元配列された複数の画素と、 画素列を兼ねる垂直 C C Dを備え、 上記の垂直 C CDは画素列の信号電荷を水平 C CDに転送する固体撮像装置に おいて、 - 垂直 C C Dの隣接する 2個のクロック転送電極はチヤンネル領域またはチヤン ネルストヅプ領域の上方で接続され、 そして上記の 2個のクロック転送電極は 3倍以上の抵抗比を持つ事を特徵とする固体撮像装置。 (3 2), a solid-state imaging device that includes a plurality of pixels arranged two-dimensionally and a vertical CCD that also serves as a pixel column, and the above-described vertical CCD is a solid-state imaging device that transfers signal charges of the pixel column to a horizontal CCD. A solid-state imaging device characterized in that two adjacent clock transfer electrodes of a vertical CCD are connected above a channel region or a channel stop region, and the two clock transfer electrodes have a resistance ratio of three times or more. .
(3 3),上記の 2個のクロック転送電極はチャンネルス ト ップ領域の上方で接 続される事を特徵とす.る第 34項記載の固体撮像装置。  (33) The solid-state imaging device according to Item 34, characterized in that the two clock transfer electrodes are connected above a channel stop region.
PCT/JP1985/000038 1984-01-30 1985-01-30 Solid state pick-up device WO1985003398A1 (en)

Applications Claiming Priority (16)

Application Number Priority Date Filing Date Title
JP59015950A JPS60160271A (en) 1984-01-30 1984-01-30 Ccd area sensor
JP59/15950 1984-01-30
JP59/34839 1984-02-25
JP59034839A JPS60210079A (en) 1984-02-25 1984-02-25 Solid state area sensor
JP59/49685 1984-03-14
JP59049685A JPS60192471A (en) 1984-03-14 1984-03-14 Solid-state area sensor
JP59069835A JPS61105180A (en) 1984-04-06 1984-04-06 Solid-state area sensor
JP59/69835 1984-04-06
JP59091417A JPS60235591A (en) 1984-05-08 1984-05-08 Solid-state image pickup device
JP59/91417 1984-05-08
JP59/95314 1984-05-12
JP59095314A JPS60239181A (en) 1984-05-12 1984-05-12 Solid-state image pickup device
JP59/189970 1984-09-10
JP59189970A JPS6167376A (en) 1984-09-10 1984-09-10 Solid-state image pickup device
JP59211797A JPS6190576A (en) 1984-10-09 1984-10-09 Solid-state image pickup element
JP59/211797 1984-10-09

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5187912A (en) * 1975-01-30 1976-07-31 Sony Corp
JPS5264219A (en) * 1975-11-20 1977-05-27 Rca Corp Method of reducing effect of smear charge signal for charge coupled image pickup device
JPS59167186A (en) * 1983-03-11 1984-09-20 Shoichi Tanaka Solid-state image pickup device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5187912A (en) * 1975-01-30 1976-07-31 Sony Corp
JPS5264219A (en) * 1975-11-20 1977-05-27 Rca Corp Method of reducing effect of smear charge signal for charge coupled image pickup device
JPS59167186A (en) * 1983-03-11 1984-09-20 Shoichi Tanaka Solid-state image pickup device

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