JPH03101484A - Drive method for solid-state image pickup element - Google Patents
Drive method for solid-state image pickup elementInfo
- Publication number
- JPH03101484A JPH03101484A JP1237031A JP23703189A JPH03101484A JP H03101484 A JPH03101484 A JP H03101484A JP 1237031 A JP1237031 A JP 1237031A JP 23703189 A JP23703189 A JP 23703189A JP H03101484 A JPH03101484 A JP H03101484A
- Authority
- JP
- Japan
- Prior art keywords
- ccd
- voltage value
- voltage
- electrodes
- vertical ccd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 4
- 238000003384 imaging method Methods 0.000 claims 5
- 238000006243 chemical reaction Methods 0.000 claims 4
- 230000003287 optical effect Effects 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 16
- 229920005591 polysilicon Polymers 0.000 abstract description 16
- 238000009413 insulation Methods 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000005520 electrodynamics Effects 0.000 description 2
- 101000857682 Homo sapiens Runt-related transcription factor 2 Proteins 0.000 description 1
- 102100025368 Runt-related transcription factor 2 Human genes 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Abstract
Description
本発明はＣＣＤ型固体撮像素子における垂直ＣＣＤの最
大転送電荷量向上のための駆動法に関する。The present invention relates to a driving method for increasing the maximum transfer charge amount of a vertical CCD in a CCD solid-state image sensor.
【従来の技術１
従来、家庭用ビデオカメラ等に用いられる固体撮像素子
には、ＣＣＤ型固体撮像素子が広く用いられている。こ
の種のＣＣＤ型固体撮像素子については、アイ・ニス・
ニス・シー・シー ダイジェスト オブ テクニカル
ペーパーズ第９６頁から第９７頁（１９８５）（ＩＳＳ
ＣＣＤＩＧＥＳＴ ＯＦ ＴＥＣＨＮＩＣＡＬ
ＰＡＰＥＲ８，ｐ、９６−９７ （１９８５））におい
て論じられている。
上記文献に記載されているＣＣＤ型固体撮像素子の画素
の構造は第９図に示すように第１ポリシリコン２２並び
に第２層ポリシリコン２１を駆動電極とする垂直ＣＣＤ
とホトダイオードからなる。
本構造においては、垂直ＣＣＤの転送動作を確実に行う
ため、２層のポリシリコン電極はオーバーラツプ部を有
する。さらに、２層のポリシリコン電極間の絶縁を高い
信頼性で行うため、電極間の絶縁膜には、第２層ポリシ
リコン２１のゲート酸化膜形成時に第１層ポリシリコン
２２上に形成される酸化膜が用いられている。
また、垂直ＣＣＤは画素構造を複雑にすることなく信号
の読みだしを行うため、第１０図に示す三値パルスで駆
動される。垂直ブランキング期間にｖ２もしくは■４端
子に最高電圧ＶＨが印加され、ホトダイオードの信号電
荷は垂直ＣＣＤに転送される。この時、Ｖｌとｖ３端子
には最低電圧ＶＬが印加され、信号電荷が垂直ＣＣＤ内
で混ざりあうのを防いでいる。垂直走査期間にはｖｌか
らｖ４端子ｌこ中間電圧ＶＭと最低小電圧ＶＬが交互に
印加され、信号電荷は垂直ＣＣＤ内を転送される。
【発明が解決しようとする課題】
上記従来技術は、ホトダイオードから垂直ＣＣＤへの信
号電荷の転送時に、ポリシリコン電極間の絶縁膜に駆動
最高電圧ＶＨと最低電圧ＶＬの高い電圧差が加わるとい
う点について考慮がされておらず、高信頼性を得るため
にポリシリコン電極間の絶縁膜、ひいては垂直ＣＣＤの
ゲート酸化膜を薄くすることができないという問題があ
った。
本発明は、ポリシリコン電極間の絶縁膜に加わる電圧を
小さくすることにより、垂直ＣＣＤのゲート酸化膜を薄
くシ、垂直ＣＣＤの単位面積あたりの転送最大電荷量を
大きくすることを目的としている。[Prior Art 1] Conventionally, CCD type solid-state image sensors have been widely used as solid-state image sensors used in home video cameras and the like. Regarding this type of CCD type solid-state image sensor, eye, varnish,
Niss C C Digest of Technical
Papers, pages 96 to 97 (1985) (ISS
CCDIGEST OF TECHNICAL
PAPER 8, p, 96-97 (1985)). As shown in FIG. 9, the pixel structure of the CCD solid-state image sensor described in the above-mentioned document is a vertical CCD in which the first polysilicon layer 22 and the second layer polysilicon layer 21 are used as drive electrodes.
and a photodiode. In this structure, the two layers of polysilicon electrodes have an overlapping portion in order to ensure the vertical CCD transfer operation. Furthermore, in order to provide highly reliable insulation between the two layers of polysilicon electrodes, the insulating film between the electrodes is formed on the first layer polysilicon 22 when forming the gate oxide film of the second layer polysilicon 21. An oxide film is used. Further, the vertical CCD is driven by a ternary pulse shown in FIG. 10 in order to read out signals without complicating the pixel structure. During the vertical blanking period, the highest voltage VH is applied to the v2 or 4 terminal, and the signal charge of the photodiode is transferred to the vertical CCD. At this time, the lowest voltage VL is applied to the Vl and v3 terminals to prevent signal charges from mixing within the vertical CCD. During the vertical scanning period, the intermediate voltage VM and the lowest voltage VL are alternately applied to terminals v1 to v4, and signal charges are transferred within the vertical CCD. [Problems to be Solved by the Invention] The problem with the above conventional technology is that a large voltage difference between the highest driving voltage VH and the lowest voltage VL is applied to the insulating film between the polysilicon electrodes when signal charges are transferred from the photodiode to the vertical CCD. However, there was a problem in that the insulating film between the polysilicon electrodes, and even the gate oxide film of the vertical CCD, could not be made thinner in order to obtain high reliability. The present invention aims to reduce the voltage applied to the insulating film between polysilicon electrodes, thereby making the gate oxide film of the vertical CCD thinner and increasing the maximum amount of charge transferred per unit area of the vertical CCD.
上記目的を達成するために本発明においては。
ホトダイオードから垂直ＣＣＤへの信号電荷の転送時に
ある垂直ＣＣＤ電極に駆動最高電圧ＶＨを印加する時、
該電極に隣接する電極には垂直ＣＣＤ内の信号電荷転送
時の高い電圧である中間電圧値ＶＭを印加したものであ
る。
さらに、上記駆動法で信号電荷が垂直ＣＣＤ内で混ざり
あうのを防ぐために、最高電圧ＶＨを印加した電極並び
に該電極に隣接している電極を除いた少なくとも１電極
に垂直ＣＣＤ内の信号電荷転送時の低い電圧である最低
電圧値ＶＬを印加したものである。In order to achieve the above object, the present invention. When applying the highest driving voltage VH to a certain vertical CCD electrode during transfer of signal charges from the photodiode to the vertical CCD,
An intermediate voltage value VM, which is a high voltage during signal charge transfer in the vertical CCD, is applied to an electrode adjacent to this electrode. Furthermore, in order to prevent signal charges from mixing within the vertical CCD in the above driving method, signal charges within the vertical CCD are transferred to at least one electrode excluding the electrode to which the highest voltage VH is applied and the electrode adjacent to the electrode. The lowest voltage value VL, which is the lowest voltage at that time, is applied.
垂直ＣＣＤポリシリコン電極間の絶縁膜に加わる電圧は
、信号電荷の転送される垂直ＣＣＤ電極と該電極に隣接
する電極間では最高電圧ＶＨと中間電圧ＶＭの差、該電
極に隣接している電極と信号電荷が垂直ＣＣＤ内で混ざ
りあうのを防ぐための電極間では中間電圧ＶＭと最低電
圧ＶＬの差となる。これらの電圧は、従来開動法におけ
る電極間の絶縁膜に加わる最大電圧ＶＨ−ＶＬの約１／
２であり。
電極間の絶縁膜内の電界強度を一定とし信頼性を従来と
同等に保ちながら電極間の絶縁膜を約１７２にできるの
で、電極間の絶縁膜と同時に形成される垂直ＣＣＤゲー
ト酸化膜を約１／２にし、垂直ＣＣＤの単位面積あたり
の転送最大電荷量を大きくすることができる。The voltage applied to the insulating film between the vertical CCD polysilicon electrodes is the difference between the highest voltage VH and the intermediate voltage VM between the vertical CCD electrode to which signal charges are transferred and the electrode adjacent to this electrode, and the difference between the highest voltage VH and the intermediate voltage VM between the vertical CCD electrode where signal charges are transferred and the electrode adjacent to this electrode. There is a difference between the intermediate voltage VM and the lowest voltage VL between the electrodes to prevent the signal charges from mixing within the vertical CCD. These voltages are approximately 1/1/1 of the maximum voltage VH-VL applied to the insulating film between the electrodes in the conventional open method.
It is 2. Since the electric field strength in the insulating film between the electrodes can be kept constant and the reliability can be maintained at the same level as before, the thickness of the insulating film between the electrodes can be reduced to about 172 cm, so the vertical CCD gate oxide film formed at the same time as the insulating film between the electrodes can be reduced to about 172 cm. 1/2, and the maximum amount of charge transferred per unit area of the vertical CCD can be increased.
以下２本発明の一実施例を第１図から第３図により説明
する０本実施例では上記従来例と同様に。
素子構成はインターライン型ＣＣＤであり、垂直ＣＣＤ
電極構造はオーバーラツプ部を有する２Ｎポリシリコン
電極よりなり、垂直ＣＣＤは４相のＪ＝＜ルスにより駆
動される。
第１図は第９図のｖｌからｖ４端子に加える駆動パルス
の垂直ブランキング期間のタイミング。
第２図（、）は第９図Ａ−Ａ’の断面構造図、同図（ｂ
）は第１図の時刻ｔ１からｔ８の各電極下の電位図、第
３図は電極間絶縁膜の許容電界強度を一定としたときの
ゲート酸化膜厚と電極間絶縁膜の耐圧の関係を示す図で
ある。
垂直ブランキング期間に入るとｖ３端子電圧が最低電圧
ＶＬから中間電圧ＶＭになった後（時刻ｔｌ）、Ｖ２端
子電圧が中間電圧ＶＭから最高電圧ＶＨになり、ｎ行の
ホトダイオードの信号電荷が垂直ＣＣＤに転送される（
時刻ｔ２）、ついでｖ２端子電圧がＶＨからＶＭになり
、信号電荷はｖｌからｖ３端子電極下に蓄積される。こ
の時Ｖ４端子には最低電圧ＶＬが印加され、信号電荷が
垂直ＣＣＤ内で混ざりあうのを防いでいる（時刻ｔ３）
。
この後ｖ１端子電圧がＶＭからＶＬとなった後（時刻ｔ
４）、Ｖ２端子電圧がＶＭからＶＬになると同時にｖ４
端子電圧がＶＭからＶＬとなり。
さらにｖ１端子電圧がＶＬからＶＭとなり、信号電荷は
垂直ＣＣＤ内を２電極分移動する（時刻ｔ５）、ついで
ｖ４端子電圧が中間電圧ＶＭから最高電圧ＶＨになり、
ｎ＋１行のホトダイオードの信号電荷が垂直ＣＣＤに転
送される（時刻ｔ６）。
ついでｖ４端子電圧がＶＨからＶＭになり、信号電荷は
ｖ３からｖ１端子電極下に蓄積される。
この時ｖ２端子には最低電圧ＶＬが印加され、信号電荷
が垂直ＣＣＤ内で混ざりあうのを防いでいる（時刻ｔ７
）、この後ｖ３端子電圧がＶＭからＶＬとなった後、Ｖ
４端子電圧がＶＭからＶＬなると同時にｖ２端子電圧が
ＶＭからＶＬとなり。
信号電荷はｖｌとｖ２端子電極下に蓄積される（時刻ｔ
８）。
垂直走査期間にはｖｌからｖ４端子に中間電圧ＶＭと最
低小電圧ＶＬが交互に印加され、信号電荷は垂直ＣＣＤ
内を転送される。
本実施例によれば電極間の絶縁膜に加わる電圧はＶＨ−
ＶＭもしくはＶＭ−ＶＬとなる０通例垂直ＣＣＤ内の電
荷転送に必要な電圧振＠ＶＭ−ＶＬとホトダイオードか
ら垂直ＣＣＤへの信号読みだしに必要な電圧振１１１Ｖ
Ｈ−ＶＭはほぼ等しく。
電極間の絶縁膜に加わる電圧は従来のＶＨ−ＶＬの約１
７２となる。
この結果、第３図に示すように電極間の絶縁膜内の許容
電界強度を一定とすると電極間の絶縁膜を約１７２にで
きるので、電極間の絶縁膜と同時に形成される垂直ＣＣ
Ｄゲート酸化膜も約１７２にすることができる。
また、ホトダイオードから垂直ＣＣＤへの信号読みだし
時に最高電圧ＶＨのかかるｖ２もしくはｖ４端子につな
がる電極に隣接しないｖ４もしくは■２端子につながる
電極に最低電圧ＶＬを加えることにより、上記能動条件
を保ちながら信号電荷が垂直ＣＣＤ内で混ざりあうのを
防いでいる。
なお、垂直ＣＣＤ［動電横配線下で発生する暗電流が問
題となるときには、中間電圧を垂直ＣＣＤ１！動電極配
線下の半導体内の不純物と同型の電荷が蓄積状態となる
ように設定すれば良い、上記＋４１の実施例において中
間電圧をｐウェル２５の電圧に対し負にすることにより
、垂直ＣＣＤＩＩ動電極配線電極配線下蓄積され、低暗
電流化ができる。
さて、第１の実施例において垂直ＣＣＤ 駆動電極とＰ
ウェルとの容量結合により駆動時にＰウェルの電位変動
が起きシェーディングといわれる疑信号が生じることが
ある。第２．第３の実施例は。
このシェーディングを低減したものである。
以下、第２の実施例を第４図により説明する。
第４図は、第９図Ｂ−Ｂ’−Ｂ”に相当する部分の本実
施例の断面構造図である。本実施例においては、ホトダ
イオード間分離領域Ｂ−Ｂ’に厚い酸化膜２７を形成し
、垂直ｃ ＣＤ ＩＨ動動電上なる第１層ポリシリコン
層２２とＰウェル２５との結合容量を小さくシ、シェー
ディングを低減した。
なお、垂直ＣＣＤの飽和信号電荷の劣化要因となる垂直
ＣＣＤの狭チャネル効果の増加を防ぐために、ホトダイ
オードと垂直ＣＣＤ間の分離領域Ｂ′−Ｂ”には厚い酸
化膜は形成しない。
さらに１本実施例では、垂直ＣＣＤｎ−チャネル層２３
とｎ基板２６間のｐウェル層２５は少なくとも垂直ＣＣ
Ｄ ＩＩＫ動電極電極低電圧ＶＬが印加された時には空
乏化せず、Ｘ方向のＰウェル層２５の抵抗が増加するの
を防ぎシェーディングを低減している。
第３の実施例を第５図により説明する。
第５図は、素子駆動パルスを発生する素子外部の駆動回
路のブロック図である。本実施例においては、素子は垂
直走査期間は低出力インピーダンスの垂直走査期間ドラ
イバ３１により、垂直ブランキング期間は高出力インピ
ーダンスの垂直ブランキング期間ドライバ３２により駆
動される。これにより相補型の駆動パルスによりウェル
電位変動を抑圧できる垂直走査期間はもう一つの要求で
ある高速性を有する駆動パルスを実現し、高速性の要求
されない垂直ブランキング−期間はパルスを鈍らせるこ
とによりウェルの電位変動を抑圧できシェーディングを
低減できる。
なお、垂直走査期間と垂直ブランキング期間のインピー
ダンスの切り替えは素子外部のドライバを１個にし素子
内部で行っても良い、さらに９本実施例では駆動パルス
の各相の駆動電極とウェル間の結合容量をほぼ同一とし
、相補型の駆動パルスによるウェル電位変動を抑圧効果
を高め、シェーディングを低減している。
また２本発明は、垂直ＣＣＤの駆動パルスの相数に依ら
ず実施できる。以下、ＴＶ学会技報１３巻１１号ＥＤ８
９−１７第７３頁から第７８頁（１９８９）に記載され
た６相駆動の垂直ＣＣＤに適用した第４の実施例を、第
６図により説明する。
第６図（ａ）は駆動パルスタイミング、同図（ｂ）は同
図（ａ）の時刻ＴＩＡ、Ｔ２Ａ、ＴＩＢ、Ｔ２Ｂの各電
極下の電位図である。本実施例においてもホトダイオー
ドから垂直ＣＣＤへの信号読みだし時に最高電圧のかか
る電極に隣接した電極には中間電圧を加えることにより
電極間絶縁膜にかかる電圧を低減しゲート酸化膜を薄く
することができる。
さらに２本発明は、素子構成に依らず実施できる。第７
図は９本発明をＴＶ学会全国大会予稿集３−６ （１９
８７）に記載されたフレームインターライン型ＣＣＤに
適用した第５の実施例の駆動パルスタイミング図である
。
本実施例においても電極間絶縁膜にかかる電圧を低減し
ゲート酸化膜を薄くすることができる。
また、第６の実施例は２本発明を、上記フレームインタ
ーライン型ＣＣＤの電子シャッタ駆動でも実施したもの
である。第８図は２本実施例の駆動パルスタイミング図
である。本実施例においては水平ブランキング期間の不
要電荷掃きたしのためのホトダイオードから垂直ＣＣＤ
への信号読みだし時には垂直ＣＣＤ内で電荷が混ざって
も良いのでφＡ４は一定の中間電圧になっている。
【発明の効果）
本発明に依れば、信頼性を従来と同等に保ちながら、垂
直ＣＣＤゲート酸化膜を約１／２とし、垂直ＣＣＤの単
位面積あたりの転送最大電荷量を大きくすることができ
る。
第１図、第６図（ａ）、第７図、第８図は本発明の一実
施例の湘動パルスタイミング図、第２図（ａ）、第４図
は本発明の一実施例の第９図Ａ−Ａ′、第９図Ｂ−Ｂ’
−Ｂ” （７）断面構造図、第２図（ｂ）、第６図（
ｂ）はそれぞれ第１図の時刻ｔ１からｔ８の、第６図（
ａ）の時刻Ｔ−ＩＡ、Ｔ２Ａ、ＴＩＢ、Ｔ２Ｂの各電極
下の電位図、第３図はゲー・ト酸化膜厚と電極間絶縁膜
の耐圧の関係を示す図、第５図は本発明の一実施例の素
子即動パルスを発生する素子外部の駆動回路のブロック
図、第９図は従来のＣＣＤ型固体撮像素子の画素の平面
構造図、第１０図は従来のＣＣＤ型固体撮像素子の駆動
パルスタイミング図である。
符号の説明
Ｖｌ、Ｖ２．Ｖ３．Ｖ４．ΦＶＩＡ、ΦＶ２゜１！１Ｖ
３Ａ、（ｔｌＶ４．（りＶＩＢ、 ΦＶ３Ｂ、（＋）Δ
１゜ΦＡ２．ΦＡ３．ΦＡ４・・・駆動パルス端子、Ｖ
Ｌ・・・最低電圧、ＶＭ・・・中間電圧、ＶＨ・・・最
高電圧。
２１・・・第２層ポリシリコン、２２・・・第１層ポリ
シリコン、２３・・・ｎ−チャネル、２４・・・ｐ十層
、２５・・・ｐウェル、２６・・・ｎ基板、２７・・・
厚い酸化膜。
２８・・・ｐ＋チャネルストップ、３１・・・垂直走査
期間ドライバ、３２・・・垂直ブランキング期間ドライ
バ
を二ｔ？
。−９０
乎
図
半ｂｒ′ｊＪ
〃
ｑＯ６ρ とρ
γ′”−ト帆化穫４（’ｈ＃Ｉ）
０
不
図
峯ｙ
図
φＡｌ１−
率
？
図
際７図Two embodiments of the present invention will be described below with reference to FIGS. 1 to 3. This embodiment is similar to the conventional example described above. The element configuration is an interline type CCD, and a vertical CCD.
The electrode structure consists of 2N polysilicon electrodes with overlapping portions, and the vertical CCD is driven by four-phase J=<Rus. FIG. 1 shows the timing of the vertical blanking period of the drive pulses applied to the vl to v4 terminals in FIG. 9. Figure 2 (,) is a cross-sectional structural diagram of Figure 9 A-A', and the same figure (b
) is the potential diagram under each electrode from time t1 to t8 in Fig. 1, and Fig. 3 shows the relationship between the gate oxide film thickness and the breakdown voltage of the interelectrode insulating film when the allowable electric field strength of the interelectrode insulating film is constant. FIG. When entering the vertical blanking period, after the V3 terminal voltage changes from the lowest voltage VL to the intermediate voltage VM (time tl), the V2 terminal voltage changes from the intermediate voltage VM to the highest voltage VH, and the signal charge of the photodiode in the n row becomes vertical. transferred to CCD (
At time t2), the v2 terminal voltage then changes from VH to VM, and the signal charge is accumulated from vl to under the v3 terminal electrode. At this time, the lowest voltage VL is applied to the V4 terminal to prevent signal charges from mixing within the vertical CCD (time t3).
. After this, the v1 terminal voltage changes from VM to VL (time t
4) At the same time as the V2 terminal voltage changes from VM to VL, v4
The terminal voltage changes from VM to VL. Further, the v1 terminal voltage changes from VL to VM, and the signal charge moves by two electrodes in the vertical CCD (time t5).Then, the v4 terminal voltage changes from the intermediate voltage VM to the highest voltage VH.
The signal charge of the photodiode in the n+1 row is transferred to the vertical CCD (time t6). Then, the v4 terminal voltage changes from VH to VM, and the signal charge is accumulated from v3 to under the v1 terminal electrode. At this time, the lowest voltage VL is applied to the v2 terminal to prevent signal charges from mixing within the vertical CCD (time t7
), then after the v3 terminal voltage changes from VM to VL, V
At the same time as the 4-terminal voltage changes from VM to VL, the v2 terminal voltage changes from VM to VL. Signal charges are accumulated under the vl and v2 terminal electrodes (at time t
8). During the vertical scanning period, the intermediate voltage VM and the lowest voltage VL are applied alternately from vl to v4 terminals, and the signal charge is applied to the vertical CCD.
Transferred within. According to this embodiment, the voltage applied to the insulating film between the electrodes is VH-
VM or VM-VL is 0, which is usually the voltage swing required for charge transfer in the vertical CCD @VM-VL, and the voltage swing 111V required for reading the signal from the photodiode to the vertical CCD.
H-VM is almost equal. The voltage applied to the insulating film between the electrodes is approximately 1 of the conventional VH-VL.
It becomes 72. As a result, as shown in Fig. 3, if the allowable electric field strength in the insulating film between the electrodes is kept constant, the insulating film between the electrodes can be approximately 172 cm, so the vertical CC is formed simultaneously with the insulating film between the electrodes.
The D gate oxide can also be about 172 mm. In addition, when reading signals from the photodiode to the vertical CCD, by applying the lowest voltage VL to the electrode connected to the v4 or ■2 terminal that is not adjacent to the electrode connected to the v2 or v4 terminal to which the highest voltage VH is applied, it is possible to maintain the above active condition. This prevents signal charges from mixing within the vertical CCD. Note that when the dark current generated under the vertical CCD [electrodynamic horizontal wiring becomes a problem, the intermediate voltage is set to the vertical CCD1! Vertical CCD II movement can be achieved by making the intermediate voltage negative with respect to the voltage of the p-well 25 in the +41 embodiment described above. Electrode wiring Accumulates under the electrode wiring, resulting in low dark current. Now, in the first embodiment, the vertical CCD drive electrode and P
Due to capacitive coupling with the well, the potential of the P well may fluctuate during driving, resulting in a false signal called shading. Second. The third example is. This shading is reduced. The second embodiment will be explained below with reference to FIG. FIG. 4 is a cross-sectional structural diagram of this embodiment of a portion corresponding to BB'-B'' in FIG. This reduces the coupling capacitance between the first layer polysilicon layer 22 on the vertical CCD IH electrodynamic and P well 25 and reduces shading. To prevent an increase in the narrow channel effect of the CCD, no thick oxide film is formed in the isolation region B'-B'' between the photodiode and the vertical CCD. Furthermore, in this embodiment, the vertical CCD n-channel layer 23
The p-well layer 25 between the n-substrate 26 and the vertical CC
D IIK active electrode electrode When low voltage VL is applied, it is not depleted, preventing the resistance of the P well layer 25 in the X direction from increasing and reducing shading. The third embodiment will be explained with reference to FIG. FIG. 5 is a block diagram of a drive circuit outside the device that generates device drive pulses. In this embodiment, the element is driven by a vertical scanning period driver 31 with low output impedance during the vertical scanning period, and by a vertical blanking period driver 32 with high output impedance during the vertical blanking period. As a result, during the vertical scanning period during which well potential fluctuations can be suppressed using complementary drive pulses, a drive pulse with high speed, which is another requirement, can be realized, and during the vertical blanking period, where high speed is not required, the pulse is made dull. As a result, potential fluctuations in the well can be suppressed and shading can be reduced. Note that the impedance switching between the vertical scanning period and the vertical blanking period may be performed inside the device by using one driver outside the device.Furthermore, in this embodiment, the switching between the drive electrode of each phase of the drive pulse and the well The capacitances are made almost the same, increasing the effect of suppressing well potential fluctuations caused by complementary drive pulses, and reducing shading. Furthermore, the present invention can be implemented regardless of the number of phases of the driving pulses of the vertical CCD. The following is TV Society Technical Report Volume 13 No. 11 ED8
A fourth embodiment applied to the six-phase drive vertical CCD described in 9-17, pages 73 to 78 (1989) will be described with reference to FIG. FIG. 6(a) is a drive pulse timing, and FIG. 6(b) is a potential diagram under each electrode at times TIA, T2A, TIB, and T2B in FIG. 6(a). In this embodiment as well, when reading signals from the photodiode to the vertical CCD, an intermediate voltage is applied to the electrode adjacent to the electrode to which the highest voltage is applied, thereby reducing the voltage applied to the interelectrode insulating film and thinning the gate oxide film. can. Furthermore, the present invention can be implemented regardless of the device configuration. 7th
Figure 9 shows the present invention in the proceedings of the TV Society National Conference 3-6 (19
87) is a drive pulse timing diagram of the fifth embodiment applied to the frame interline type CCD described in 87). In this embodiment as well, the voltage applied to the interelectrode insulating film can be reduced and the gate oxide film can be made thinner. Further, in the sixth embodiment, the two aspects of the present invention are implemented in the electronic shutter drive of the above-mentioned frame interline type CCD. FIG. 8 is a drive pulse timing diagram of the two embodiments. In this embodiment, the vertical CCD is connected from the photodiode to sweep away unnecessary charges during the horizontal blanking period.
Since charges may be mixed in the vertical CCD when reading a signal to , φA4 is set to a constant intermediate voltage. [Effects of the Invention] According to the present invention, it is possible to reduce the vertical CCD gate oxide film to about 1/2 and increase the maximum amount of charge transferred per unit area of the vertical CCD, while maintaining the same reliability as the conventional one. can. 1, 6(a), 7, and 8 are floating pulse timing diagrams of one embodiment of the present invention, and FIG. 2(a), and 4 are diagrams of one embodiment of the present invention. Figure 9 A-A', Figure 9 B-B'
-B” (7) Cross-sectional structure diagram, Fig. 2 (b), Fig. 6 (
b) from time t1 to t8 in FIG. 1 and FIG. 6 (
The potential diagram under each electrode at times T-IA, T2A, TIB, and T2B in a), FIG. 3 is a diagram showing the relationship between the gate oxide film thickness and the withstand voltage of the interelectrode insulating film, and FIG. A block diagram of a drive circuit outside the device that generates instantaneous pulses in one embodiment of the device; FIG. 9 is a plan view of a pixel structure of a conventional CCD solid-state image sensor; and FIG. 10 is a diagram of a conventional CCD solid-state image sensor. FIG. 3 is a drive pulse timing diagram of FIG. Explanation of symbols Vl, V2. V3. V4. ΦVIA, ΦV2゜1!1V
3A, (tlV4.(RIVIB, ΦV3B, (+)Δ
1゜ΦA2. ΦA3. ΦA4...Drive pulse terminal, V
L: lowest voltage, VM: intermediate voltage, VH: highest voltage. 21... Second layer polysilicon, 22... First layer polysilicon, 23... N-channel, 24... P ten layer, 25... P well, 26... N substrate, 27...
thick oxide film. 28...p+channel stop, 31...vertical scanning period driver, 32...vertical blanking period driver 2t? . -90 乎囯halfbr'jJ 〃 qO6ρ and ρ γ′''-Tohokaretsu 4 ('h#I) 0 Futumine y FigureφAl1- Rate? Figure 7
Claims (1)
子群と、該素子に蓄積された光信号電荷を順次転送する
ＣＣＤを集積化した固体撮像素子において、該ＣＣＤを
構成する電極に第一の電圧値と第二の電圧値を印加する
ことにより該ＣＣＤ内を信号電荷を転送し、該ＣＣＤを
構成する電極に第三の電圧値を印加することにより該光
電変換素子から該ＣＣＤへの信号電荷を転送する際に、
該ＣＣＤの隣接する２電極に該第一から第三の電圧値の
うち電圧差が最大となる２電圧値を同時に印加しないこ
とを特徴とする固体撮像素子の駆動法。 ２、同一半導体基板上に光学情報を取り出す光電変換素
子群と、該素子に蓄積された光信号電荷を順次転送する
ＣＣＤを集積化した固体撮像素子において、該ＣＣＤを
構成する電極に第一の電圧値と第二の電圧値を印加する
ことにより該ＣＣＤ内を信号電荷を転送し、該ＣＣＤを
構成する電極に第三の電圧値を印加することにより該光
電変換素子から該ＣＣＤへの信号電荷を転送する際に、
該ＣＣＤを構成する電極に第三の電圧値を印加する時、
該電極に隣接する電極に第一の電圧値と第二の電圧値の
うち第三の電圧値との電圧差の小さい電圧値を印加する
ことを特徴する固体撮像像素子の駆動法。 ３、請求項１もしくは２記載の固体撮像像素子の駆動法
において、第三の電圧値を印加する電極に隣接していな
い電極には、第一の電圧値と第二の電圧値のうち第三の
電圧値との電圧差の大きい電圧値を印加することを特徴
とする固体撮像像素子の駆動法。[Claims] 1. In a solid-state imaging device in which a group of photoelectric conversion elements for extracting optical information and a CCD for sequentially transferring optical signal charges accumulated in the elements are integrated on the same semiconductor substrate, the CCD is configured. A signal charge is transferred within the CCD by applying a first voltage value and a second voltage value to the electrodes forming the photoelectric conversion element, and a third voltage value is applied to the electrodes constituting the CCD. When transferring signal charges from to the CCD,
A method for driving a solid-state imaging device, characterized in that two voltage values having the maximum voltage difference among the first to third voltage values are not simultaneously applied to two adjacent electrodes of the CCD. 2. In a solid-state image sensor that integrates a group of photoelectric conversion elements that extract optical information on the same semiconductor substrate and a CCD that sequentially transfers optical signal charges accumulated in the element, a first electrode is attached to the electrode constituting the CCD. A signal charge is transferred within the CCD by applying a voltage value and a second voltage value, and a signal is transferred from the photoelectric conversion element to the CCD by applying a third voltage value to the electrodes constituting the CCD. When transferring charge,
When applying a third voltage value to the electrodes constituting the CCD,
A method for driving a solid-state imaging device, comprising applying a voltage value having a small voltage difference between a first voltage value and a third voltage value among the second voltage values to an electrode adjacent to the electrode. 3. In the method for driving a solid-state imaging device according to claim 1 or 2, the electrode that is not adjacent to the electrode to which the third voltage value is applied is supplied with the first voltage value of the first voltage value and the second voltage value. A method for driving a solid-state imaging device, characterized by applying a voltage value having a large voltage difference from the voltage value of the third voltage value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1237031A JPH03101484A (en) | 1989-09-14 | 1989-09-14 | Drive method for solid-state image pickup element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1237031A JPH03101484A (en) | 1989-09-14 | 1989-09-14 | Drive method for solid-state image pickup element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03101484A true JPH03101484A (en) | 1991-04-26 |
Family
ID=17009371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1237031A Pending JPH03101484A (en) | 1989-09-14 | 1989-09-14 | Drive method for solid-state image pickup element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03101484A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7038723B1 (en) | 1999-04-26 | 2006-05-02 | Matsushita Electric Industrial Co., Ltd. | Solid state imaging device, method for driving the same and camera using the same |
| JP2009153057A (en) * | 2007-12-21 | 2009-07-09 | Panasonic Corp | Solid-state imaging device and method of driving the same, and camera |
-
1989
- 1989-09-14 JP JP1237031A patent/JPH03101484A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7038723B1 (en) | 1999-04-26 | 2006-05-02 | Matsushita Electric Industrial Co., Ltd. | Solid state imaging device, method for driving the same and camera using the same |
| JP2009153057A (en) * | 2007-12-21 | 2009-07-09 | Panasonic Corp | Solid-state imaging device and method of driving the same, and camera |
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